Hi Jonas,

On 2024/6/7 18:27, Kever Yang wrote:

On 2024/5/12 20:16, Jonas Karlman wrote:

...

GPIO IOMUX control is located at PMU2_IOC or BUS_IOC offset on RK3588.

Based on Linux commit fdc33eba11c5 ("pinctrl/rockchip: add rk3588 support").

Compared to the Linux commit, this include a fix so that the iomux of GPIO0_B4-D7 is reported correctly.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

I have apply the first 3 patches of this patch for master, and please rebase other patches for next.

Thanks,

- Kever

Thanks,

• Kever

...

---

The fix to report correct iomux for GPIO0_B4-D7 will be sent to Linux.

.../pinctrl/rockchip/pinctrl-rockchip-core.c  | 24 ++++++++++++++++++-   1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 973e6a4f6db9..efc2070d32d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -14,10 +14,10 @@   #include <linux/libfdt.h>     #include "pinctrl-rockchip.h" +#include <dt-bindings/pinctrl/rockchip.h>     #define MAX_ROCKCHIP_PINS_ENTRIES    30   #define MAX_ROCKCHIP_GPIO_PER_BANK      32 -#define RK_FUNC_GPIO                    0     static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)   { @@ -147,6 +147,28 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)       if (bank->recalced_mask & BIT(pin))           rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);   +    if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) { +        if (bank->bank_num == 0) { +            if (pin >= RK_PB4 && pin <= RK_PD7) { +                u32 reg0 = 0;

+                reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ +                ret = regmap_read(regmap, reg0, &val); +                if (ret) +                    return ret;

+                ret = ((val >> bit) & mask); +                if (ret != 8) +                    return ret;

+                reg = reg + 0x8000; /* BUS_IOC_BASE */ +                regmap = priv->regmap_base; +            } +        } else if (bank->bank_num > 0) { +            reg += 0x8000; /* BUS_IOC_BASE */ +        } +    }

ret = regmap_read(regmap, reg, &val);       if (ret)           return ret;

On 2024/5/12 20:16, Jonas Karlman wrote:

Use syscon_regmap_lookup_by_phandle() to simplify the code.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

.../pinctrl/rockchip/pinctrl-rockchip-core.c | 39 ++++++------------- 1 file changed, 12 insertions(+), 27 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index efc2070d32d9..b7c08c23311f 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -11,6 +11,7 @@ #include <syscon.h> #include <fdtdec.h> #include <linux/bitops.h> +#include <linux/err.h> #include <linux/libfdt.h>

#include "pinctrl-rockchip.h" @@ -672,37 +673,21 @@ int rockchip_pinctrl_probe(struct udevice *dev) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl;

• struct udevice *syscon;

• struct regmap *regmap;

• int ret = 0;

• /* get rockchip grf syscon phandle */

• ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",

• 			   &syscon);
  

• if (ret) {

• debug("unable to find rockchip,grf syscon device (%d)\n", ret);
  

• return ret;
  

• priv->regmap_base =

• 	syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
  

• if (IS_ERR(priv->regmap_base)) {

• debug("unable to find rockchip,grf regmap\n");
  

• return PTR_ERR(priv->regmap_base);
  

  }

• /* get grf-reg base address */
• regmap = syscon_get_regmap(syscon);
• if (!regmap) {

• debug("unable to find rockchip grf regmap\n");
  

• return -ENODEV;
  

• }
• priv->regmap_base = regmap;
• /* option: get pmu-reg base address */
• ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",

• 			   &syscon);
  

• if (!ret) {

• /* get pmugrf-reg base address */
  

• regmap = syscon_get_regmap(syscon);
  

• if (!regmap) {
  

• 	debug("unable to find rockchip pmu regmap\n");
  

• 	return -ENODEV;
  

• if (dev_read_bool(dev, "rockchip,pmu")) {

• priv->regmap_pmu =
  

• 	syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu");
  

• if (IS_ERR(priv->regmap_pmu)) {
  

• 	debug("unable to find rockchip,pmu regmap\n");
  

• 	return PTR_ERR(priv->regmap_pmu);
  

  }

• priv->regmap_pmu = regmap;
  

  }

  ctrl = rockchip_pinctrl_get_soc_data(dev);

On 2024/5/12 20:16, Jonas Karlman wrote:

Add a way to get_gpio_mux() based on the pinctrl pin offset, use -1 as banknum to use the pinctrl pin offset mode instead of bank pin offset.

This mode will be used by the gpio driver to ensure a pin used by gpio request() and get_function() ops always refer to the same pinctrl pin.

Also add verify_config() of banknum and index to avoid an out of range access of the pin_banks array, i.e. with gpio6 on rk3066a.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

The pin_to_mux() helper will be used in the get_pin_muxing() ops added in a later patch to support the pinmux status cmd.

---

.../pinctrl/rockchip/pinctrl-rockchip-core.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b7c08c23311f..1a8eec19d268 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -194,10 +194,30 @@ static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, return NULL; }

+static int rockchip_pin_to_mux(struct udevice *dev, unsigned int pin) +{

• struct rockchip_pin_bank *bank;
• bank = rockchip_pin_to_bank(dev, pin);
• if (!bank)

• return -EINVAL;
  

• return rockchip_get_mux(bank, pin - bank->pin_base);

+}

• static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index)

-{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); +{

• struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl = priv->ctrl;

• int ret;

• if (banknum == -1)

• return rockchip_pin_to_mux(dev, index);
  

• ret = rockchip_verify_config(dev, banknum, index);

• if (ret)

• return ret;
  
  

  return rockchip_get_mux(&ctrl->pin_banks[banknum], index); }

On 2024/5/12 20:16, Jonas Karlman wrote:

Get pinctrl device from gpio-ranges phandle when the property exists, fallback to get the first pinctrl device.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/gpio/rk_gpio.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 956894501633..8f8f21acc2f5 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -191,12 +191,6 @@ static int rockchip_gpio_probe(struct udevice *dev)

priv->regs = dev_read_addr_ptr(dev);

• if (CONFIG_IS_ENABLED(PINCTRL)) {

• ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
  

• if (ret)
  

• 	return ret;
  

• }
• /*
  • If "gpio-ranges" is present in the devicetree use it to parse
  • the GPIO bank ID, otherwise use the legacy method.

@@ -204,16 +198,33 @@ static int rockchip_gpio_probe(struct udevice *dev) ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", NULL, 3, 0, &args);

• if (!ret || ret != -ENOENT) {

• if (!ret) { uc_priv->gpio_count = args.args[2]; priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;

• } else {

• if (CONFIG_IS_ENABLED(PINCTRL)) {
  

• 	ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,
  

• 					  args.node,
  

• 					  &priv->pinctrl);
  

• 	if (ret)
  

• 		return ret;
  

• }
  

• } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; ret = dev_read_alias_seq(dev, &priv->bank); if (ret) { end = strrchr(dev->name, '@'); priv->bank = trailing_strtoln(dev->name, end); }

• if (CONFIG_IS_ENABLED(PINCTRL)) {
  

• 	ret = uclass_first_device_err(UCLASS_PINCTRL,
  

• 				      &priv->pinctrl);
  

• 	if (ret)
  

• 		return ret;
  

• }
  

• } else {

• return ret;
  

  }

  priv->name[0] = 'A' + priv->bank;

On 2024/5/12 20:16, Jonas Karlman wrote:

Use the pinctrl pin offset to get_gpio_mux() to remove the bank num dependency and instead only use the bank num to assign a bank name.

Most Rockchip SoCs use all 32 pins of each gpio controller, meaning the pinctrl pin offset typically is aligned to 32.

However, for gpio0 on RK3288 only 24 pins are used meaning the pinctrl pin offset start at pin 24 for gpio1. Use DIV_ROUND_UP to get the 32 pin aligned bank num.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/gpio/rk_gpio.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 8f8f21acc2f5..a3691ad25b78 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -35,7 +35,7 @@ enum { struct rockchip_gpio_priv { void __iomem *regs; struct udevice *pinctrl;

• int bank;

• int pfc_offset; char name[2]; u32 version; };

@@ -109,7 +109,8 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) int ret;

if (CONFIG_IS_ENABLED(PINCTRL)) {

• ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
  

• ret = pinctrl_get_gpio_mux(priv->pinctrl, -1,
  

• 			   priv->pfc_offset + offset);
  

  if (ret < 0) return ret; else if (ret != RK_FUNC_GPIO)

@@ -187,7 +188,7 @@ static int rockchip_gpio_probe(struct udevice *dev) struct rockchip_gpio_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; char *end;

• int ret;

• int bank, ret;

  priv->regs = dev_read_addr_ptr(dev);

@@ -200,7 +201,8 @@ static int rockchip_gpio_probe(struct udevice *dev) 0, &args); if (!ret) { uc_priv->gpio_count = args.args[2];

• priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
  

• bank = DIV_ROUND_UP(args.args[1], ROCKCHIP_GPIOS_PER_BANK);
  

• priv->pfc_offset = args.args[1];
  
  

  if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,

@@ -211,11 +213,12 @@ static int rockchip_gpio_probe(struct udevice *dev) } } else if (ret == -ENOENT || !CONFIG_IS_ENABLED(PINCTRL)) { uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;

• ret = dev_read_alias_seq(dev, &priv->bank);
  

• ret = dev_read_alias_seq(dev, &bank);
  

  if (ret) { end = strrchr(dev->name, '@');

• 	priv->bank = trailing_strtoln(dev->name, end);
  

• 	bank = trailing_strtoln(dev->name, end);
  

  }

• priv->pfc_offset = bank * ROCKCHIP_GPIOS_PER_BANK;
  
  

  if (CONFIG_IS_ENABLED(PINCTRL)) { ret = uclass_first_device_err(UCLASS_PINCTRL,

@@ -227,7 +230,7 @@ static int rockchip_gpio_probe(struct udevice *dev) return ret; }

• priv->name[0] = 'A' + priv->bank;

• priv->name[0] = 'A' + bank; uc_priv->bank_name = priv->name;

  priv->version = readl(priv->regs + VER_ID_V2);

On 2024/5/12 20:16, Jonas Karlman wrote:

Add get_pins_count(), get_pin_name() and get_pin_muxing() ops to support the pinmux status cmd.

=> pinmux dev pinctrl dev: pinctrl => pinmux status GPIO0_A0 : gpio GPIO0_A1 : func-1 GPIO0_A2 : gpio GPIO0_A3 : gpio GPIO0_A4 : func-1 GPIO0_A5 : gpio GPIO0_A6 : gpio GPIO0_A7 : func-1 GPIO0_B0 : gpio GPIO0_B1 : func-1 GPIO0_B2 : func-1 GPIO0_B3 : gpio [...]

The change to use ENOENT for unrouted pins also help hide a "Error -22" message for unrouted pins using the gpio status -a cmd.

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

.../pinctrl/rockchip/pinctrl-rockchip-core.c | 50 ++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 1a8eec19d268..fa24de37b443 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -127,7 +127,7 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)

if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { debug("pin %d is unrouted\n", pin);

• return -EINVAL;
  

• return -ENOENT;
  

  }

  if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)

@@ -194,6 +194,32 @@ static struct rockchip_pin_bank *rockchip_pin_to_bank(struct udevice *dev, return NULL; }

+static int rockchip_pinctrl_get_pins_count(struct udevice *dev) +{

• struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
• struct rockchip_pin_ctrl *ctrl = priv->ctrl;
• return ctrl->nr_pins;

+}

+static const char *rockchip_pinctrl_get_pin_name(struct udevice *dev,

• 				 unsigned int selector)
  

+{

• static char name[PINNAME_SIZE];
• struct rockchip_pin_bank *bank;
• unsigned int index;
• bank = rockchip_pin_to_bank(dev, selector);
• if (!bank)

• return NULL;
  

• index = selector - bank->pin_base;
• snprintf(name, sizeof(name), "GPIO%u_%c%u",

•  bank->bank_num, 'A' + (index / 8), index % 8);
  

• return name;

+}

• static int rockchip_pin_to_mux(struct udevice *dev, unsigned int pin) { struct rockchip_pin_bank *bank;

@@ -222,6 +248,25 @@ static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, return rockchip_get_mux(&ctrl->pin_banks[banknum], index); }

+static int rockchip_pinctrl_get_pin_muxing(struct udevice *dev,

• 			   unsigned int selector,
  

• 			   char *buf, int size)
  

+{

• int mux;
• mux = rockchip_pin_to_mux(dev, selector);
• if (mux == -ENOENT)

• strlcpy(buf, "unrouted", size);
  

• else if (mux < 0)

• return mux;
  

• else if (mux)

• snprintf(buf, size, "func-%d", mux);
  

• else

• strlcpy(buf, "gpio", size);
  

• return 0;

+}

• static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux) {

@@ -571,8 +616,11 @@ static int rockchip_pinctrl_set_state(struct udevice *dev, }

const struct pinctrl_ops rockchip_pinctrl_ops = {

• .get_pins_count = rockchip_pinctrl_get_pins_count,
• .get_pin_name = rockchip_pinctrl_get_pin_name, .set_state = rockchip_pinctrl_set_state, .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
• .get_pin_muxing = rockchip_pinctrl_get_pin_muxing, .gpio_request_enable = rockchip_pinctrl_gpio_request_enable, };

On 2024/5/12 20:16, Jonas Karlman wrote:

Add gpio-ranges props to supported SoCs based on the following Linux patches:

ARM: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/26007385-81dc-9961-05d5-8b9a0969d0b6@gmail.com/

arm64: dts: rockchip: add gpio-ranges property to gpio nodes https://lore.kernel.org/all/18c8c89a-9962-40f0-814f-81e2c420c957@gmail.com/

For RK3066 and RK3288 the gpio-ranges props is adjusted to match https://lore.kernel.org/all/541b7633-af3b-4392-ac29-7ee1f2c6f943@kwiboo.se/

Re-enable gpio6 on RK3066 now that the pinctrl pin offset is used with get_gpio_mux().

Signed-off-by: Jonas Karlman jonas@kwiboo.se

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

Cc: Johan Jonker jbx6244@gmail.com

arch/arm/dts/rk3036-u-boot.dtsi | 12 ++++++++++++ arch/arm/dts/rk3066a-u-boot.dtsi | 3 +-- arch/arm/dts/rk3128-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk322x-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3288-u-boot.dtsi | 33 ++++++++++++++++++++++++++++++++ arch/arm/dts/rk3308-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rk3328-u-boot.dtsi | 13 +++++++++++++ arch/arm/dts/rk3368-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/rv1108-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/rv1126-u-boot.dtsi | 14 ++++++++++++++ 11 files changed, 177 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3036-u-boot.dtsi b/arch/arm/dts/rk3036-u-boot.dtsi index 41ac054b81e8..3e788187f630 100644 --- a/arch/arm/dts/rk3036-u-boot.dtsi +++ b/arch/arm/dts/rk3036-u-boot.dtsi @@ -4,3 +4,15 @@ */

#include "rockchip-u-boot.dtsi"

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5e..35b52d6fb7f3 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -24,6 +24,5 @@ };

&gpio6 {

• status = "disabled";

• gpio-ranges = <&pinctrl 0 160 16>; };

diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi index 6d1965e6b520..dd1208e7cf40 100644 --- a/arch/arm/dts/rk3128-u-boot.dtsi +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -14,6 +14,22 @@ bootph-all; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

• &grf { bootph-all; };

diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi index aea917544b1c..f0e2a1f95aa0 100644 --- a/arch/arm/dts/rk322x-u-boot.dtsi +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -47,6 +47,22 @@ max-frequency = <150000000>; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

• &grf { bootph-all; };

diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7b..0f8053a8b690 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -95,8 +95,41 @@ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 24>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 24 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 56 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 88 32>;

+};

+&gpio4 {

• gpio-ranges = <&pinctrl 0 120 32>;

+};

+&gpio5 {

• gpio-ranges = <&pinctrl 0 152 32>;

+};

+&gpio6 {

• gpio-ranges = <&pinctrl 0 184 32>;

+};

• &gpio7 { bootph-all;
• gpio-ranges = <&pinctrl 0 216 32>;

+};

+&gpio8 {

• gpio-ranges = <&pinctrl 0 248 16>; };

  &grf {

diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index 684fa7abddb1..7d3cf55c33fa 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -70,6 +70,26 @@ bootph-some-ram; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

+&gpio4 {

• gpio-ranges = <&pinctrl 0 128 32>;

+};

• &grf { bootph-all; };

diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 0135bc08d491..3bc776146a82 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -57,6 +57,19 @@

&gpio0 { bootph-pre-ram;

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>; };

  &grf {

diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi index 811d59ac346e..be2ebda83529 100644 --- a/arch/arm/dts/rk3368-u-boot.dtsi +++ b/arch/arm/dts/rk3368-u-boot.dtsi @@ -26,3 +26,19 @@ reg = <0x0 0xff740000 0x0 0x1000>; }; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index b6b43271172e..b85aac0ad0d1 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -80,6 +80,26 @@ bootph-some-ram; };

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

+&gpio4 {

• gpio-ranges = <&pinctrl 0 128 32>;

+};

• &grf { bootph-all; };

diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index ccf2d8bd83ec..f772d618bd1d 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -5,6 +5,22 @@

#include "rockchip-u-boot.dtsi"

+&gpio0 {

• gpio-ranges = <&pinctrl 0 0 32>;

+};

+&gpio1 {

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

• &grf { bootph-all; };

diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 448598013578..3e6df1e433db 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -31,10 +31,24 @@

&gpio0 { bootph-pre-ram;

• gpio-ranges = <&pinctrl 0 0 32>; };

  &gpio1 { bootph-pre-ram;

• gpio-ranges = <&pinctrl 0 32 32>;

+};

+&gpio2 {

• gpio-ranges = <&pinctrl 0 64 32>;

+};

+&gpio3 {

• gpio-ranges = <&pinctrl 0 96 32>;

+};

+&gpio4 {

• gpio-ranges = <&pinctrl 0 128 2>; };

  &grf {