On 08/22/2016 05:02 PM, Chin Liang See wrote:

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

Acked-by: Marek Vasut marex@denx.de

---

arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100755 index 0000000..cd29a59 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,48 @@ +/*

• • Copyright (C) 2016, Intel Corporation
• • SPDX-License-Identifier: GPL-2.0
• */

+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_

+#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff800000 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_NANDDATA_ADDRESS 0xffb90000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_I2C0_ADDRESS 0xffc02800 +#define SOCFPGA_I2C1_ADDRESS 0xffc02900 +#define SOCFPGA_I2C2_ADDRESS 0xffc02a00 +#define SOCFPGA_I2C3_ADDRESS 0xffc02b00 +#define SOCFPGA_I2C4_ADDRESS 0xffc02c00 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_GPIO0_ADDRESS 0xffc03200 +#define SOCFPGA_GPIO1_ADDRESS 0xffc03300 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_SPIS0_ADDRESS 0xffda2000 +#define SOCFPGA_SPIS1_ADDRESS 0xffda3000 +#define SOCFPGA_SPIM0_ADDRESS 0xffda4000 +#define SOCFPGA_SPIM1_ADDRESS 0xffda5000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000

+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

On 08/22/2016 05:02 PM, Chin Liang See wrote:

Add Reset Manager registers structure for Stratix 10 SoC

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

Acked-by: Marek Vasut marex@denx.de

---

arch/arm/mach-socfpga/include/mach/reset_manager.h | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..1f868da 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void);

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -28,11 +29,42 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +struct socfpga_reset_manager {

• u32 status;
• u32 mpu_rst_stat;
• u32 misc_stat;
• u32 padding1;
• u32 hdsk_en;
• u32 hdsk_req;
• u32 hdsk_ack;
• u32 hdsk_stall;
• u32 mpu_mod_reset;
• u32 per_mod_reset; /* stated as per0_mod_reset in S10 datasheet */
• u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
• u32 brg_mod_reset;
• u32 padding2;
• u32 cold_mod_reset;
• u32 padding3;
• u32 dbg_mod_reset;
• u32 tap_mod_reset;
• u32 padding4;
• u32 padding5;
• u32 brg_warm_mask;
• u32 padding6[3];
• u32 tst_stat;
• u32 padding7;
• u32 hdsk_timeout;
• u32 mpul2flushtimeout;
• u32 dbghdsktimeout;

+}; +#endif

#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 #else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#define RSTMGR_MPUMODRST_CORE0 1 #endif

/*

On 08/22/2016 05:02 PM, Chin Liang See wrote:

Segregate the Reset Manager to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

Acked-by: Marek Vasut marex@denx.de

---

arch/arm/mach-socfpga/reset_manager.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..0fa5f1a 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -15,8 +15,10 @@ DECLARE_GLOBAL_DATA_PTR;

static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */

/* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) @@ -31,8 +33,10 @@ void socfpga_per_reset(u32 reset, int set) reg = &reset_manager_base->per2_mod_reset; else if (RSTMGR_BANK(reset) == 3) reg = &reset_manager_base->brg_mod_reset; +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 else if (RSTMGR_BANK(reset) == 4) reg = &reset_manager_base->misc_mod_reset; +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */ else /* Invalid reset register, do nothing */ return;

@@ -60,9 +64,15 @@ void socfpga_per_reset_all(void) */ void reset_cpu(ulong addr) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* request a warm reset */ writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), &reset_manager_base->ctrl); +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• writel((1 << RSTMGR_MPUMODRST_CORE0),

• &reset_manager_base->mpu_mod_reset);
  

+#endif

• /*
  • infinite loop here as watchdog will trigger and reset
  • the processor

@@ -92,6 +102,7 @@ void socfpga_bridges_reset(int enable)

void socfpga_bridges_reset(int enable) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | L3REGS_REMAP_HPS2FPGA_MASK | L3REGS_REMAP_OCRAM_MASK; @@ -116,5 +127,6 @@ void socfpga_bridges_reset(int enable) /* Remap the bridges into memory map */ writel(l3mask, SOCFPGA_L3REGS_ADDRESS); } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */ } #endif

On 08/22/2016 05:02 PM, Chin Liang See wrote:

Segregate the Clock Manager to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..0d67b3c 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -10,6 +10,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)

return clock; } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

unsigned int cm_get_mmc_controller_clk_hz(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) uint32_t reg, clock = 0;

/* identify the source of MMC clock */ @@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void) /* further divide by 4 as we have fixed divider at wrapper */ clock /= 4; return clock; +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• return 25000000;

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ }

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) unsigned int cm_get_qspi_controller_clk_hz(void)

Are you sure this won't cause build breakage ? I believe this is still used by the cadence qspi driver.

{ uint32_t reg, clock = 0; @@ -556,3 +563,4 @@ U_BOOT_CMD( "display clocks", "" ); +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

On 09/06/2016 07:14 AM, Chin Liang See wrote:

On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:

...

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Segregate the Clock Manager to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach -socfpga/clock_manager.c index aa71636..0d67b3c 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -10,6 +10,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)

return clock; } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

unsigned int cm_get_mmc_controller_clk_hz(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) uint32_t reg, clock = 0;

/* identify the source of MMC clock */ @@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void) /* further divide by 4 as we have fixed divider at wrapper */ clock /= 4; return clock; +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• return 25000000;

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ }

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) unsigned int cm_get_qspi_controller_clk_hz(void)

Are you sure this won't cause build breakage ? I believe this is still used by the cadence qspi driver.

That is a good question. As for SOC Virtual Platform, we are not enabling the QSPI controller.

When stratix 10 ships, this will be left broken then ?

On 09/07/2016 03:26 PM, Chin Liang See wrote:

On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:

...

On 09/06/2016 07:14 AM, Chin Liang See wrote:

...

On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:

...

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Segregate the Clock Manager to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach -socfpga/clock_manager.c index aa71636..0d67b3c 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -10,6 +10,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)

return clock; } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

unsigned int cm_get_mmc_controller_clk_hz(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) uint32_t reg, clock = 0;

/* identify the source of MMC clock */ @@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void) /* further divide by 4 as we have fixed divider at wrapper */ clock /= 4; return clock; +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• return 25000000;

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ }

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) unsigned int cm_get_qspi_controller_clk_hz(void)

Are you sure this won't cause build breakage ? I believe this is still used by the cadence qspi driver.

That is a good question. As for SOC Virtual Platform, we are not enabling the QSPI controller.

When stratix 10 ships, this will be left broken then ?

Definitely not as we will enable and validate this against emulation in coming weeks.

Great, thanks. U-Boot 2016.09 is out on sept. 12 , so that should give you some space to clean this up.

On 08/22/2016 05:02 PM, Chin Liang See wrote:

Segregate the FPGA Manager to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/fpga_manager.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 43fd2fe..a01e062 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Timeout count */ #define FPGA_TIMEOUT_CNT 0x1000000

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;

@@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)

return 0; }

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

Did you just disable the whole file ? If so, then just don't compile it at all, just add conditional into the Makefile.

On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/misc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach -socfpga/misc.c index 5cbd8a4..295121f 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -24,6 +24,8 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_TARGET_SOCFPGA_GEN5

static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; +#endif

int dram_init(void) { @@ -41,6 +44,7 @@ int dram_init(void) return 0; }

+#ifdef CONFIG_TARGET_SOCFPGA_GEN5 void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id) socfpga_fpga_model[i].name, version); return i; } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

/*

• Print CPU information

@@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); printf("BOOT: %s\n", bsel_str[bsel].name); +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• puts("CPU: Altera SoCFPGA Platform\n");
• puts("FPGA: Altera Stratix 10\n");

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

Can't you decode the boot mode and FPGA type instead ?

That is a good question. This is now not available in SOC Virtual Platform. But will definitely enhance this in later stage with hardware available.

Thanks Chin Liang

...

return 0; } #endif

+#ifdef CONFIG_TARGET_SOCFPGA_GEN5 #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { @@ -469,3 +480,4 @@ U_BOOT_CMD( "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS -to-FPGA bridges\n" "" ); +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

On Tue, 2016-09-06 at 14:09 +0200, Marek Vasut wrote:

On 09/06/2016 08:19 AM, Chin Liang See wrote:

...

On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:

...

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/misc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach -socfpga/misc.c index 5cbd8a4..295121f 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -24,6 +24,8 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_TARGET_SOCFPGA_GEN5

static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; +#endif

int dram_init(void) { @@ -41,6 +44,7 @@ int dram_init(void) return 0; }

+#ifdef CONFIG_TARGET_SOCFPGA_GEN5 void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id) socfpga_fpga_model[i].name, version); return i; } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

/*

• Print CPU information

@@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool print_id) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; puts("CPU: Altera SoCFPGA Platform\n"); socfpga_fpga_id(1); printf("BOOT: %s\n", bsel_str[bsel].name); +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)

• puts("CPU: Altera SoCFPGA Platform\n");
• puts("FPGA: Altera Stratix 10\n");

+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

Can't you decode the boot mode and FPGA type instead ?

That is a good question. This is now not available in SOC Virtual Platform. But will definitely enhance this in later stage with hardware available.

What do you mean not available ? Does the VT not emulate the SoC precisely ?

The VT doesn't emulate the Secure Device Manager (SDM) part as its focusing on ARM64 for this phase.

Thanks Chin Liang

On Mon, 2016-09-05 at 18:02 +0200, Marek Vasut wrote:

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Fix casting warning to pointer from integer of different size when enabling ARM64 support

What sort of error did you observe ?

The warning is triggered as ARM64 has build flag -Wpointer-to-int-cast and similar. Here is the build error log

arch/arm/mach-socfpga/system_manager.c: In function sysmgr_pinmux_init:

arch/arm/mach-socfpga/system_manager.c:59:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] uint32_t regs = (uint32_t)&sysmgr_regs ->emacio[0]; ^

In file included from arch/arm/mach-socfpga/system_manager.c:8:0:

./arch/arm/include/asm/io.h:78:29: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) ^ Thanks Chin Liang

...

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/mach-socfpga/system_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach -socfpga/system_manager.c index 75a65f3..89161bd 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -56,7 +56,7 @@ static void populate_sysmgr_fpgaintf_module(void) */ void sysmgr_pinmux_init(void) {

• uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];

• uint32_t *regs = (uint32_t *)&sysmgr_regs->emacio[0]; const u8 *sys_mgr_init_table; unsigned int len; int i;

On 08/22/2016 05:02 PM, Chin Liang See wrote:

Add board folder for Stratix 10 SoC development kit

Directory, this is not Windows :-(

Oh, btw also use "separate", not "segregate", in the previous patches.

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

board/altera/stratix10-socdk/MAINTAINERS | 8 ++++++++ board/altera/stratix10-socdk/Makefile | 7 +++++++ board/altera/stratix10-socdk/socfpga.c | 7 +++++++ 3 files changed, 22 insertions(+) create mode 100755 board/altera/stratix10-socdk/MAINTAINERS create mode 100755 board/altera/stratix10-socdk/Makefile create mode 100755 board/altera/stratix10-socdk/socfpga.c

diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS new file mode 100755 index 0000000..06f8989 --- /dev/null +++ b/board/altera/stratix10-socdk/MAINTAINERS @@ -0,0 +1,8 @@ +SOCFPGA BOARD +M: Chin-Liang See clsee@altera.com +M: Dinh Nguyen dinguyen@opensource.altera.com +S: Maintained +F: board/altera/stratix10-socdk/ +F: include/configs/socfpga_stratix10_socdk.h +F: configs/socfpga_stratix10_defconfig

diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile new file mode 100755 index 0000000..a0c8024 --- /dev/null +++ b/board/altera/stratix10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2016, Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 +#

+obj-y := socfpga.o diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c new file mode 100755 index 0000000..6778c04 --- /dev/null +++ b/board/altera/stratix10-socdk/socfpga.c @@ -0,0 +1,7 @@ +/*

• • Copyright (C) 2016, Intel Corporation
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h>

On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Add support for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/Kconfig | 7 +- arch/arm/mach-socfpga/Kconfig | 10 +++ configs/socfpga_stratix10_defconfig | 14 ++++ include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+), 3 deletions(-) create mode 100755 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..c8e8767 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON

config ARCH_SOCFPGA bool "Altera SOCFPGA family"

• select CPU_V7
• select SUPPORT_SPL

• select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
• select ARM64 if TARGET_SOCFPGA_STRATIX10
• select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10 select OF_CONTROL

• select SPL_OF_CONTROL

• select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10

Why is the SPL disabled ?

We will be having SPL for Stratix 10. It will added in later days as SPL main function is for DDR setup. This is not needed for SOC Virtual Platform now.

...

select DM select DM_SPI_FLASH select DM_SPI diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach -socfpga/Kconfig index 1a43c7b..4e3b238 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool

+config TARGET_SOCFPGA_STRATIX10

• bool

choice prompt "Altera SOCFPGA board select" optional @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5

+config TARGET_SOCFPGA_STRATIX10_SOCDK

• bool "Altera SOCFPGA SoCDK (Stratix 10)"
• select TARGET_SOCFPGA_STRATIX10

endchoice

config SYS_BOARD @@ -63,6 +70,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

• default "stratix10-socdk" if

TARGET_SOCFPGA_STRATIX10_SOCDK

Keep all the lists sorted .

Noted, will fix this.

...

config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -72,6 +80,7 @@ config SYS_VENDOR default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT

• default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK

config SYS_SOC default "socfpga" @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

• default "socfpga_stratix10_socdk" if

TARGET_SOCFPGA_STRATIX10_SOCDK

endif

[...]

btw. what about Arria 10 ? Will it ever land ? And will I ever get a kit ? :)

Since S10 is good, I will help out the A10 upstreaming once S10 is intergrated. While for dev kit, let me work that out as we have A10 dev kit with production silicon :)

Thanks Chin Liang

On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:

On 09/06/2016 11:18 AM, Chin Liang See wrote:

...

On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:

...

On 08/22/2016 05:02 PM, Chin Liang See wrote:

...

Add support for Stratix 10 SoC development kit

Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com

---

arch/arm/Kconfig | 7 +- arch/arm/mach-socfpga/Kconfig | 10 +++ configs/socfpga_stratix10_defconfig | 14 ++++ include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+), 3 deletions(-) create mode 100755 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..c8e8767 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON

config ARCH_SOCFPGA bool "Altera SOCFPGA family"

•   select CPU_V7
  

•   select SUPPORT_SPL
  

•   select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
  

•   select ARM64 if TARGET_SOCFPGA_STRATIX10
  

•   select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
    select OF_CONTROL
  

•   select SPL_OF_CONTROL
  

•   select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
  

Why is the SPL disabled ?

We will be having SPL for Stratix 10. It will added in later days as SPL main function is for DDR setup. This is not needed for SOC Virtual Platform now.

Please do things right from the start, add the SPL and skip the DRAM init if it's not needed.

That is my next to do list as I am enabling the Stratix 10 by phases. In this case, I shall repost this series once getting SPL available.

Thanks Chin Liang

...

...

...

    select DM
    select DM_SPI_FLASH
    select DM_SPI

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach -socfpga/Kconfig index 1a43c7b..4e3b238 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool

+config TARGET_SOCFPGA_STRATIX10

•   bool
  

choice prompt "Altera SOCFPGA board select" optional @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5

+config TARGET_SOCFPGA_STRATIX10_SOCDK

•   bool "Altera SOCFPGA SoCDK (Stratix 10)"
  

•   select TARGET_SOCFPGA_STRATIX10
  

endchoice

config SYS_BOARD @@ -63,6 +70,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

•   default "stratix10-socdk" if
  

TARGET_SOCFPGA_STRATIX10_SOCDK

Keep all the lists sorted .

Noted, will fix this.

...

...

config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -72,6 +80,7 @@ config SYS_VENDOR default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT

•   default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  
  

config SYS_SOC default "socfpga" @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

•   default "socfpga_stratix10_socdk" if
  

TARGET_SOCFPGA_STRATIX10_SOCDK

endif

[...]

btw. what about Arria 10 ? Will it ever land ? And will I ever get a kit ? :)

Since S10 is good, I will help out the A10 upstreaming once S10 is intergrated. While for dev kit, let me work that out as we have A10 dev kit with production silicon :)

The production silicon a10 is still not available ?

...

Thanks Chin Liang

...