On Apr 18, 2006, at 9:51 AM, Kumar Gala wrote:

I'm not aware of any. I'm just guessing the boards people have were built this way.

I have a board that doesn't use CS2/CS3. Once I get it running well I'll submit the patches. Basically, I created a #define in the board configuration header file that indicates the base chip select used. I then use this base and base+1 in the code in place of the hard coded assumption of CS2/3 in the spd_sdram.c file.

-- Dan

Jerry,

The 83xx chips have a separate memory bus for DDR, with its own chip selects. For these chips, you do in fact need to use the local bus CS0 for your boot flash/EEPROM.

I can't find anything in the manual that differentiates between the DDR chip selects, so using CS2/3 was probably just a design choice.

regards, Ben

On Tue, 2006-04-18 at 10:02 -0400, Jerry Van Baren wrote:

Aziz Mzili wrote:

...

Hi

I'm wondering why in cpu/83xx/spd_ram.c we expect the DDR ram to be on cs2 and cs3. Is there any issue with it on cs0 and cs1 ?

thank you

Aziz Mzili

I'm not a 834x expert, but all my experience is that CS0 is used to boot the processor. If it is DDR RAM rather than flash, someone other than the 834x must initialize the DDR RAM and load it with the boot program. That is possible, but very uncommon.

gvb

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