[U-Boot] [PATCH 01/10] dm: arm: Remove support for lpc2292
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de --- arch/arm/cpu/arm720t/cpu.c | 2 +- arch/arm/cpu/arm720t/interrupts.c | 28 +-- arch/arm/cpu/arm720t/lpc2292/Makefile | 50 ---- arch/arm/cpu/arm720t/lpc2292/flash.c | 249 -------------------- arch/arm/cpu/arm720t/lpc2292/iap_entry.S | 7 - arch/arm/cpu/arm720t/lpc2292/mmc.c | 131 ---------- arch/arm/cpu/arm720t/lpc2292/mmc_hw.c | 233 ------------------ arch/arm/cpu/arm720t/lpc2292/mmc_hw.h | 29 --- arch/arm/cpu/arm720t/lpc2292/spi.c | 40 ---- arch/arm/cpu/arm720t/start.S | 70 ------ arch/arm/include/asm/arch-lpc2292/hardware.h | 33 --- .../include/asm/arch-lpc2292/lpc2292_registers.h | 225 ------------------ arch/arm/include/asm/arch-lpc2292/spi.h | 82 ------- drivers/i2c/soft_i2c.c | 3 - drivers/serial/Makefile | 1 - drivers/serial/serial_lpc2292.c | 104 -------- include/flash.h | 1 - 17 files changed, 2 insertions(+), 1286 deletions(-) delete mode 100644 arch/arm/cpu/arm720t/lpc2292/Makefile delete mode 100644 arch/arm/cpu/arm720t/lpc2292/flash.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/iap_entry.S delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc_hw.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc_hw.h delete mode 100644 arch/arm/cpu/arm720t/lpc2292/spi.c delete mode 100644 arch/arm/include/asm/arch-lpc2292/hardware.h delete mode 100644 arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h delete mode 100644 arch/arm/include/asm/arch-lpc2292/spi.h delete mode 100644 drivers/serial/serial_lpc2292.c
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 974f288..52685c1 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -46,7 +46,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 464dd30..45e3cde 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -37,11 +37,6 @@ /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff)
-#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) -#endif - #else #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) @@ -73,13 +68,6 @@ void do_irq (struct pt_regs *pt_regs) } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - - void (*pfnct)(void); - - pfnct = (void (*)(void))VICVectAddr; - - (*pfnct)(); #else #error do_irq() not defined for this CPU type #endif @@ -172,14 +160,6 @@ int timer_init (void)
/* Start timer */ SET_REG( REG_TMOD, TM0_RUN); -#elif defined(CONFIG_LPC2292) - PUT32(T0IR, 0); /* disable all timer0 interrupts */ - PUT32(T0TCR, 0); /* disable timer0 */ - PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ); - PUT32(T0MCR, 0); - PUT32(T0TC, 0); - PUT32(T0TCR, 1); /* enable timer0 */ - #else #error No timer_init() defined for this CPU type #endif @@ -195,7 +175,7 @@ int timer_init (void) */
-#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM)
ulong get_timer (ulong base) { @@ -213,12 +193,6 @@ void __udelay (unsigned long usec) tmo += get_timer (0);
while (get_timer_masked () < tmo) -#ifdef CONFIG_LPC2292 - /* GJ - not sure whether this is really needed or a misunderstanding */ - __asm__ __volatile__(" nop"); -#else - /*NOP*/; -#endif }
ulong get_timer_masked (void) diff --git a/arch/arm/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile deleted file mode 100644 index 1b93008..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = flash.o mmc.o mmc_hw.o spi.o -SOBJS = $(obj)iap_entry.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -# this MUST be compiled as thumb code! -$(SOBJS): - $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c deleted file mode 100644 index 3d2dc32..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/flash.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> - * - * Modified to remove all but the IAP-command related code by - * Gary Jennejohn garyj@denx.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/hardware.h> - -/* IAP commands use 32 bytes at the top of CPU internal sram, we - use 512 bytes below that */ -#define COPY_BUFFER_LOCATION 0x40003de0 - -#define IAP_LOCATION 0x7ffffff1 -#define IAP_CMD_PREPARE 50 -#define IAP_CMD_COPY 51 -#define IAP_CMD_ERASE 52 -#define IAP_CMD_CHECK 53 -#define IAP_CMD_ID 54 -#define IAP_CMD_VERSION 55 -#define IAP_CMD_COMPARE 56 - -#define IAP_RET_CMD_SUCCESS 0 - -static unsigned long command[5]; -static unsigned long result[2]; - -extern void iap_entry(unsigned long * command, unsigned long * result); - -/*----------------------------------------------------------------------- - * - */ -static int get_flash_sector(flash_info_t * info, ulong flash_addr) -{ - int i; - - for(i = 1; i < (info->sector_count); i++) { - if (flash_addr < (info->start[i])) - break; - } - - return (i-1); -} - -/*----------------------------------------------------------------------- - * This function assumes that flash_addr is aligned on 512 bytes boundary - * in flash. This function also assumes that prepare have been called - * for the sector in question. - */ -int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) -{ - int first_sector; - int last_sector; - - first_sector = get_flash_sector(info, flash_addr); - last_sector = get_flash_sector(info, flash_addr + 512 - 1); - - /* prepare sectors for write */ - command[0] = IAP_CMD_PREPARE; - command[1] = first_sector; - command[2] = last_sector; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROG_ERROR; - } - - command[0] = IAP_CMD_COPY; - command[1] = flash_addr; - command[2] = COPY_BUFFER_LOCATION; - command[3] = 512; - command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP copy failed\n"); - return 1; - } - - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag; - int prot; - int sect; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - - flag = disable_interrupts(); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first + 1, s_first); - - command[0] = IAP_CMD_PREPARE; - command[1] = s_first; - command[2] = s_last; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROTECTED; - } - - command[0] = IAP_CMD_ERASE; - command[1] = s_first; - command[2] = s_last; - command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP erase failed\n"); - return ERR_PROTECTED; - } - - if (flag) - enable_interrupts(); - - return ERR_OK; -} - -int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr, - ulong cnt) -{ - int first_copy_size; - int last_copy_size; - int first_block; - int last_block; - int nbr_mid_blocks; - uchar memmap_value; - ulong i; - uchar* src_org; - uchar* dst_org; - int ret = ERR_OK; - - src_org = src; - dst_org = (uchar*)addr; - - first_block = addr / 512; - last_block = (addr + cnt) / 512; - nbr_mid_blocks = last_block - first_block - 1; - - first_copy_size = 512 - (addr % 512); - last_copy_size = (addr + cnt) % 512; - - debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", - (ulong)(first_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - first_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)(first_block * 512)); - - /* copy first block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(first_block * 512), 512); - memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - src, first_copy_size); - lpc2292_copy_buffer_to_flash(info, first_block * 512); - src += first_copy_size; - addr += first_copy_size; - - /* copy middle blocks */ - for (i = 0; i < nbr_mid_blocks; i++) { - debug("copy middle block: %lX -> %lX 512 bytes, " - "%lX -> %lX 512 bytes\n", - (ulong)src, - (ulong)COPY_BUFFER_LOCATION, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); - - memcpy((void*)COPY_BUFFER_LOCATION, src, 512); - lpc2292_copy_buffer_to_flash(info, addr); - src += 512; - addr += 512; - } - - - if (last_copy_size > 0) { - debug("copy last block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", - (ulong)(last_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION), - last_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); - - /* copy last block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(last_block * 512), 512); - memcpy((void*)COPY_BUFFER_LOCATION, - src, last_copy_size); - lpc2292_copy_buffer_to_flash(info, addr); - } - - /* verify write */ - memmap_value = GET8(MEMMAP); - - disable_interrupts(); - - PUT8(MEMMAP, 01); /* we must make sure that initial 64 - bytes are taken from flash when we - do the compare */ - - for (i = 0; i < cnt; i++) { - if (*dst_org != *src_org){ - printf("Write failed. Byte %lX differs\n", i); - ret = ERR_PROG_ERROR; - break; - } - dst_org++; - src_org++; - } - - PUT8(MEMMAP, memmap_value); - enable_interrupts(); - - return ret; -} diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S deleted file mode 100644 index c31d519..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S +++ /dev/null @@ -1,7 +0,0 @@ -IAP_ADDRESS: .word 0x7FFFFFF1 - -.globl iap_entry -iap_entry: - ldr r2, IAP_ADDRESS - bx r2 - mov pc, lr diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c deleted file mode 100644 index beaffe9..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <mmc.h> -#include <asm/errno.h> -#include <asm/arch/hardware.h> -#include <part.h> -#include <fat.h> -#include "mmc_hw.h" -#include <asm/arch/spi.h> - -#ifdef CONFIG_MMC - -#undef MMC_DEBUG - -static block_dev_desc_t mmc_dev; - -/* these are filled out by a call to mmc_hw_get_parameters */ -static int hw_size; /* in kbytes */ -static int hw_nr_sects; -static int hw_sect_size; /* in bytes */ - -block_dev_desc_t * mmc_get_dev(int dev) -{ - return (block_dev_desc_t *)(&mmc_dev); -} - -unsigned long mmc_block_read(int dev, - unsigned long start, - lbaint_t blkcnt, - void *buffer) -{ - unsigned long rc = 0; - unsigned char *p = (unsigned char *)buffer; - unsigned long i; - unsigned long addr = start; - -#ifdef MMC_DEBUG - printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, - (unsigned long)blkcnt); -#endif - - for(i = 0; i < (unsigned long)blkcnt; i++) { -#ifdef MMC_DEBUG - printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); -#endif - (void)mmc_read_sector(addr, p); - rc++; - addr++; - p += hw_sect_size; - } - - return rc; -} - -/*----------------------------------------------------------------------------- - * Read hardware paramterers (sector size, size, number of sectors) - */ -static int mmc_hw_get_parameters(void) -{ - unsigned char csddata[16]; - unsigned int sizemult; - unsigned int size; - - mmc_read_csd(csddata); - hw_sect_size = 1<<(csddata[5] & 0x0f); - size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); - sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); - hw_nr_sects = (size+1)*(1<<(sizemult+2)); - hw_size = hw_nr_sects*hw_sect_size/1024; - -#ifdef MMC_DEBUG - printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " - "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); -#endif - - return 0; -} - -int mmc_legacy_init(int verbose) -{ - int ret = -ENODEV; - - if (verbose) - printf("mmc_legacy_init\n"); - - spi_init(); - /* this meeds to be done twice */ - mmc_hw_init(); - udelay(1000); - mmc_hw_init(); - - mmc_hw_get_parameters(); - - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - mmc_dev.blksz = hw_sect_size; - mmc_dev.lba = hw_nr_sects; - sprintf((char*)mmc_dev.vendor, "Unknown vendor"); - sprintf((char*)mmc_dev.product, "Unknown product"); - sprintf((char*)mmc_dev.revision, "N/A"); - mmc_dev.removable = 0; /* should be true??? */ - mmc_dev.block_read = mmc_block_read; - - fat_register_device(&mmc_dev, 1); - - ret = 0; - - return ret; -} - -#endif /* CONFIG_MMC */ diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c deleted file mode 100644 index bd6a5b1..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - This code was original written by Ulrich Radig and modified by - Embedded Artists AB (www.embeddedartists.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <config.h> -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spi.h> - -#define MMC_Enable() PUT32(IO1CLR, 1l << 22) -#define MMC_Disable() PUT32(IO1SET, 1l << 22) -#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); - -static unsigned char Write_Command_MMC (unsigned char *CMD); -static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, - unsigned short int Bytes); - -/* initialize the hardware */ -int mmc_hw_init(void) -{ - unsigned long a; - unsigned short int Timeout = 0; - unsigned char b; - unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; - - /* set-up GPIO and SPI */ - (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ - (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ - - MMC_Disable(); - - spi_lock(); - spi_set_clock(248); - spi_set_cfg(0, 1, 0); - MMC_Enable(); - - /* waste some time */ - for(a=0; a < 20000; a++) - asm("nop"); - - /* Put the MMC/SD-card into SPI-mode */ - for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ - spi_write(0xff); - - /* Sends command CMD0 to MMC/SD-card */ - while (Write_Command_MMC(CMD) != 1) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return(1); /* Abort with command 1 (return 1) */ - } - } - /* Sends Command CMD1 an MMC/SD-card */ - Timeout = 0; - CMD[0] = 0x41;/* Command 1 */ - CMD[5] = 0xFF; - - while (Write_Command_MMC(CMD) != 0) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return (2); /* Abort with command 2 (return 2) */ - } - } - - MMC_Disable(); - spi_unlock(); - - return 0; -} - -/* ############################################################################ - Sends a command to the MMC/SD-card - ######################################################################### */ -static unsigned char Write_Command_MMC (unsigned char *CMD) -{ - unsigned char a, tmp = 0xff; - unsigned short int Timeout = 0; - - MMC_Disable(); - spi_write(0xFF); - MMC_Enable(); - - for (a = 0; a < 0x06; a++) - spi_write(*CMD++); - - while (tmp == 0xff) { - tmp = spi_read(); - if (Timeout++ > 5000) - break; - } - - return (tmp); -} - -/* ############################################################################ - Routine to read the CID register from the MMC/SD-card (16 bytes) - ######################################################################### */ -void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short - int Bytes) -{ - unsigned short int a; - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - if (Write_Command_MMC(CMD) != 0) { - MMC_Disable(); - spi_unlock(); - return; - } - - while (spi_read() != 0xfe) {}; - for (a = 0; a < Bytes; a++) - *Buffer++ = spi_read(); - - /* Read the CRC-byte */ - spi_read(); /* CRC - byte is discarded */ - spi_read(); /* CRC - byte is discarded */ - /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ - MMC_Disable(); - spi_unlock(); - - return; -} - -/* ############################################################################ - Routine to read a block (512 bytes) from the MMC/SD-card - ######################################################################### */ -unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) -{ - /* Command 16 to read aBlocks from the MMC/SD - caed */ - unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; - - /* The address on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - MMC_Read_Block(CMD, Buffer, 512); - - return (0); -} - -/* ############################################################################ - Routine to write a block (512 byte) to the MMC/SD-card - ######################################################################### */ -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) -{ - unsigned char tmp, a; - unsigned short int b; - /* Command 24 to write a block to the MMC/SD - card */ - unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - /* The address on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ - tmp = Write_Command_MMC(CMD); - if (tmp != 0) { - MMC_Disable(); - spi_unlock(); - return(tmp); - } - - /* Do a short delay and send a clock-pulse to the MMC/SD-card */ - for (a = 0; a < 100; a++) - spi_read(); - - /* Send a start byte to the MMC/SD-card */ - spi_write(0xFE); - - /* Write the block (512 bytes) to the MMC/SD-card */ - for (b = 0; b < 512; b++) - spi_write(*Buffer++); - - /* write the CRC-Byte */ - spi_write(0xFF); /* write a dummy CRC */ - spi_write(0xFF); /* CRC code is not used */ - - /* Wait for MMC/SD-card busy */ - while (spi_read() != 0xff) {}; - - /* set MMC_Chip_Select to high (MMC/SD-card inactive) */ - MMC_Disable(); - spi_unlock(); - return (0); -} - -/* ######################################################################### - Routine to read the CSD register from the MMC/SD-card (16 bytes) - ######################################################################### */ -unsigned char mmc_read_csd (unsigned char *Buffer) -{ - /* Command to read the CSD register */ - unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - MMC_Read_Block(CMD, Buffer, 16); - - return (0); -} diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h deleted file mode 100644 index 3687dbf..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - This module implements a linux character device driver for the 24c256 chip. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef _MMC_HW_ -#define _MMC_HW_ - -unsigned char mmc_read_csd(unsigned char *Buffer); -unsigned char mmc_read_sector (unsigned long addr, - unsigned char *Buffer); -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); -int mmc_hw_init(void); - -#endif /* _MMC_HW_ */ diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c deleted file mode 100644 index d296bda..0000000 --- a/arch/arm/cpu/arm720t/lpc2292/spi.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - This module implements an interface to the SPI on the lpc22xx. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <config.h> -#include <common.h> -#include <asm/errno.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spi.h> - -unsigned long spi_flags; -unsigned char spi_idle = 0x00; - -int spi_init(void) -{ - unsigned long pinsel0_value; - - /* activate spi pins */ - pinsel0_value = GET32(PINSEL0); - pinsel0_value &= ~(0xFFl << 8); - pinsel0_value |= (0x55l << 8); - PUT32(PINSEL0, pinsel0_value); - - return 0; -} diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 540e3c2..8ecd351 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -43,11 +43,7 @@ _start: b reset ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort -#ifdef CONFIG_LPC2292 - .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ -#else ldr pc, _not_used -#endif ldr pc, _irq ldr pc, _fiq
@@ -135,10 +131,6 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 - bl lowlevel_init -#endif - /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -272,16 +264,6 @@ _dynsym_start_ofs: ************************************************************************* */
-#if defined(CONFIG_LPC2292) -PLLCFG_ADR: .word PLLCFG -PLLFEED_ADR: .word PLLFEED -PLLCON_ADR: .word PLLCON -PLLSTAT_ADR: .word PLLSTAT -VPBDIV_ADR: .word VPBDIV -MEMMAP_ADR: .word MEMMAP - -#endif - cpu_init_crit: #if defined(CONFIG_NETARM) /* @@ -352,50 +334,6 @@ cpu_init_crit:
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - /* Set-up PLL */ - mov r3, #0xAA - mov r4, #0x55 - /* First disconnect and disable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x00 - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set new M and P values */ - ldr r0, PLLCFG_ADR - mov r1, #0x23 /* M=4 and P=2 */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Then enable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x01 /* PLL enable bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Wait for the lock */ - ldr r0, PLLSTAT_ADR - mov r1, #0x400 /* lock bit */ -lock_loop: - ldr r2, [r0] - and r2, r1, r2 - cmp r2, #0 - beq lock_loop - /* And finally connect the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x03 /* PLL enable bit and connect bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set-up VPBDIV register */ - ldr r0, VPBDIV_ADR - mov r1, #0x01 /* VPB clock is same as process clock */ - str r1, [r0] #else #error No cpu_init_crit() defined for current CPU type #endif @@ -411,7 +349,6 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 mov ip, lr /* * before relocating, we have to setup RAM timing @@ -420,8 +357,6 @@ lock_loop: */ bl lowlevel_init mov lr, ip -#endif - mov pc, lr
@@ -613,11 +548,6 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - .align 5 -.globl reset_cpu -reset_cpu: - mov pc, r0 #else #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/arm/include/asm/arch-lpc2292/hardware.h deleted file mode 100644 index 5e227e3..0000000 --- a/arch/arm/include/asm/arch-lpc2292/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune curt@cucy.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_LPC2292) -#include <asm/arch-lpc2292/lpc2292_registers.h> -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h deleted file mode 100644 index 5715f3e..0000000 --- a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __LPC2292_REGISTERS_H -#define __LPC2292_REGISTERS_H - -#include <config.h> - -/* Macros for reading/writing registers */ -#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) -#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) -#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) -#define GET8(reg) (*(volatile unsigned char*)(reg)) -#define GET16(reg) (*(volatile unsigned short*)(reg)) -#define GET32(reg) (*(volatile unsigned int*)(reg)) - -/* External Memory Controller */ - -#define BCFG0 0xFFE00000 /* 32-bits */ -#define BCFG1 0xFFE00004 /* 32-bits */ -#define BCFG2 0xFFE00008 /* 32-bits */ -#define BCFG3 0xFFE0000c /* 32-bits */ - -/* System Control Block */ - -#define EXTINT 0xE01FC140 -#define EXTWAKE 0xE01FC144 -#define EXTMODE 0xE01FC148 -#define EXTPOLAR 0xE01FC14C -#define MEMMAP 0xE01FC040 -#define PLLCON 0xE01FC080 -#define PLLCFG 0xE01FC084 -#define PLLSTAT 0xE01FC088 -#define PLLFEED 0xE01FC08C -#define PCON 0xE01FC0C0 -#define PCONP 0xE01FC0C4 -#define VPBDIV 0xE01FC100 - -/* Memory Acceleration Module */ - -#define MAMCR 0xE01FC000 -#define MAMTIM 0xE01FC004 - -/* Vectored Interrupt Controller */ - -#define VICIRQStatus 0xFFFFF000 -#define VICFIQStatus 0xFFFFF004 -#define VICRawIntr 0xFFFFF008 -#define VICIntSelect 0xFFFFF00C -#define VICIntEnable 0xFFFFF010 -#define VICIntEnClr 0xFFFFF014 -#define VICSoftInt 0xFFFFF018 -#define VICSoftIntClear 0xFFFFF01C -#define VICProtection 0xFFFFF020 -#define VICVectAddr 0xFFFFF030 -#define VICDefVectAddr 0xFFFFF034 -#define VICVectAddr0 0xFFFFF100 -#define VICVectAddr1 0xFFFFF104 -#define VICVectAddr2 0xFFFFF108 -#define VICVectAddr3 0xFFFFF10C -#define VICVectAddr4 0xFFFFF110 -#define VICVectAddr5 0xFFFFF114 -#define VICVectAddr6 0xFFFFF118 -#define VICVectAddr7 0xFFFFF11C -#define VICVectAddr8 0xFFFFF120 -#define VICVectAddr9 0xFFFFF124 -#define VICVectAddr10 0xFFFFF128 -#define VICVectAddr11 0xFFFFF12C -#define VICVectAddr12 0xFFFFF130 -#define VICVectAddr13 0xFFFFF134 -#define VICVectAddr14 0xFFFFF138 -#define VICVectAddr15 0xFFFFF13C -#define VICVectCntl0 0xFFFFF200 -#define VICVectCntl1 0xFFFFF204 -#define VICVectCntl2 0xFFFFF208 -#define VICVectCntl3 0xFFFFF20C -#define VICVectCntl4 0xFFFFF210 -#define VICVectCntl5 0xFFFFF214 -#define VICVectCntl6 0xFFFFF218 -#define VICVectCntl7 0xFFFFF21C -#define VICVectCntl8 0xFFFFF220 -#define VICVectCntl9 0xFFFFF224 -#define VICVectCntl10 0xFFFFF228 -#define VICVectCntl11 0xFFFFF22C -#define VICVectCntl12 0xFFFFF230 -#define VICVectCntl13 0xFFFFF234 -#define VICVectCntl14 0xFFFFF238 -#define VICVectCntl15 0xFFFFF23C - -/* Pin connect block */ - -#define PINSEL0 0xE002C000 /* 32 bits */ -#define PINSEL1 0xE002C004 /* 32 bits */ -#define PINSEL2 0xE002C014 /* 32 bits */ - -/* GPIO */ - -#define IO0PIN 0xE0028000 -#define IO0SET 0xE0028004 -#define IO0DIR 0xE0028008 -#define IO0CLR 0xE002800C -#define IO1PIN 0xE0028010 -#define IO1SET 0xE0028014 -#define IO1DIR 0xE0028018 -#define IO1CLR 0xE002801C -#define IO2PIN 0xE0028020 -#define IO2SET 0xE0028024 -#define IO2DIR 0xE0028028 -#define IO2CLR 0xE002802C -#define IO3PIN 0xE0028030 -#define IO3SET 0xE0028034 -#define IO3DIR 0xE0028038 -#define IO3CLR 0xE002803C - -/* Uarts */ - -#define U0RBR 0xE000C000 -#define U0THR 0xE000C000 -#define U0IER 0xE000C004 -#define U0IIR 0xE000C008 -#define U0FCR 0xE000C008 -#define U0LCR 0xE000C00C -#define U0LSR 0xE000C014 -#define U0SCR 0xE000C01C -#define U0DLL 0xE000C000 -#define U0DLM 0xE000C004 - -#define U1RBR 0xE0010000 -#define U1THR 0xE0010000 -#define U1IER 0xE0010004 -#define U1IIR 0xE0010008 -#define U1FCR 0xE0010008 -#define U1LCR 0xE001000C -#define U1MCR 0xE0010010 -#define U1LSR 0xE0010014 -#define U1MSR 0xE0010018 -#define U1SCR 0xE001001C -#define U1DLL 0xE0010000 -#define U1DLM 0xE0010004 - -/* I2C */ - -#define I2CONSET 0xE001C000 -#define I2STAT 0xE001C004 -#define I2DAT 0xE001C008 -#define I2ADR 0xE001C00C -#define I2SCLH 0xE001C010 -#define I2SCLL 0xE001C014 -#define I2CONCLR 0xE001C018 - -/* SPI */ - -#define S0SPCR 0xE0020000 -#define S0SPSR 0xE0020004 -#define S0SPDR 0xE0020008 -#define S0SPCCR 0xE002000C -#define S0SPINT 0xE002001C - -#define S1SPCR 0xE0030000 -#define S1SPSR 0xE0030004 -#define S1SPDR 0xE0030008 -#define S1SPCCR 0xE003000C -#define S1SPINT 0xE003001C - -/* CAN controller */ - -/* skip for now */ - -/* Timers */ - -#define T0IR 0xE0004000 -#define T0TCR 0xE0004004 -#define T0TC 0xE0004008 -#define T0PR 0xE000400C -#define T0PC 0xE0004010 -#define T0MCR 0xE0004014 -#define T0MR0 0xE0004018 -#define T0MR1 0xE000401C -#define T0MR2 0xE0004020 -#define T0MR3 0xE0004024 -#define T0CCR 0xE0004028 -#define T0CR0 0xE000402C -#define T0CR1 0xE0004030 -#define T0CR2 0xE0004034 -#define T0CR3 0xE0004038 -#define T0EMR 0xE000403C - -#define T1IR 0xE0008000 -#define T1TCR 0xE0008004 -#define T1TC 0xE0008008 -#define T1PR 0xE000800C -#define T1PC 0xE0008010 -#define T1MCR 0xE0008014 -#define T1MR0 0xE0008018 -#define T1MR1 0xE000801C -#define T1MR2 0xE0008020 -#define T1MR3 0xE0008024 -#define T1CCR 0xE0008028 -#define T1CR0 0xE000802C -#define T1CR1 0xE0008030 -#define T1CR2 0xE0008034 -#define T1CR3 0xE0008038 -#define T1EMR 0xE000803C - -/* PWM */ - -/* skip for now */ - -/* A/D converter */ - -/* skip for now */ - -/* Real Time Clock */ - -/* skip for now */ - -/* Watchdog */ - -#define WDMOD 0xE0000000 -#define WDTC 0xE0000004 -#define WDFEED 0xE0000008 -#define WDTV 0xE000000C - -/* EmbeddedICE LOGIC */ - -/* skip for now */ - -#endif diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h deleted file mode 100644 index 6ae66e8..0000000 --- a/arch/arm/include/asm/arch-lpc2292/spi.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - This file defines the interface to the lpc22xx SPI module. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This file may be included in software not adhering to the GPL. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef SPI_H -#define SPI_H - -#include <config.h> -#include <common.h> -#include <asm/errno.h> -#include <asm/arch/hardware.h> - -#define SPIF 0x80 - -#define spi_lock() disable_interrupts(); -#define spi_unlock() enable_interrupts(); - -extern unsigned long spi_flags; -extern unsigned char spi_idle; - -int spi_init(void); - -static inline unsigned char spi_read(void) -{ - unsigned char b; - - PUT8(S0SPDR, spi_idle); - while (!(GET8(S0SPSR) & SPIF)); - b = GET8(S0SPDR); - - return b; -} - -static inline void spi_write(unsigned char b) -{ - PUT8(S0SPDR, b); - while (!(GET8(S0SPSR) & SPIF)); - GET8(S0SPDR); /* this will clear the SPIF bit */ -} - -static inline void spi_set_clock(unsigned char clk_value) -{ - PUT8(S0SPCCR, clk_value); -} - -static inline void spi_set_cfg(unsigned char phase, - unsigned char polarity, - unsigned char lsbf) -{ - unsigned char v = 0x20; /* master bit set */ - - if (phase) - v |= 0x08; /* set phase bit */ - if (polarity) { - v |= 0x10; /* set polarity bit */ - spi_idle = 0xFF; - } else { - spi_idle = 0x00; - } - if (lsbf) - v |= 0x40; /* set lsbf bit */ - - PUT8(S0SPCR, v); -} -#endif /* SPI_H */ diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 36c6114..1595c07 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -41,9 +41,6 @@ #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> #endif -#ifdef CONFIG_LPC2292 -#include <asm/arch/hardware.h> -#endif #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) #include <asm/io.h> #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 65d0f23..cae15f9 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -42,7 +42,6 @@ COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o -COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o diff --git a/drivers/serial/serial_lpc2292.c b/drivers/serial/serial_lpc2292.c deleted file mode 100644 index e3a60b6..0000000 --- a/drivers/serial/serial_lpc2292.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - unsigned short divisor = 0; - - switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; - } - - /* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ -} - -int serial_init (void) -{ - unsigned long pinsel0; - - serial_setbrg (); - - pinsel0 = GET32(PINSEL0); - pinsel0 &= ~(0x00000003); - pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} - -int serial_getc (void) -{ - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* Test if there is a byte to read */ -int serial_tstc (void) -{ - return (GET8(U0LSR) & 1); -} diff --git a/include/flash.h b/include/flash.h index 0ca70d9..e91a5bf 100644 --- a/include/flash.h +++ b/include/flash.h @@ -347,7 +347,6 @@ extern flash_info_t *flash_get_info(ulong base);
#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ -#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
/*----------------------------------------------------------------------- * Internal FLASH identification codes
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Curt Brune curt@cucy.com --- CREDITS | 5 - arch/arm/cpu/arm720t/cpu.c | 2 +- arch/arm/cpu/arm720t/interrupts.c | 106 +--------- arch/arm/cpu/arm720t/s3c4510b/Makefile | 45 ---- arch/arm/cpu/arm720t/s3c4510b/cache.c | 86 -------- arch/arm/cpu/arm720t/start.S | 19 -- arch/arm/include/asm/arch-s3c4510b/hardware.h | 272 ------------------------- drivers/serial/Makefile | 1 - drivers/serial/s3c4510b_uart.c | 212 ------------------- drivers/serial/s3c4510b_uart.h | 109 ---------- 10 files changed, 2 insertions(+), 855 deletions(-) delete mode 100644 arch/arm/cpu/arm720t/s3c4510b/Makefile delete mode 100644 arch/arm/cpu/arm720t/s3c4510b/cache.c delete mode 100644 arch/arm/include/asm/arch-s3c4510b/hardware.h delete mode 100644 drivers/serial/s3c4510b_uart.c delete mode 100644 drivers/serial/s3c4510b_uart.h
diff --git a/CREDITS b/CREDITS index 933104c..c039553 100644 --- a/CREDITS +++ b/CREDITS @@ -79,11 +79,6 @@ N: Oliver Brown E: obrown@adventnetworks.com D: Port to the gw8260 board
-N: Curt Brune -E: curt@cucy.com -D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC) -W: http://www.cucy.com - N: Jonathan De Bruyne E: jonathan.debruyne@siemens.atea.be D: Port to Siemens IAD210 board diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 52685c1..5db4146 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -46,7 +46,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) +#if defined(CONFIG_NETARM) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 45e3cde..68592b3 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -45,28 +45,10 @@ #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) #endif
-#ifdef CONFIG_S3C4510B -/* require interrupts for the S3C4510B */ -# ifndef CONFIG_USE_IRQ -# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B -# else -static struct _irq_handler IRQ_HANDLER[N_IRQS]; -# endif -#endif /* CONFIG_S3C4510B */ - #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { -#if defined(CONFIG_S3C4510B) - unsigned int pending; - - while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ - IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data); - - /* clear pending interrupt */ - PUT_REG( REG_INTPEND, (1<<(pending>>2))); - } -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ #else #error do_irq() not defined for this CPU type @@ -74,23 +56,6 @@ void do_irq (struct pt_regs *pt_regs) } #endif
-#ifdef CONFIG_S3C4510B -static void default_isr( void *data) { - printf ("default_isr(): called for IRQ %d\n", (int)data); -} - -static void timer_isr( void *data) { - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - if ( !(*pTime % (CONFIG_SYS_HZ/4))) { - /* toggle LED 0 */ - PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); - } - -} -#endif - #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* Use IntegratorAP routines in board/integratorap.c */ #else @@ -98,32 +63,6 @@ static void timer_isr( void *data) { static ulong timestamp; static ulong lastdec;
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B) -int arch_interrupt_init (void) -{ - int i; - - /* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); - /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); - - lastdec = 0; - - /* install interrupt handler for timer */ - IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; - IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; - - return 0; -} -#endif - int timer_init (void) { #if defined(CONFIG_NETARM) @@ -137,29 +76,6 @@ int timer_init (void)
/* set timer 2 counter */ lastdec = TIMER_LOAD_VAL; -#elif defined(CONFIG_S3C4510B) - /* configure free running timer 0 */ - PUT_REG( REG_TMOD, 0x0); - /* Stop timer 0 */ - CLR_REG( REG_TMOD, TM0_RUN); - - /* Configure for interval mode */ - CLR_REG( REG_TMOD, TM1_TOGGLE); - - /* - * Load Timer data register with count down value. - * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ - */ - PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ)); - - /* - * Enable global interrupt - * Enable timer0 interrupt - */ - CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0))); - - /* Start timer */ - SET_REG( REG_TMOD, TM0_RUN); #else #error No timer_init() defined for this CPU type #endif @@ -234,26 +150,6 @@ void udelay_masked (unsigned long usec) } while (diff >= 0); }
-#elif defined(CONFIG_S3C4510B) - -ulong get_timer (ulong base) -{ - return timestamp - base; -} - -void __udelay (unsigned long usec) -{ - u32 ticks; - - ticks = (usec * CONFIG_SYS_HZ) / 1000000; - - ticks += get_timer (0); - - while (get_timer (0) < ticks) - /*NOP*/; - -} - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ #else diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile deleted file mode 100644 index 5c6df08..0000000 --- a/arch/arm/cpu/arm720t/s3c4510b/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c deleted file mode 100644 index 104d287..0000000 --- a/arch/arm/cpu/arm720t/s3c4510b/cache.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/hardware.h> - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 8ecd351..2af4d33 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -316,22 +316,6 @@ cpu_init_crit: ldr r0, =NETARM_GEN_MODULE_BASE str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-#elif defined(CONFIG_S3C4510B) - - /* - * Mask off all IRQ sources - */ - ldr r1, =REG_INTMASK - ldr r0, =0x3FFFFF - str r0, [r1] - - /* - * Disable Cache - */ - ldr r0, =REG_SYSCFG - ldr r1, =0x83ffffa0 /* cache-disabled */ - str r1, [r0] - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ #else @@ -543,9 +527,6 @@ reset_cpu: ldr r1, =NETARM_GEN_SW_SVC_RESETB str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] mov pc, r0 -#elif defined(CONFIG_S3C4510B) -/* Nothing done here as reseting the CPU is board specific, depending - * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ #else diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h deleted file mode 100644 index 6b8c8ed..0000000 --- a/arch/arm/include/asm/arch-s3c4510b/hardware.h +++ /dev/null @@ -1,272 +0,0 @@ -#ifndef __HW_S3C4510_H -#define __HW_S3C4510_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune curt@cucy.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Description: Samsung S3C4510B register layout - */ - -/*------------------------------------------------------------------------ - * ASIC Address Definition - *----------------------------------------------------------------------*/ - -/* L1 8KB on chip SRAM base address */ -#define SRAM_BASE (0x03fe0000) - -/* Special Register Start Address After System Reset */ -#define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) - -/* *********************** */ -/* System Manager Register */ -/* *********************** */ -#define REG_SYSCFG (REG_BASE+0x0000) - -#define REG_CLKCON (REG_BASE+0x3000) -#define REG_EXTACON0 (REG_BASE+0x3008) -#define REG_EXTACON1 (REG_BASE+0x300c) -#define REG_EXTDBWTH (REG_BASE+0x3010) -#define REG_ROMCON0 (REG_BASE+0x3014) -#define REG_ROMCON1 (REG_BASE+0x3018) -#define REG_ROMCON2 (REG_BASE+0x301c) -#define REG_ROMCON3 (REG_BASE+0x3020) -#define REG_ROMCON4 (REG_BASE+0x3024) -#define REG_ROMCON5 (REG_BASE+0x3028) -#define REG_DRAMCON0 (REG_BASE+0x302c) -#define REG_DRAMCON1 (REG_BASE+0x3030) -#define REG_DRAMCON2 (REG_BASE+0x3034) -#define REG_DRAMCON3 (REG_BASE+0x3038) -#define REG_REFEXTCON (REG_BASE+0x303c) - -/* *********************** */ -/* Ethernet BDMA Register */ -/* *********************** */ -#define REG_BDMATXCON (REG_BASE+0x9000) -#define REG_BDMARXCON (REG_BASE+0x9004) -#define REG_BDMATXPTR (REG_BASE+0x9008) -#define REG_BDMARXPTR (REG_BASE+0x900c) -#define REG_BDMARXLSZ (REG_BASE+0x9010) -#define REG_BDMASTAT (REG_BASE+0x9014) - -/* Content Address Memory */ -#define REG_CAM_BASE (REG_BASE+0x9100) - -#define REG_BDMATXBUF (REG_BASE+0x9200) -#define REG_BDMARXBUF (REG_BASE+0x9800) - -/* *********************** */ -/* Ethernet MAC Register */ -/* *********************** */ -#define REG_MACCON (REG_BASE+0xa000) -#define REG_CAMCON (REG_BASE+0xa004) -#define REG_MACTXCON (REG_BASE+0xa008) -#define REG_MACTXSTAT (REG_BASE+0xa00c) -#define REG_MACRXCON (REG_BASE+0xa010) -#define REG_MACRXSTAT (REG_BASE+0xa014) -#define REG_STADATA (REG_BASE+0xa018) -#define REG_STACON (REG_BASE+0xa01c) -#define REG_CAMEN (REG_BASE+0xa028) -#define REG_EMISSCNT (REG_BASE+0xa03c) -#define REG_EPZCNT (REG_BASE+0xa040) -#define REG_ERMPZCNT (REG_BASE+0xa044) -#define REG_ETXSTAT (REG_BASE+0x9040) -#define REG_MACRXDESTR (REG_BASE+0xa064) -#define REG_MACRXSTATEM (REG_BASE+0xa090) -#define REG_MACRXFIFO (REG_BASE+0xa200) - -/********************/ -/* I2C Bus Register */ -/********************/ -#define REG_I2C_CON (REG_BASE+0xf000) -#define REG_I2C_BUF (REG_BASE+0xf004) -#define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) - -/********************/ -/* GDMA 0 */ -/********************/ -#define REG_GDMACON0 (REG_BASE+0xb000) -#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) -#define REG_GDMASRC0 (REG_BASE+0xb004) -#define REG_GDMADST0 (REG_BASE+0xb008) -#define REG_GDMACNT0 (REG_BASE+0xb00c) - -/********************/ -/* GDMA 1 */ -/********************/ -#define REG_GDMACON1 (REG_BASE+0xc000) -#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) -#define REG_GDMASRC1 (REG_BASE+0xc004) -#define REG_GDMADST1 (REG_BASE+0xc008) -#define REG_GDMACNT1 (REG_BASE+0xc00c) - -/********************/ -/* UART 0 */ -/********************/ -#define UART0_BASE (REG_BASE+0xd000) -#define REG_UART0_LCON (REG_BASE+0xd000) -#define REG_UART0_CTRL (REG_BASE+0xd004) -#define REG_UART0_STAT (REG_BASE+0xd008) -#define REG_UART0_TXB (REG_BASE+0xd00c) -#define REG_UART0_RXB (REG_BASE+0xd010) -#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) -#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) -#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) - -/********************/ -/* UART 1 */ -/********************/ -#define UART1_BASE (REG_BASE+0xe000) -#define REG_UART1_LCON (REG_BASE+0xe000) -#define REG_UART1_CTRL (REG_BASE+0xe004) -#define REG_UART1_STAT (REG_BASE+0xe008) -#define REG_UART1_TXB (REG_BASE+0xe00c) -#define REG_UART1_RXB (REG_BASE+0xe010) -#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) -#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) -#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) - -/********************/ -/* Timer Register */ -/********************/ -#define REG_TMOD (REG_BASE+0x6000) -#define REG_TDATA0 (REG_BASE+0x6004) -#define REG_TDATA1 (REG_BASE+0x6008) -#define REG_TCNT0 (REG_BASE+0x600c) -#define REG_TCNT1 (REG_BASE+0x6010) - -/**********************/ -/* I/O Port Interface */ -/**********************/ -#define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) - -/*********************************/ -/* Interrupt Controller Register */ -/*********************************/ -#define REG_INTMODE (REG_BASE+0x4000) -#define REG_INTPEND (REG_BASE+0x4004) -#define REG_INTMASK (REG_BASE+0x4008) - -#define REG_INTPRI0 (REG_BASE+0x400c) -#define REG_INTPRI1 (REG_BASE+0x4010) -#define REG_INTPRI2 (REG_BASE+0x4014) -#define REG_INTPRI3 (REG_BASE+0x4018) -#define REG_INTPRI4 (REG_BASE+0x401c) -#define REG_INTPRI5 (REG_BASE+0x4020) -#define REG_INTOFFSET (REG_BASE+0x4024) -#define REG_INTPNDPRI (REG_BASE+0x4028) -#define REG_INTPNDTST (REG_BASE+0x402C) - -/*********************************/ -/* CACHE CONTROL MASKS */ -/*********************************/ -#define CACHE_STALL (0x00000001) -#define CACHE_ENABLE (0x00000002) -#define CACHE_WRITE_BUFF (0x00000004) -#define CACHE_MODE (0x00000030) -#define CACHE_MODE_00 (0x00000000) -#define CACHE_MODE_01 (0x00000010) -#define CACHE_MODE_10 (0x00000020) - -/*********************************/ -/* CACHE RAM BASE ADDRESSES */ -/*********************************/ -#define CACHE_SET0_RAM (0x10000000) -#define CACHE_SET1_RAM (0x10800000) -#define CACHE_TAG_RAM (0x11000000) - -/*********************************/ -/* CACHE_DISABLE MASK */ -/*********************************/ -#define CACHE_DISABLE_MASK (0x04000000) - -#define GET_REG(reg) (*((volatile u32 *)(reg))) -#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) -#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) -#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) -#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) -#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) -#define GET__U8(reg) (*((volatile u8 *)(reg))) - -#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) -#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) -#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } -#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } - -/***********************************/ -/* CLOCK CONSTANTS -- 50 MHz Clock */ -/***********************************/ - -#define CLK_FREQ_MHZ (50) -#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ -#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ - -/*********************************************************/ -/* TIMER MODE REGISTER */ -/*********************************************************/ -#define TM0_RUN 0x01 /* Timer 0 enable */ -#define TM0_TOGGLE 0x02 /* 0, interval mode */ -#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ -#define TM1_RUN 0x08 /* Timer 1 enable */ -#define TM1_TOGGLE 0x10 /* 0, interval mode */ -#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ - - -/*********************************/ -/* INTERRUPT SOURCES */ -/*********************************/ -#define INT_EXTINT0 0 -#define INT_EXTINT1 1 -#define INT_EXTINT2 2 -#define INT_EXTINT3 3 -#define INT_UARTTX0 4 -#define INT_UARTRX0 5 -#define INT_UARTTX1 6 -#define INT_UARTRX1 7 -#define INT_GDMA0 8 -#define INT_GDMA1 9 -#define INT_TIMER0 10 -#define INT_TIMER1 11 -#define INT_HDLCTXA 12 -#define INT_HDLCRXA 13 -#define INT_HDLCTXB 14 -#define INT_HDLCRXB 15 -#define INT_BDMATX 16 -#define INT_BDMARX 17 -#define INT_MACTX 18 -#define INT_MACRX 19 -#define INT_IIC 20 -#define INT_GLOBAL 21 -#define N_IRQS (21) - -#ifndef __ASSEMBLER__ -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -#endif - -#endif /* __S3C4510_h */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index cae15f9..fb0969c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -34,7 +34,6 @@ COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o -COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c deleted file mode 100644 index aa378e1..0000000 --- a/drivers/serial/s3c4510b_uart.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune curt@cucy.com - * - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * MODULE: $Id:$ - * Description: UART/Serial interface for Samsung S3C4510B SoC - * Runtime Env: ARM7TDMI - * Change History: - * 03-02-04 Create (Curt Brune) curt@cucy.com - * - */ - -#include <common.h> - -#include <asm/hardware.h> -#include "s3c4510b_uart.h" - -DECLARE_GLOBAL_DATA_PTR; - -static UART *uart; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while( uart->m_stat.bf.rxReady) { - tmp = uart->m_rx; - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while( !uart->m_stat.bf.txBufEmpty); - - return 0; -} - - -void serial_setbrg (void) -{ - UART_LINE_CTRL ulctrl; - UART_CTRL uctrl; - UART_BAUD_DIV ubd; - - serial_flush_output(); - serial_flush_input(); - - /* control register */ - uctrl.ui = 0x0; - uctrl.bf.rxMode = 0x1; - uctrl.bf.rxIrq = 0x0; - uctrl.bf.txMode = 0x1; - uctrl.bf.DSR = 0x0; - uctrl.bf.sendBreak = 0x0; - uctrl.bf.loopBack = 0x0; - uart->m_ctrl.ui = uctrl.ui; - - /* line control register */ - ulctrl.ui = 0x0; - ulctrl.bf.wordLen = 0x3; /* 8 bit data */ - ulctrl.bf.nStop = 0x0; /* 1 stop bit */ - ulctrl.bf.parity = 0x0; /* no parity */ - ulctrl.bf.clk = 0x0; /* internal clock */ - ulctrl.bf.infra_red = 0x0; /* no infra_red */ - uart->m_lineCtrl.ui = ulctrl.ui; - - ubd.ui = 0x0; - - /* see table on page 10-15 in SAMSUNG S3C4510B manual */ - /* get correct divisor */ - switch(gd->baudrate) { - case 1200: ubd.bf.cnt0 = 1301; break; - case 2400: ubd.bf.cnt0 = 650; break; - case 4800: ubd.bf.cnt0 = 324; break; - case 9600: ubd.bf.cnt0 = 162; break; - case 19200: ubd.bf.cnt0 = 80; break; - case 38400: ubd.bf.cnt0 = 40; break; - case 57600: ubd.bf.cnt0 = 26; break; - case 115200: ubd.bf.cnt0 = 13; break; - } - - uart->m_baudDiv.ui = ubd.ui; - uart->m_baudCnt = 0x0; - uart->m_baudClk = 0x0; - -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - -#if CONFIG_SERIAL1 == 1 - uart = (UART *)UART0_BASE; -#elif CONFIG_SERIAL1 == 2 - uart = (UART *)UART1_BASE; -#else -#error CONFIG_SERIAL1 not equal to 1 or 2 -#endif - - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - /* wait for room in the transmit FIFO */ - while( !uart->m_stat.bf.txBufEmpty); - - uart->m_tx = c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Test if an input byte is ready from the serial port. Returns non-zero on - * success, 0 otherwise. - */ -int serial_tstc (void) -{ - return uart->m_stat.bf.rxReady; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - int rv; - - for(;;) { - rv = serial_tstc(); - - if (rv) { - return uart->m_rx & 0xFF; - } - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } - - /* busy wait for tx complete */ - while ( !uart->m_stat.bf.txComplete); - - /* clear break */ - uart->m_ctrl.bf.sendBreak = 0; - -} diff --git a/drivers/serial/s3c4510b_uart.h b/drivers/serial/s3c4510b_uart.h deleted file mode 100644 index b06c76d..0000000 --- a/drivers/serial/s3c4510b_uart.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __UART_H -#define __UART_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune curt@cucy.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Description: S3C4510B UART register layout - */ - -/* UART LINE CONTROL register */ -typedef struct __BF_UART_LINE_CTRL { - u32 wordLen: 2; - u32 nStop: 1; - u32 parity: 3; - u32 clk: 1; - u32 infra_red: 1; - u32 unused:24; -} BF_UART_LINE_CTRL; - -typedef union _UART_LINE_CTRL { - u32 ui; - BF_UART_LINE_CTRL bf; -} UART_LINE_CTRL; - -/* UART CONTROL register */ -typedef struct __BF_UART_CTRL { - u32 rxMode: 2; - u32 rxIrq: 1; - u32 txMode: 2; - u32 DSR: 1; - u32 sendBreak: 1; - u32 loopBack: 1; - u32 unused:24; -} BF_UART_CTRL; - -typedef union _UART_CTRL { - u32 ui; - BF_UART_CTRL bf; -} UART_CTRL; - -/* UART STATUS register */ -typedef struct __BF_UART_STAT { - u32 overrun: 1; - u32 parity: 1; - u32 frame: 1; - u32 breakIrq: 1; - u32 DTR: 1; - u32 rxReady: 1; - u32 txBufEmpty: 1; - u32 txComplete: 1; - u32 unused:24; -} BF_UART_STAT; - -typedef union _UART_STAT { - u32 ui; - BF_UART_STAT bf; -} UART_STAT; - -/* UART BAUD_DIV register */ -typedef struct __BF_UART_BAUD_DIV { - u32 cnt1: 4; - u32 cnt0:12; - u32 unused:16; -} BF_UART_BAUD_DIV; - -typedef union _UART_BAUD_DIV { - u32 ui; - BF_UART_BAUD_DIV bf; -} UART_BAUD_DIV; - -/* UART register block */ -typedef struct __UART { - volatile UART_LINE_CTRL m_lineCtrl; - volatile UART_CTRL m_ctrl; - volatile UART_STAT m_stat; - volatile u32 m_tx; - volatile u32 m_rx; - volatile UART_BAUD_DIV m_baudDiv; - volatile u32 m_baudCnt; - volatile u32 m_baudClk; -} UART; - -#define NL 0x0A -#define CR 0x0D -#define BSP 0x08 -#define ESC 0x1B -#define CTRLZ 0x1A -#define RUBOUT 0x7F - -#endif
This stuff has been rotting in the tree for a while now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Curt Brune curt@cucy.com --- arch/arm/cpu/arm720t/cpu.c | 13 +- arch/arm/cpu/arm720t/interrupts.c | 118 +------ arch/arm/cpu/arm720t/start.S | 79 +---- .../include/asm/arch-arm720t/netarm_dma_module.h | 182 ---------- .../include/asm/arch-arm720t/netarm_eni_module.h | 121 ------- .../include/asm/arch-arm720t/netarm_eth_module.h | 160 --------- .../include/asm/arch-arm720t/netarm_gen_module.h | 186 ----------- .../include/asm/arch-arm720t/netarm_mem_module.h | 184 ---------- .../include/asm/arch-arm720t/netarm_registers.h | 96 ------ .../include/asm/arch-arm720t/netarm_ser_module.h | 347 ------------------- drivers/net/Makefile | 1 - drivers/net/netarm_eth.c | 352 -------------------- drivers/net/netarm_eth.h | 42 --- drivers/serial/Makefile | 1 - drivers/serial/serial_netarm.c | 190 ----------- 15 files changed, 10 insertions(+), 2062 deletions(-) delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_dma_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_eni_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_eth_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_gen_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_mem_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_registers.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_ser_module.h delete mode 100644 drivers/net/netarm_eth.c delete mode 100644 drivers/net/netarm_eth.h delete mode 100644 drivers/serial/serial_netarm.c
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 5db4146..c215ce3 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -36,6 +36,10 @@ #include <asm/hardware.h> #include <asm/system.h>
+#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) +#error No cleanup_before_linux() defined for this CPU type +#endif + int cleanup_before_linux (void) { /* @@ -45,14 +49,5 @@ int cleanup_before_linux (void) * we turn off caches etc ... * and we set the CPU-speed to 73 MHz - see start.S for details */ - -#if defined(CONFIG_NETARM) - disable_interrupts (); - /* Nothing more needed */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No cleanup before linux for IntegratorAP/CM720T as yet */ -#else -#error No cleanup_before_linux() defined for this CPU type -#endif return 0; } diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 68592b3..ed4af60 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -31,127 +31,17 @@ #include <asm/proc-armv/ptrace.h> #include <asm/hardware.h>
-#ifndef CONFIG_NETARM +#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) +#error Timer routines not defined for this CPU type +#endif + /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff)
-#else -#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) -#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) -#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) -#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK -#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) -#endif - #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No do_irq() for IntegratorAP/CM720T as yet */ -#else -#error do_irq() not defined for this CPU type -#endif -} -#endif - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* Use IntegratorAP routines in board/integratorap.c */ -#else - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ -#if defined(CONFIG_NETARM) - /* disable all interrupts */ - IRQEN = 0; - - /* operate timer 2 in non-prescale mode */ - TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) | - NETARM_GEN_TCTL_ENABLE | - NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); - - /* set timer 2 counter */ - lastdec = TIMER_LOAD_VAL; -#else -#error No timer_init() defined for this CPU type -#endif - timestamp = 0; - - return (0); -} - -#endif /* ! IntegratorAP */ - -/* - * timer without interrupts - */ - - -#if defined(CONFIG_NETARM) - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; } - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No timer routines for IntegratorAP/CM720T as yet */ -#else -#error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 2af4d33..c53c824 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -265,60 +265,7 @@ _dynsym_start_ofs: */
cpu_init_crit: -#if defined(CONFIG_NETARM) - /* - * prior to software reset : need to set pin PORTC4 to be *HRESET - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ - NETARM_GEN_PORT_DIR(0x10)) - str r1, [r0, #+NETARM_GEN_PORTC] - /* - * software reset : see HW Ref. Guide 8.2.4 : Software Service register - * for an explanation of this process - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - /* - * setup PLL and System Config - */ - ldr r0, =NETARM_GEN_MODULE_BASE - - ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ - NETARM_GEN_SYS_CFG_BUSFULL | \ - NETARM_GEN_SYS_CFG_USER_EN | \ - NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ - NETARM_GEN_SYS_CFG_BUSARB_INT | \ - NETARM_GEN_SYS_CFG_BUSMON_EN ) - - str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] - -#ifndef CONFIG_NETARM_PLL_BYPASS - ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ - NETARM_GEN_PLL_CTL_POLTST_DEF | \ - NETARM_GEN_PLL_CTL_INDIV(1) | \ - NETARM_GEN_PLL_CTL_ICP_DEF | \ - NETARM_GEN_PLL_CTL_OUTDIV(2) ) - str r1, [r0, #+NETARM_GEN_PLL_CONTROL] -#endif - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0 - ldr r0, =NETARM_GEN_MODULE_BASE - str r1, [r0, #+NETARM_GEN_INTR_ENABLE] - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific initialisation for IntegratorAP/CM720T as yet */ -#else +#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) #error No cpu_init_crit() defined for current CPU type #endif
@@ -507,28 +454,6 @@ fiq:
#endif
-#if defined(CONFIG_NETARM) - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, =NETARM_MEM_MODULE_BASE - ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] - ldr r1, =0xFFFFF000 - and r0, r1, r0 - ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE) - add r0, r1, r0 - ldr r4, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - mov pc, r0 -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific reset actions for IntegratorAP/CM720T as yet */ -#else +#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h deleted file mode 100644 index 328eaf0..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h +++ /dev/null @@ -1,182 +0,0 @@ -/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * David Smith - */ - -#ifndef __NETARM_DMA_MODULE_REGISTERS_H -#define __NETARM_DMA_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_DMA_MODULE_BASE (0xFF900000) - -#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) - -#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) -#define NETARM_DMA1A_CONTROL (0x10) -#define NETARM_DMA1A_STATUS (0x14) -#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) -#define NETARM_DMA1B_CONTROL (0x30) -#define NETARM_DMA1B_STATUS (0x34) -#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) -#define NETARM_DMA1C_CONTROL (0x50) -#define NETARM_DMA1C_STATUS (0x54) -#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) -#define NETARM_DMA1D_CONTROL (0x70) -#define NETARM_DMA1D_STATUS (0x74) - -#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) -#define NETARM_DMA2_CONTROL (0x90) -#define NETARM_DMA2_STATUS (0x94) - -#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) -#define NETARM_DMA3_CONTROL (0xB0) -#define NETARM_DMA3_STATUS (0xB4) - -#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) -#define NETARM_DMA4_CONTROL (0xD0) -#define NETARM_DMA4_STATUS (0xD4) - -#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) -#define NETARM_DMA5_CONTROL (0xF0) -#define NETARM_DMA5_STATUS (0xF4) - -#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) -#define NETARM_DMA6_CONTROL (0x110) -#define NETARM_DMA6_STATUS (0x114) - -#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) -#define NETARM_DMA7_CONTROL (0x130) -#define NETARM_DMA7_STATUS (0x134) - -#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) -#define NETARM_DMA8_CONTROL (0x150) -#define NETARM_DMA8_STATUS (0x154) - -#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) -#define NETARM_DMA9_CONTROL (0x170) -#define NETARM_DMA9_STATUS (0x174) - -#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) -#define NETARM_DMA10_CONTROL (0x190) -#define NETARM_DMA10_STATUS (0x194) - -/* select bitfield defintions */ - -/* DMA Control Register ( 0xFF90_0XX0 ) */ - -#define NETARM_DMA_CTL_ENABLE (0x80000000) - -#define NETARM_DMA_CTL_ABORT (0x40000000) - -#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) -#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) -#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) -#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) - -#define NETARM_DMA_CTL_BUS_MASK (0x30000000) - -#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) -#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) -#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) - -#define NETARM_DMA_CTL_BURST_NONE (0x00000000) -#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) -#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) - -#define NETARM_DMA_CTL_BURST_MASK (0x03000000) - -#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) - -#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) - -/* these apply only to ext xfers on DMA 3 or 4 */ - -#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) - -#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) -#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) -#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) - -#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) -#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) - -/* DMA Status Register ( 0xFF90_0XX4 ) */ - -#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) -#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) -#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) -#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) -#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) - -#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) -#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) -#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) -#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) -#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) - -#define NETARM_DMA_STAT_WRAP (0x00080000) -#define NETARM_DMA_STAT_IDONE (0x00040000) -#define NETARM_DMA_STAT_LAST (0x00020000) -#define NETARM_DMA_STAT_FULL (0x00010000) - -#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) - -/* DMA Buffer Descriptor Word 0 bitfields. */ - -#define NETARM_DMA_BD0_WRAP (0x80000000) -#define NETARM_DMA_BD0_IDONE (0x40000000) -#define NETARM_DMA_BD0_LAST (0x20000000) -#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) - -/* DMA Buffer Descriptor Word 1 bitfields. */ - -#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) -#define NETARM_DMA_BD1_FULL (0x00008000) -#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) - -#ifndef __ASSEMBLER__ - -typedef struct __NETARM_DMA_Buff_Desc_FlyBy -{ - unsigned int word0; - unsigned int word1; -} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; - -typedef struct __NETARM_DMA_Buff_Desc_M_to_M -{ - unsigned int word0; - unsigned int word1; - unsigned int word2; - unsigned int word3; -} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h deleted file mode 100644 index 317b354..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eni_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : David Smith - */ - -#ifndef __NETARM_ENI_MODULE_REGISTERS_H -#define __NETARM_ENI_MODULE_REGISTERS_H - -/* ENI unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_ENI_MODULE_BASE (0xFFA00000) -/* #endif / * CONFIG_ARCH_NETARM */ - -#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) -#define get_eni_ctl_reg_addr(minor) \ - (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) - -#define NETARM_ENI_GENERAL_CONTROL (0x00) -#define NETARM_ENI_STATUS_CONTROL (0x04) -#define NETARM_ENI_FIFO_MODE_DATA (0x08) - -#define NETARM_ENI_1284_PORT1_CONTROL (0x10) -#define NETARM_ENI_1284_PORT2_CONTROL (0x14) -#define NETARM_ENI_1284_PORT3_CONTROL (0x18) -#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) - -#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) -#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) -#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) -#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) - -#define NETARM_ENI_ENI_CONTROL (0x30) -#define NETARM_ENI_ENI_PULSED_INTR (0x34) -#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) -#define NETARM_ENI_ENI_SHARED (0x3c) - -/* select bitfield defintions */ - -/* General Control Register (0xFFA0_0000) */ - -#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) -#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) -#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) -#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) -#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) - -#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) - -/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, - 0xFFA0_0018, 0xFFA0_001c) */ - -#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) -#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) -#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) -#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) -#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) -#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) - -#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ -#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) - -#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) -#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) -#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) - -#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) -#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) -#define NETARM_ENI_1284PC_INIT (0x00020000) -#define NETARM_ENI_1284PC_HSELECT (0x00010000) -#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) -#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) -#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) -#define NETARM_ENI_1284PC_IBR (0x00001000) - -#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) -#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) -#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) -#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) - -#define NETARM_ENI_1284PC_RBCC (0x00000200) -#define NETARM_ENI_1284PC_RBCT (0x00000100) -#define NETARM_ENI_1284PC_ACK (0x00000080) -#define NETARM_ENI_1284PC_FIFO_E (0x00000040) -#define NETARM_ENI_1284PC_OBE (0x00000020) -#define NETARM_ENI_1284PC_ACK_INT (0x00000010) -#define NETARM_ENI_1284PC_BUSY (0x00000008) -#define NETARM_ENI_1284PC_PE (0x00000004) -#define NETARM_ENI_1284PC_PSELECT (0x00000002) -#define NETARM_ENI_1284PC_FAULT (0x00000001) - -#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h deleted file mode 100644 index 8f2f369..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eth_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Jackie Smith Cashion - * David Smith - */ - -#ifndef __NETARM_ETH_MODULE_REGISTERS_H -#define __NETARM_ETH_MODULE_REGISTERS_H - -/* ETH unit register offsets */ - -#define NETARM_ETH_MODULE_BASE (0xFF800000) - -#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) - -#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ -#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ -#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ -#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ -#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ -#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ - -#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ -#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ -#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ -#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG - Gap Timer Reg */ -#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back - IPG Gap Timer Reg */ -#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ -#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ -#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ -#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ -#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ -#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ -#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ -#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ -#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ -#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ -#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ -#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral - Counter */ -#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ -#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address - Filter Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address - Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) -#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) -#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ -#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) -#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) -#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) - -/* select bitfield defintions */ - -/* Ethernet General Control Register (0xFF80_0000) */ - -#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ -#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ -#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ -#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ -#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water - Mark. Start transmit - when FIFO is 50% - full. */ -#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer - Descriptor Format */ - -/* Ethernet General Status Register (0xFF80_0004) */ - -#define NETARM_ETH_GST_RXFDB (0x30000000) -#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register - Ready */ -#define NETARM_ETH_GST_RXFIFOH (0x04000000) -#define NETARM_ETH_GST_RXBR (0x02000000) -#define NETARM_ETH_GST_RXSKIP (0x01000000) - -#define NETARM_ETH_GST_TXBC (0x00020000) - - -/* Ethernet Transmit Status Register (0xFF80_0010) */ - -#define NETARM_ETH_TXSTAT_TXOK (0x00008000) - - -/* Ethernet Receive Status Register (0xFF80_0014) */ - -#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) -#define NETARM_ETH_RXSTAT_RXOK (0x00002000) - - -/* PCS Configuration Register (0xFF80_0408) */ - -#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ -#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ -#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ -#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ - -/* STL Configuration Register (0xFF80_0410) */ - -#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ -#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ - -/* MAC Configuration Register (0xFF80_0400) */ - -#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit - Frame Sizes */ -#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames - to 64 Bytes */ -#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit - Frames */ - -/* MII (PHY) Command Register (0xFF80_0540) */ - -#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ - -/* MII Indicators Register (0xFF80_0550) */ - -#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with - Read/Write */ - -/* SAL Station Address Filter Register (0xFF80_05C0) */ - -#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ -#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast - Packets */ -#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets - using Hash Table */ -#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast - Packets */ - - -#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h deleted file mode 100644 index 13656a3..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_gen_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., art@videon-central.com - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_GEN_MODULE_REGISTERS_H -#define __NETARM_GEN_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_GEN_MODULE_BASE (0xFFB00000) - -#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) - -#define NETARM_GEN_SYSTEM_CONTROL (0x00) -#define NETARM_GEN_STATUS_CONTROL (0x04) -#define NETARM_GEN_PLL_CONTROL (0x08) -#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) - -#define NETARM_GEN_TIMER1_CONTROL (0x10) -#define NETARM_GEN_TIMER1_STATUS (0x14) -#define NETARM_GEN_TIMER2_CONTROL (0x18) -#define NETARM_GEN_TIMER2_STATUS (0x1c) - -#define NETARM_GEN_PORTA (0x20) -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORTB (0x24) -#endif -#define NETARM_GEN_PORTC (0x28) - -#define NETARM_GEN_INTR_ENABLE (0x30) -#define NETARM_GEN_INTR_ENABLE_SET (0x34) -#define NETARM_GEN_INTR_ENABLE_CLR (0x38) -#define NETARM_GEN_INTR_STATUS_EN (0x34) -#define NETARM_GEN_INTR_STATUS_RAW (0x38) - -#define NETARM_GEN_CACHE_CONTROL1 (0x40) -#define NETARM_GEN_CACHE_CONTROL2 (0x44) - -/* select bitfield definitions */ - -/* System Control Register ( 0xFFB0_0000 ) */ - -#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) -#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) - -#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) -#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) - -#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) - -#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) -#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) -#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) -#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) -#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) -#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) - -#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) -#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) -#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) -#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) - -#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) -#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) - -#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) -#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) - -#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) - -#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) - -#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) - -#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) - -#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) - -#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) - -/* PLL Control Register ( 0xFFB0_0008 ) */ - -#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) - -#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ - NETARM_GEN_PLL_CTL_PLLCNT_MASK) - -/* Defaults for POLTST and ICP Fields in PLL CTL */ -#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) -#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) -#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) -#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) - - -/* Software Service Register ( 0xFFB0_000C ) */ - -#define NETARM_GEN_SW_SVC_RESETA (0x123) -#define NETARM_GEN_SW_SVC_RESETB (0x321) - -/* PORT C Register ( 0xFFB0_0028 ) */ - -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) -#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) -#else -#define NETARM_GEN_PORT_MODE(x) ((x)<<24) -#define NETARM_GEN_PORT_DIR(x) ((x)<<16) -#define NETARM_GEN_PORT_CSF(x) ((x)<<8) -#endif - -/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ - -#define NETARM_GEN_TCTL_ENABLE (0x80000000) -#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) - -#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) -#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) - -#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) -#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) - -#define NETARM_GEN_TSTAT_INTPEN (0x40000000) -#if ~defined(CONFIG_NETARM_NS7520) -#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) -#else -#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) -#endif - -/* prescale to msecs conversion */ - -#if !defined(CONFIG_NETARM_PLL_BYPASS) -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) - -#else -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h deleted file mode 100644 index c650c3b..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_mem_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., art@videon-central.com - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_MEM_MODULE_REGISTERS_H -#define __NETARM_MEM_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_MEM_MODULE_BASE (0xFFC00000) - -#define NETARM_MEM_MODULE_CONFIG (0x00) -#define NETARM_MEM_CS0_BASE_ADDR (0x10) -#define NETARM_MEM_CS0_OPTIONS (0x14) -#define NETARM_MEM_CS1_BASE_ADDR (0x20) -#define NETARM_MEM_CS1_OPTIONS (0x24) -#define NETARM_MEM_CS2_BASE_ADDR (0x30) -#define NETARM_MEM_CS2_OPTIONS (0x34) -#define NETARM_MEM_CS3_BASE_ADDR (0x40) -#define NETARM_MEM_CS3_OPTIONS (0x44) -#define NETARM_MEM_CS4_BASE_ADDR (0x50) -#define NETARM_MEM_CS4_OPTIONS (0x54) - -/* select bitfield defintions */ - -/* Module Configuration Register ( 0xFFC0_0000 ) */ - -#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) -#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) - -#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) -#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) -#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) -#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) - -#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) - -#define NETARM_MEM_CFG_A27_ADDR (0x00080000) -#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) - -#define NETARM_MEM_CFG_A26_ADDR (0x00040000) -#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) - -#define NETARM_MEM_CFG_A25_ADDR (0x00020000) -#define NETARM_MEM_CFG_A25_BLAST (0x00000000) - -#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) - - -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it to verify */ -/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ -/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ - ) - (1) ) << (24))) - -#if 0 -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it toverify */ -/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ - ) - (1) ) << (24))) -#endif - -/* Base Address Registers (0xFFC0_00X0) */ - -#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) - -/* macro to define base */ - -#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_BAR_DRAM_FP (0x00000000) -#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) -#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) - -#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) - -#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) - -#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) - -#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) - -#define NETARM_MEM_BAR_BURST_EN (0x00000004) - -#define NETARM_MEM_BAR_WRT_PROT (0x00000002) - -#define NETARM_MEM_BAR_VALID (0x00000001) - -/* Option Registers (0xFFC0_00X4) */ - -/* macro to define which bits of the base are significant */ - -#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) - -#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) - -#define NETARM_MEM_OPT_BCYC_1 (0x00000000) -#define NETARM_MEM_OPT_BCYC_2 (0x00000040) -#define NETARM_MEM_OPT_BCYC_3 (0x00000080) -#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) - -#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) -#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) -#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) -#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) - -#define NETARM_MEM_OPT_32BIT (0x00000000) -#define NETARM_MEM_OPT_16BIT (0x00000004) -#define NETARM_MEM_OPT_8BIT (0x00000008) -#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) - -#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) - -#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) -#define NETARM_MEM_OPT_READ_SYNC (0x00000002) - -#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) -#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) - -#ifdef CONFIG_NETARM_NS7520 -/* The NS7520 has a second options register for each chip select */ -#define NETARM_MEM_CS0_OPTIONS_B (0x18) -#define NETARM_MEM_CS1_OPTIONS_B (0x28) -#define NETARM_MEM_CS2_OPTIONS_B (0x38) -#define NETARM_MEM_CS3_OPTIONS_B (0x48) -#define NETARM_MEM_CS4_OPTIONS_B (0x58) - -/* Option B Registers (0xFFC0_00x8) */ -#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) -#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) - -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h deleted file mode 100644 index fa88128..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_registers.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_registers.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., art@videon-central.com - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NET_ARM_REGISTERS_H -#define __NET_ARM_REGISTERS_H - -#include <config.h> - -/* fundamental constants : */ -/* the input crystal/clock frequency ( in Hz ) */ -#define NETARM_XTAL_FREQ_25MHz (18432000) -#define NETARM_XTAL_FREQ_33MHz (23698000) -#define NETARM_XTAL_FREQ_48MHz (48000000) -#define NETARM_XTAL_FREQ_55MHz (55000000) -#define NETARM_XTAL_FREQ_EMLIN1 (20000000) - -/* the frequency of SYS_CLK */ -#if defined(CONFIG_NETARM_EMLIN) - -/* EMLIN board: 33 MHz (exp.) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV2) - -/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV4) - -/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with - NETARM_XTAL_FREQ_25MHz) 4 */ -#define NETARM_PLL_COUNT_VAL 4 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET50) - -/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 8 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#else /* CONFIG_NETARM_NS7520 */ - -#define NETARM_PLL_COUNT_VAL 0 - -#if defined(CONFIG_BOARD_UNC20) -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz -#else -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz -#endif - -#endif - -/* #include "arm_registers.h" */ -#include <asm/arch/netarm_gen_module.h> -#include <asm/arch/netarm_mem_module.h> -#include <asm/arch/netarm_ser_module.h> -#include <asm/arch/netarm_eni_module.h> -#include <asm/arch/netarm_dma_module.h> -#include <asm/arch/netarm_eth_module.h> - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h deleted file mode 100644 index 6fbae11..0000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_ser_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * Clark Williams - */ - -#ifndef __NETARM_SER_MODULE_REGISTERS_H -#define __NETARM_SER_MODULE_REGISTERS_H - -#ifndef __ASSEMBLER__ - -/* (--sub)#include "types.h" */ - -/* serial channel control structure */ -typedef struct { - u32 ctrl_a; - u32 ctrl_b; - u32 status_a; - u32 bitrate; - u32 fifo; - u32 rx_buf_timer; - u32 rx_char_timer; - u32 rx_match; - u32 rx_match_mask; - u32 ctrl_c; - u32 status_b; - u32 status_c; - u32 fifo_last; - u32 unused[3]; -} netarm_serial_channel_t; - -#endif - -/* SER unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_SER_MODULE_BASE (0xFFD00000) -/* #else */ -/* extern serial_channel_t netarm_dummy_registers[]; */ -/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ -/* #ifndef NETARM_XTAL_FREQ */ -/* #define NETARM_XTAL_FREQ 18432000 */ -/* #endif */ -/* #endif */ - -/* calculate the sysclk value from the pll setting */ -#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ - ( NETARM_PLL_COUNT_VAL + 3 )) - -#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) - -#define NETARM_SER_CH1_CTRL_A (0x00) -#define NETARM_SER_CH1_CTRL_B (0x04) -#define NETARM_SER_CH1_STATUS_A (0x08) -#define NETARM_SER_CH1_BITRATE (0x0C) -#define NETARM_SER_CH1_FIFO (0x10) -#define NETARM_SER_CH1_RX_BUF_TMR (0x14) -#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) -#define NETARM_SER_CH1_RX_MATCH (0x1c) -#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) -#define NETARM_SER_CH1_CTRL_C (0x24) -#define NETARM_SER_CH1_STATUS_B (0x28) -#define NETARM_SER_CH1_STATUS_C (0x2c) -#define NETARM_SER_CH1_FIFO_LAST (0x30) - -#define NETARM_SER_CH2_CTRL_A (0x40) -#define NETARM_SER_CH2_CTRL_B (0x44) -#define NETARM_SER_CH2_STATUS_A (0x48) -#define NETARM_SER_CH2_BITRATE (0x4C) -#define NETARM_SER_CH2_FIFO (0x50) -#define NETARM_SER_CH2_RX_BUF_TMR (0x54) -#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) -#define NETARM_SER_CH2_RX_MATCH (0x5c) -#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) -#define NETARM_SER_CH2_CTRL_C (0x64) -#define NETARM_SER_CH2_STATUS_B (0x68) -#define NETARM_SER_CH2_STATUS_C (0x6c) -#define NETARM_SER_CH2_FIFO_LAST (0x70) - -/* select bitfield defintions */ - -/* Control Register A */ - -#define NETARM_SER_CTLA_ENABLE (0x80000000) -#define NETARM_SER_CTLA_BRK (0x40000000) - -#define NETARM_SER_CTLA_STICKP (0x20000000) - -#define NETARM_SER_CTLA_P_EVEN (0x18000000) -#define NETARM_SER_CTLA_P_ODD (0x08000000) -#define NETARM_SER_CTLA_P_NONE (0x00000000) - -/* if you read the errata, you will find that the STOP bits don't work right */ -#define NETARM_SER_CTLA_2STOP (0x00000000) -#define NETARM_SER_CTLA_3STOP (0x04000000) - -#define NETARM_SER_CTLA_5BITS (0x00000000) -#define NETARM_SER_CTLA_6BITS (0x01000000) -#define NETARM_SER_CTLA_7BITS (0x02000000) -#define NETARM_SER_CTLA_8BITS (0x03000000) - -#define NETARM_SER_CTLA_CTSTX (0x00800000) -#define NETARM_SER_CTLA_RTSRX (0x00400000) - -#define NETARM_SER_CTLA_LOOP_REM (0x00200000) -#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) - -#define NETARM_SER_CTLA_GPIO2 (0x00080000) -#define NETARM_SER_CTLA_GPIO1 (0x00040000) - -#define NETARM_SER_CTLA_DTR_EN (0x00020000) -#define NETARM_SER_CTLA_RTS_EN (0x00010000) - -#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) -#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) -#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) -#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) -#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) -#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) -#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) -#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) -#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) -#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) -#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) - -#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ - |NETARM_SER_CTLA_IE_RX_FRMERR \ - |NETARM_SER_CTLA_IE_RX_PARERR \ - |NETARM_SER_CTLA_IE_RX_OVERRUN \ - |NETARM_SER_CTLA_IE_RX_RDY \ - |NETARM_SER_CTLA_IE_RX_HALF \ - |NETARM_SER_CTLA_IE_RX_FULL \ - |NETARM_SER_CTLA_IE_RX_DMAEN \ - |NETARM_SER_CTLA_IE_RX_DCD \ - |NETARM_SER_CTLA_IE_RX_RI \ - |NETARM_SER_CTLA_IE_RX_DSR) - -#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) -#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) -#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) -#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) -#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) - -#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ - |NETARM_SER_CTLA_IE_TX_EMPTY \ - |NETARM_SER_CTLA_IE_TX_HALF \ - |NETARM_SER_CTLA_IE_TX_FULL \ - |NETARM_SER_CTLA_IE_TX_DMAEN) - -/* Control Register B */ - -#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) -#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) -#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) -#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) - -#define NETARM_SER_CTLB_RBGT_EN (0x08000000) -#define NETARM_SER_CTLB_RCGT_EN (0x04000000) - -#define NETARM_SER_CTLB_UART_MODE (0x00000000) -#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) -#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) -#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) - -#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) - -#define NETARM_SER_CTLB_MAM1 (0x00040000) -#define NETARM_SER_CTLB_MAM2 (0x00020000) - -/* Status Register A */ - -#define NETARM_SER_STATA_MATCH1 (0x80000000) -#define NETARM_SER_STATA_MATCH2 (0x40000000) -#define NETARM_SER_STATA_MATCH3 (0x20000000) -#define NETARM_SER_STATA_MATCH4 (0x10000000) - -#define NETARM_SER_STATA_BGAP (0x80000000) -#define NETARM_SER_STATA_CGAP (0x40000000) - -#define NETARM_SER_STATA_RX_1B (0x00100000) -#define NETARM_SER_STATA_RX_2B (0x00200000) -#define NETARM_SER_STATA_RX_3B (0x00300000) -#define NETARM_SER_STATA_RX_4B (0x00000000) - -/* downshifted values */ - -#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) -#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) -#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) -#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) - -#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) -#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ - >> 20) - -#define NETARM_SER_STATA_DCD (0x00080000) -#define NETARM_SER_STATA_RI (0x00040000) -#define NETARM_SER_STATA_DSR (0x00020000) -#define NETARM_SER_STATA_CTS (0x00010000) - -#define NETARM_SER_STATA_RX_BRK (0x00008000) -#define NETARM_SER_STATA_RX_FRMERR (0x00004000) -#define NETARM_SER_STATA_RX_PARERR (0x00002000) -#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) -#define NETARM_SER_STATA_RX_RDY (0x00000800) -#define NETARM_SER_STATA_RX_HALF (0x00000400) -#define NETARM_SER_STATA_RX_CLOSED (0x00000200) -#define NETARM_SER_STATA_RX_FULL (0x00000100) -#define NETARM_SER_STATA_RX_DCD (0x00000080) -#define NETARM_SER_STATA_RX_RI (0x00000040) -#define NETARM_SER_STATA_RX_DSR (0x00000020) - -#define NETARM_SER_STATA_TX_CTS (0x00000010) -#define NETARM_SER_STATA_TX_RDY (0x00000008) -#define NETARM_SER_STATA_TX_HALF (0x00000004) -#define NETARM_SER_STATA_TX_FULL (0x00000002) -#define NETARM_SER_STATA_TX_DMAEN (0x00000001) - -/* you have to clear all receive signals to get the fifo to move forward */ -#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ - NETARM_SER_STATA_RX_FRMERR | \ - NETARM_SER_STATA_RX_PARERR | \ - NETARM_SER_STATA_RX_OVERRUN | \ - NETARM_SER_STATA_RX_HALF | \ - NETARM_SER_STATA_RX_CLOSED | \ - NETARM_SER_STATA_RX_FULL | \ - NETARM_SER_STATA_RX_DCD | \ - NETARM_SER_STATA_RX_RI | \ - NETARM_SER_STATA_RX_DSR | \ - NETARM_SER_STATA_TX_CTS ) - -/* Bit Rate Registers */ - -#define NETARM_SER_BR_EN (0x80000000) -#define NETARM_SER_BR_TMODE (0x40000000) - -#define NETARM_SER_BR_RX_CLK_INT (0x00000000) -#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) -#define NETARM_SER_BR_TX_CLK_INT (0x00000000) -#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) - -#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) -#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) - -#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) -#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) -#define NETARM_SER_BR_CLK_OUT1A (0x02000000) -#define NETARM_SER_BR_CLK_OUT2A (0x03000000) - -#define NETARM_SER_BR_TX_CLK_INV (0x00800000) -#define NETARM_SER_BR_RX_CLK_INV (0x00400000) - -/* complete settings assuming system clock input is 18MHz */ - -#define NETARM_SER_BR_MASK (0x000007FF) - -/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ -/* from section 7.5.4 of HW Ref Guide */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -/* -#else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -#endif -*/ - -/* Receive Buffer Gap Timer */ - -#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) -#define NETARM_SER_RX_GAP_MASK (0x00003FFF) - -/* rx gap is a function of bit rate x */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -/* -#else -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif -*/ - -#if 0 -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif - -#define MIN_BAUD_RATE 600 -#define MAX_BAUD_RATE 115200 - -/* the default BAUD rate for the BOOTLOADER, there is a separate */ -/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */ -#define DEFAULT_BAUD_RATE 9600 -#define NETARM_SER_FIFO_SIZE 32 -#define MIN_GAP 0 - -#endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 430f90c..9b6a557 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -59,7 +59,6 @@ COBJS-$(CONFIG_MVGBE) += mvgbe.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o -COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o COBJS-$(CONFIG_NETCONSOLE) += netconsole.o COBJS-$(CONFIG_NS8382X) += ns8382x.o COBJS-$(CONFIG_PCNET) += pcnet.o diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c deleted file mode 100644 index 325f16c..0000000 --- a/drivers/net/netarm_eth.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (C) 2004 IMMS gGmbH <www.imms.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * author(s): Thomas Elste, info@elste.org - * (some parts derived from uCLinux Netarm Ethernet Driver) - */ - - -#include <common.h> -#include <command.h> -#include <net.h> -#include "netarm_eth.h" -#include <asm/arch/netarm_registers.h> - -static int na_mii_poll_busy (void); - -static void na_get_mac_addr (void) -{ - unsigned short p[3]; - char *m_addr; - char ethaddr[20]; - - m_addr = (char *) p; - - p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); - p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); - p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); - - sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - m_addr[0], m_addr[1], - m_addr[2], m_addr[3], m_addr[4], m_addr[5]); - - printf ("HW-MAC Address: %s\n", ethaddr); - - /* set env, todo: check if already an adress is set */ - setenv ("ethaddr", ethaddr); -} - -static void na_mii_write (int reg, int value) -{ - int mii_addr; - - /* Select register */ - mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; - SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); - /* Write value */ - SET_EADDR (NETARM_ETH_MII_WRITE, value); - na_mii_poll_busy (); -} - -static unsigned int na_mii_read (int reg) -{ - int mii_addr, val; - - /* Select register */ - mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; - SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); - /* do one management cycle */ - SET_EADDR (NETARM_ETH_MII_CMD, - GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); - na_mii_poll_busy (); - /* Return read value */ - val = GET_EADDR (NETARM_ETH_MII_READ); - return val; -} - -static int na_mii_poll_busy (void) -{ - ulong start; - /* arm simple, non interrupt dependent timer */ - start = get_timer(0)); - while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) { - if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { - return 1; - } - } - printf ("na_mii_busy timeout\n"); - return (0); -} - -static int na_mii_identify_phy (void) -{ - int id_reg_a = 0; - - /* get phy id register */ - id_reg_a = na_mii_read (MII_PHY_ID); - - if (id_reg_a == 0x0043) { - /* This must be an Enable or a Lucent LU3X31 PHY chip */ - return 1; - } else if (id_reg_a == 0x0013) { - /* it is an Intel LXT971A */ - return 1; - } - return (0); -} - -static int na_mii_negotiate (void) -{ - int i = 0; - - /* Enable auto-negotiation */ - na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); - /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ - /* Restart auto-negotiation */ - na_mii_write (MII_PHY_CONTROL, 0x1200); - - /* status register is 0xffff after setting the autoneg restart bit */ - while (na_mii_read (MII_PHY_STATUS) == 0xffff) { - i++; - } - - /* na_mii_read uses the timer already, so we can't use it again for - timeout checking. - Instead we just try some times. - */ - for (i = 0; i < 40000; i++) { - if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { - return 0; - } - } - /* - printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); - */ - return (1); -} - -static unsigned int na_mii_check_speed (void) -{ - unsigned int status; - - /* Read Status register */ - status = na_mii_read (MII_PHY_STATUS); - /* Check link status. If 0, default to 100 Mbps. */ - if ((status & 0x0004) == 0) { - printf ("*Warning* no link detected, set default speed to 100Mbs\n"); - return 1; - } else { - if ((na_mii_read (17) & 0x4000) != 0) { - printf ("100Mbs link detected\n"); - return 1; - } else { - printf ("10Mbs link detected\n"); - return 0; - } - } - return 0; -} - -static int reset_eth (void) -{ - int pt; - ulong start; - - na_get_mac_addr (); - pt = na_mii_identify_phy (); - - /* reset the phy */ - na_mii_write (MII_PHY_CONTROL, 0x8000); - start = get_timer(0); - while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) { - if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { - break; - } - } - if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY) - printf ("phy reset timeout\n"); - - /* set the PCS reg */ - SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | - NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); - - na_mii_negotiate (); - na_mii_check_speed (); - - /* Delay 10 millisecond. (Maybe this should be 1 second.) */ - udelay (10000); - - /* Turn receive on. - Enable statistics register autozero on read. - Do not insert MAC address on transmit. - Do not enable special test modes. */ - SET_EADDR (NETARM_ETH_STL_CFG, - (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); - - /* Set the inter-packet gap delay to 0.96us for MII. - The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG - Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG - Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ - SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); - SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); - - /* Add CRC to end of packets. - Pad packets to minimum length of 64 bytes. - Allow unlimited length transmit packets. - Receive all broadcast packets. - NOTE: Multicast addressing is NOT enabled here currently. */ - SET_EADDR (NETARM_ETH_MAC_CFG, - (NETARM_ETH_MACC_CRCEN | - NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); - SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); - - /* enable fifos */ - SET_EADDR (NETARM_ETH_GEN_CTRL, - (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); - - return (0); -} - - -extern int eth_init (bd_t * bd) -{ - reset_eth (); - return 0; -} - -extern void eth_halt (void) -{ - SET_EADDR (NETARM_ETH_GEN_CTRL, 0); -} - -/* Get a data block via Ethernet */ -extern int eth_rx (void) -{ - int i; - unsigned short rxlen; - unsigned int *addr; - unsigned int rxstatus, lastrxlen; - char *pa; - - /* RXBR is 1, data block was received */ - if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) - return 0; - - /* get status register and the length of received block */ - rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); - rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; - - if (rxlen == 0) - return 0; - - /* clear RXBR to make fifo available */ - SET_EADDR (NETARM_ETH_GEN_STAT, - GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); - - /* clear TXBC to make fifo available */ - /* According to NETARM50 data manual you just have to clear - RXBR but that has no effect. Only after clearing TXBC the - Fifo becomes readable. */ - SET_EADDR (NETARM_ETH_GEN_STAT, - GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); - - addr = (unsigned int *) NetRxPackets[0]; - pa = (char *) NetRxPackets[0]; - - /* read the fifo */ - for (i = 0; i < rxlen / 4; i++) { - *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); - addr++; - } - - if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { - /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ - lastrxlen = - (GET_EADDR (NETARM_ETH_GEN_STAT) & - NETARM_ETH_GST_RXFDB) >> 28; - *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); - switch (lastrxlen) { - case 1: - *addr &= 0xff000000; - break; - case 2: - *addr &= 0xffff0000; - break; - case 3: - *addr &= 0xffffff00; - break; - } - } - - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[0], rxlen); - - return rxlen; -} - -/* Send a data block via Ethernet. */ -extern int eth_send(void *packet, int length) -{ - int i, length32; - char *pa; - unsigned int *pa32, lastp = 0, rest; - - pa = (char *) packet; - pa32 = (unsigned int *) packet; - length32 = length / 4; - rest = length % 4; - - /* make sure there's no garbage in the last word */ - switch (rest) { - case 0: - lastp = pa32[length32]; - length32--; - break; - case 1: - lastp = pa32[length32] & 0x000000ff; - break; - case 2: - lastp = pa32[length32] & 0x0000ffff; - break; - case 3: - lastp = pa32[length32] & 0x00ffffff; - break; - } - - /* write to the fifo */ - for (i = 0; i < length32; i++) - SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); - - /* the last word is written to an extra register, this - starts the transmission */ - SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); - - /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission - went fine. But we can't use the timer for a timeout loop because - of it is used already in upper layers. So we just try some times. */ - i = 0; - while (i < 50000) { - if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) - == NETARM_ETH_TXSTAT_TXOK) - return 0; - i++; - } - - printf ("eth_send timeout\n"); - return 1; -} diff --git a/drivers/net/netarm_eth.h b/drivers/net/netarm_eth.h deleted file mode 100644 index 8edab82..0000000 --- a/drivers/net/netarm_eth.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2003 IMMS gGmbH <www.imms.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * author(s): Thomas Elste, info@elste.org - */ - -#include <asm/types.h> -#include <config.h> - -#ifdef CONFIG_DRIVER_NETARMETH - -#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val -#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) - -#define NA_MII_POLL_BUSY_DELAY 900 - -/* MII negotiation timeout value - 500 jiffies = 5 seconds */ -#define NA_MII_NEGOTIATE_DELAY 30 - -/* Registers in the physical layer chip */ -#define MII_PHY_CONTROL 0 -#define MII_PHY_STATUS 1 -#define MII_PHY_ID 2 -#define MII_PHY_AUTONEGADV 4 - -#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index fb0969c..5f0e714 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -44,7 +44,6 @@ COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o -COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c deleted file mode 100644 index d04790d..0000000 --- a/drivers/serial/serial_netarm.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Serial Port stuff - taken from Linux - * - * (C) Copyright 2002 - * MAZeT GmbH <www.mazet.de> - * Stephan Linz linz@mazet.de, linz@li-pro.net - * - * (c) 2004 - * IMMS gGmbH <www.imms.de> - * Thomas Elste info@elste.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) -#if !defined(CONFIG_NETARM_NS7520) -#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) -#else -#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) -#endif - -/* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ -{ \ - ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \ - while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ - if (get_timer(0) > tmo) \ - break; \ - } \ -} - - -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); - -extern void _netarm_led_FAIL1(void); - -/* - * Setup both serial i/f with given baudrate - */ -void serial_setbrg (void) -{ - /* set 0 ... make sure pins are configured for serial */ -#if !defined(CONFIG_NETARM_NS7520) - PORTA = PORTB = - NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#else - PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); - PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#endif - - /* first turn em off */ - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; - - /* clear match register, we don't need it */ - serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; - - /* setup bit rate generator and rx buffer gap timer (1 byte only) */ - if ((gd->baudrate >= MIN_BAUD_RATE) - && (gd->baudrate <= MAX_BAUD_RATE)) { - serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = - NETARM_SER_BR_X16 (gd->baudrate); - serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = - 0; - serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = - NETARM_SER_RXGAP (gd->baudrate); - } else { - hang (); - } - - /* setup port mode */ - serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = - ( NETARM_SER_CTLB_RCGT_EN | - NETARM_SER_CTLB_UART_MODE); - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = - ( NETARM_SER_CTLA_ENABLE | - NETARM_SER_CTLA_P_NONE | - /* see errata */ - NETARM_SER_CTLA_2STOP | - NETARM_SER_CTLA_8BITS | - NETARM_SER_CTLA_DTR_EN | - NETARM_SER_CTLA_RTS_EN); -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int serial_init (void) -{ - serial_setbrg (); - return 0; -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - volatile unsigned char *fifo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); - TXWAITRDY (serial_reg_ch1); - *fifo = c; -} - -/* - * Test of a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_tstc(void) -{ - return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_getc (void) -{ - unsigned int ch_uint; - volatile unsigned int *fifo; - volatile unsigned char *fifo_char = NULL; - int buf_count = 0; - - while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) - /* NOP */ ; - - fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); - fifo_char = (unsigned char *) &ch_uint; - ch_uint = *fifo; - - buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); - switch (buf_count) { - case NETARM_SER_STATA_RXFDB_4BYTES: - buf_count = 4; - break; - case NETARM_SER_STATA_RXFDB_3BYTES: - buf_count = 3; - break; - case NETARM_SER_STATA_RXFDB_2BYTES: - buf_count = 2; - break; - case NETARM_SER_STATA_RXFDB_1BYTES: - buf_count = 1; - break; - default: - /* panic, be never here */ - break; - } - - serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; - - return ch_uint & 0xff; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -}
Signed-off-by: Marek Vasut marex@denx.de Cc: Oliver Brown obrown@adventnetworks.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de --- arch/arm/cpu/arm1176/tnetv107x/Makefile | 2 +- drivers/watchdog/Makefile | 1 + .../cpu/arm1176/tnetv107x/wdt.c => drivers/watchdog/tnetv107x_wdt.c | 0 include/configs/tnetv107x_evm.h | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) rename arch/arm/cpu/arm1176/tnetv107x/wdt.c => drivers/watchdog/tnetv107x_wdt.c (100%)
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile index c63dc92..c1d4d67 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o +COBJS += aemif.o clock.o init.o mux.o timer.o SOBJS += lowlevel_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5579bf2..923acb9 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o +COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/drivers/watchdog/tnetv107x_wdt.c similarity index 100% rename from arch/arm/cpu/arm1176/tnetv107x/wdt.c rename to drivers/watchdog/tnetv107x_wdt.c diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 2272ad2..fd4ec84 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM +#define CONFIG_TNETV107X_WATCHDOG #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_DISABLE_TCM
Hi Marek,
On Sat, 21 Jul 2012 17:02:21 +0200, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Oliver Brown obrown@adventnetworks.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
arch/arm/cpu/arm1176/tnetv107x/Makefile | 2 +- drivers/watchdog/Makefile | 1 + .../cpu/arm1176/tnetv107x/wdt.c => drivers/watchdog/tnetv107x_wdt.c | 0 include/configs/tnetv107x_evm.h | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) rename arch/arm/cpu/arm1176/tnetv107x/wdt.c => drivers/watchdog/tnetv107x_wdt.c (100%)
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile index c63dc92..c1d4d67 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o +COBJS += aemif.o clock.o init.o mux.o timer.o SOBJS += lowlevel_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5579bf2..923acb9 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o +COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/drivers/watchdog/tnetv107x_wdt.c similarity index 100% rename from arch/arm/cpu/arm1176/tnetv107x/wdt.c rename to drivers/watchdog/tnetv107x_wdt.c diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 2272ad2..fd4ec84 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM +#define CONFIG_TNETV107X_WATCHDOG #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_DISABLE_TCM
Applied to u-boot-arm/master, thanks!
Amicalement,
Signed-off-by: Marek Vasut marex@denx.de Cc: David Müller d.mueller@elsoft.ch Cc: Minkyu Kang mk7.kang@samsung.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de --- arch/arm/cpu/arm920t/s3c24x0/Makefile | 3 - arch/arm/cpu/arm920t/s3c24x0/usb.c | 71 -------------------- drivers/usb/host/Makefile | 1 + .../usb_ohci.c => drivers/usb/host/ohci-s3c24xx.c | 46 ++++++++++++- .../usb_ohci.h => drivers/usb/host/ohci-s3c24xx.h | 0 include/configs/VCMA9.h | 1 + include/configs/smdk2410.h | 1 + 7 files changed, 48 insertions(+), 75 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/s3c24x0/usb.c rename arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c => drivers/usb/host/ohci-s3c24xx.c (97%) rename arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h => drivers/usb/host/ohci-s3c24xx.h (100%)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile index 0029700..808ab8f 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/Makefile +++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile @@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o COBJS-y += speed.o COBJS-y += timer.o -COBJS-y += usb.o -COBJS-y += usb_ohci.o -
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c deleted file mode 100644 index 226a3f6..0000000 --- a/arch/arm/cpu/arm920t/s3c24x0/usb.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2006 - * DENX Software Engineering mk@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) - -#include <asm/arch/s3c24x0_cpu.h> -#include <asm/io.h> - -int usb_cpu_init(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); - /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); - - /* - * Enable USB host clock. - */ - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); - - return 0; -} - -int usb_cpu_stop(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - /* may not want to do this */ - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -int usb_cpu_init_fail(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6de9164..a5c1ef4 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o +COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
# echi COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/drivers/usb/host/ohci-s3c24xx.c similarity index 97% rename from arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c rename to drivers/usb/host/ohci-s3c24xx.c index cf0335c..127c1f9 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -42,7 +42,7 @@ #include <asm/io.h> #include <malloc.h> #include <usb.h> -#include "usb_ohci.h" +#include "ohci-s3c24xx.h"
#define OHCI_USE_NPS /* force NoPowerSwitching mode */ #undef OHCI_VERBOSE_DEBUG /* not always helpful */ @@ -1755,3 +1755,47 @@ int usb_lowlevel_stop(void) }
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ + +#if defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) + +int usb_cpu_init(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); + + /* + * Set the 48 MHz UPLL clocking. Values are taken from + * "PLL value selection guide", 6-23, s3c2400_UM.pdf. + */ + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); + + /* + * Enable USB host clock. + */ + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); + + return 0; +} + +int usb_cpu_stop(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + /* may not want to do this */ + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + return 0; +} + +int usb_cpu_init_fail(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + return 0; +} + +#endif /* defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h b/drivers/usb/host/ohci-s3c24xx.h similarity index 100% rename from arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h rename to drivers/usb/host/ohci-s3c24xx.h diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 6ad4a6b..5deb56a 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -126,6 +126,7 @@
/* USB support (currently only works with D-cache off) */ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 8792c85..351f137 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -68,6 +68,7 @@ * USB support (currently only works with D-cache off) ************************************************************/ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap-common/Makefile | 3 --- drivers/gpio/Makefile | 1 + arch/arm/cpu/armv7/omap-common/gpio.c => drivers/gpio/omap_gpio.c | 0 include/configs/cm_t35.h | 1 + include/configs/devkit8000.h | 2 ++ include/configs/dig297.h | 1 + include/configs/igep00x0.h | 1 + include/configs/mcx.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_mvblx.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_pandora.h | 1 + include/configs/omap3_zoom2.h | 1 + include/configs/omap4_common.h | 1 + include/configs/omap5_evm.h | 1 + include/configs/tam3517-common.h | 1 + 18 files changed, 17 insertions(+), 3 deletions(-) rename arch/arm/cpu/armv7/omap-common/gpio.c => drivers/gpio/omap_gpio.c (100%)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 2a6625f..d37b22d 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -29,9 +29,6 @@ SOBJS := reset.o
COBJS := timer.o COBJS += utils.o -ifdef CONFIG_OMAP -COBJS += gpio.o -endif
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) COBJS += hwinit-common.o diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 32a2474..8958bb4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/drivers/gpio/omap_gpio.c similarity index 100% rename from arch/arm/cpu/armv7/omap-common/gpio.c rename to drivers/gpio/omap_gpio.c diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index ee4bce5..6eeb2d3 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -37,6 +37,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 037a5bb..e529099 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -36,6 +36,8 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 +#define CONFIG_OMAP_GPIO + /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 4845d51..f123675 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -45,6 +45,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 88e2e3a..727b800 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -30,6 +30,7 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 970c882..0b75460 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -27,6 +27,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_MCX /* working with mcx */ +#define CONFIG_OMAP_GPIO
#define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 657780e..382b791 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -34,6 +34,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 20192a9..b12ce2e 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -22,6 +22,7 @@ */ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP34XX /* belonging to 34XX family */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 2e1e6b9..6d4faed 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -33,6 +33,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ +#define CONFIG_OMAP_GPIO
#undef CONFIG_USE_IRQ /* no support for IRQs */
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 6a13046..30ca312 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -39,6 +39,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index d29b326..f6afb7a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -25,6 +25,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_OVERO /* working with overo */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 604b53d..28f8a3e 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -29,6 +29,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index b60ece3..98b93f8 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -36,6 +36,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 2192c2b..bc73f21 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -35,6 +35,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ +#define CONFIG_OMAP_GPIO
/* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index c5874bb..0884280 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -38,6 +38,7 @@ #define CONFIG_OMAP54XX /* which is a 54XX */ #define CONFIG_OMAP5430 /* which is in a 5430 */ #define CONFIG_5430EVM /* working with EVM */ +#define CONFIG_OMAP_GPIO
/* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 777f77c..94006e7 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -27,6 +27,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
On Sat, Jul 21, 2012 at 05:02:23PM +0200, Marek Vasut wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
Acked-by: Tom Rini trini@ti.com
Hi Marek,
On Sat, 21 Jul 2012 17:02:23 +0200, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
arch/arm/cpu/armv7/omap-common/Makefile | 3 --- drivers/gpio/Makefile | 1 + arch/arm/cpu/armv7/omap-common/gpio.c => drivers/gpio/omap_gpio.c | 0 include/configs/cm_t35.h | 1 + include/configs/devkit8000.h | 2 ++ include/configs/dig297.h | 1 + include/configs/igep00x0.h | 1 + include/configs/mcx.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm_common.h | 1 + include/configs/omap3_logic.h | 1 + include/configs/omap3_mvblx.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_pandora.h | 1 + include/configs/omap3_zoom2.h | 1 + include/configs/omap4_common.h | 1 + include/configs/omap5_evm.h | 1 + include/configs/tam3517-common.h | 1 + 18 files changed, 17 insertions(+), 3 deletions(-) rename arch/arm/cpu/armv7/omap-common/gpio.c => drivers/gpio/omap_gpio.c (100%)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 2a6625f..d37b22d 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -29,9 +29,6 @@ SOBJS := reset.o
COBJS := timer.o COBJS += utils.o -ifdef CONFIG_OMAP -COBJS += gpio.o -endif
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) COBJS += hwinit-common.o diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 32a2474..8958bb4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/drivers/gpio/omap_gpio.c similarity index 100% rename from arch/arm/cpu/armv7/omap-common/gpio.c rename to drivers/gpio/omap_gpio.c diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index ee4bce5..6eeb2d3 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -37,6 +37,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 037a5bb..e529099 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -36,6 +36,8 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 +#define CONFIG_OMAP_GPIO
/*
- 1MB into the SDRAM to allow for SPL's bss at the beginning of
SDRAM
- 64 bytes before this address should be set aside for u-boot.img's
diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 4845d51..f123675 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -45,6 +45,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 88e2e3a..727b800 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -30,6 +30,7 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 970c882..0b75460 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -27,6 +27,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_MCX /* working with mcx */ +#define CONFIG_OMAP_GPIO
#define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 657780e..382b791 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -34,6 +34,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 20192a9..b12ce2e 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -22,6 +22,7 @@ */ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP34XX /* belonging to 34XX family */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 2e1e6b9..6d4faed 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -33,6 +33,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ +#define CONFIG_OMAP_GPIO
#undef CONFIG_USE_IRQ /* no support for IRQs */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 6a13046..30ca312 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -39,6 +39,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index d29b326..f6afb7a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -25,6 +25,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_OVERO /* working with overo */ +#define CONFIG_OMAP_GPIO #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 604b53d..28f8a3e 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -29,6 +29,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index b60ece3..98b93f8 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -36,6 +36,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 2192c2b..bc73f21 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -35,6 +35,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ +#define CONFIG_OMAP_GPIO
/* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index c5874bb..0884280 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -38,6 +38,7 @@ #define CONFIG_OMAP54XX /* which is a 54XX */ #define CONFIG_OMAP5430 /* which is in a 5430 */ #define CONFIG_5430EVM /* working with EVM */ +#define CONFIG_OMAP_GPIO
/* Get CPU defs */ #include <asm/arch/cpu.h> diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 777f77c..94006e7 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -27,6 +27,7 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
When applied on top of u-boot-arm/master, this patch causes a raise in build failures. With master:
--------------------- SUMMARY ---------------------------- Boards compiled: 315 Boards with warnings but no errors: 2 ( VCMA9 smdk2410 ) ----------------------------------------------------------
With master + this patch:
--------------------- SUMMARY ---------------------------- Boards compiled: 315 Boards with errors: 23 ( mcx igep0030_nand omap3_evm_quick_nand omap3_evm omap3_pandora omap3_overo omap5_evm omap4_panda mt_ventoux igep0020_nand omap4_sdp4430 twister omap3_zoom2 igep0030 igep0020 omap3_evm_quick_mmc cm_t35 omap3_beagle am335x_evm dig297 omap3_logic omap3_mvblx devkit8000 ) Boards with warnings but no errors: 2 ( VCMA9 smdk2410 ) ----------------------------------------------------------
Typical diagnostics:
/home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_set_value': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: multiple definition of `gpio_set_value' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_get_value': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:161: multiple definition of `gpio_get_value' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:161: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_direction_input': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:195: multiple definition of `gpio_direction_input' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:195: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_direction_output': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:211: multiple definition of `gpio_direction_output' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:211: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_request': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:230: multiple definition of `gpio_request' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:230: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_free': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:243: multiple definition of `gpio_free' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:243: first defined here
Am I missing some dependency of this patch?
Amicalement,
On Fri, Aug 31, 2012 at 06:27:23PM +0200, Albert ARIBAUD wrote:
Hi Marek,
On Sat, 21 Jul 2012 17:02:23 +0200, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
[snip]
Typical diagnostics:
/home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_set_value': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: multiple definition of `gpio_set_value' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: first defined here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:
This patch is already in u-boot-arm/master :)
Dear Tom Rini,
On Fri, Aug 31, 2012 at 06:27:23PM +0200, Albert ARIBAUD wrote:
Hi Marek,
On Sat, 21 Jul 2012 17:02:23 +0200, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
[snip]
Typical diagnostics:
/home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o: In function `gpio_set_value': /home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: multiple definition of `gpio_set_value' /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:/ home/albert/src/u-boot-arm/drivers/gpio/omap_gpio.c:146: first defined
here /home/albert/src/u-boot-arm/build/omap4_panda/drivers/gpio/omap_gpio.o:
This patch is already in u-boot-arm/master :)
Heh :-)
Agreed though, this was applied a while ago through Toms tree. btw. Albert, can you please pick 1-3/3 from this crude series? I think noone will mourn for them.
Best regards, Marek Vasut
Signed-off-by: Marek Vasut marex@denx.de Cc: David Müller d.mueller@elsoft.ch Cc: Minkyu Kang mk7.kang@samsung.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de --- arch/arm/cpu/armv7/s5p-common/Makefile | 1 - drivers/watchdog/Makefile | 1 + arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c (100%)
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index f975f3f..1705399 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o COBJS-y += timer.o COBJS-y += sromc.o -COBJS-y += wdt.o COBJS-$(CONFIG_PWM) += pwm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 923acb9..bc09123 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o +COBJS-$(CONFIG_S5P) += s5p_wdt.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/s5p-common/wdt.c b/drivers/watchdog/s5p_wdt.c similarity index 100% rename from arch/arm/cpu/armv7/s5p-common/wdt.c rename to drivers/watchdog/s5p_wdt.c
Dear Marek,
On 22 July 2012 00:02, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: David Müller d.mueller@elsoft.ch Cc: Minkyu Kang mk7.kang@samsung.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
arch/arm/cpu/armv7/s5p-common/Makefile | 1 - drivers/watchdog/Makefile | 1 + arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c (100%)
applied to u-boot-samsung.
Thanks. Minkyu Kang.
Dear Minkyu Kang,
Dear Marek,
On 22 July 2012 00:02, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: David Müller d.mueller@elsoft.ch Cc: Minkyu Kang mk7.kang@samsung.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
arch/arm/cpu/armv7/s5p-common/Makefile | 1
- drivers/watchdog/Makefile |
1 + arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/cpu/armv7/s5p-common/wdt.c => drivers/watchdog/s5p_wdt.c (100%)
applied to u-boot-samsung.
Good, thanks! Please don't forget to clean up patchwork too (if you didn't already).
Best regards, Marek Vasut
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de --- arch/arm/cpu/armv7/tegra2/usb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c index 5f2b243..ea7f701 100644 --- a/arch/arm/cpu/armv7/tegra2/usb.c +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -158,7 +158,8 @@ static void set_host_mode(struct fdt_usb *config) } }
-void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +static void usbf_reset_controller(struct fdt_usb *config, + struct usb_ctlr *usbctlr) { /* Reset the USB controller with 2us delay */ reset_periph(config->periph_id, 2); @@ -382,8 +383,8 @@ int tegrausb_stop_port(void) return 0; }
-int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, - struct fdt_usb *config) +static int fdt_decode_usb(const void *blob, int node, + unsigned osc_frequency_mhz, struct fdt_usb *config) { const char *phy, *mode;
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Acked-by: Simon Glass sjg@chromium.org
arch/arm/cpu/armv7/tegra2/usb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c index 5f2b243..ea7f701 100644 --- a/arch/arm/cpu/armv7/tegra2/usb.c +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -158,7 +158,8 @@ static void set_host_mode(struct fdt_usb *config) } }
-void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +static void usbf_reset_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr){ /* Reset the USB controller with 2us delay */ reset_periph(config->periph_id, 2); @@ -382,8 +383,8 @@ int tegrausb_stop_port(void) return 0; }
-int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
struct fdt_usb *config)+static int fdt_decode_usb(const void *blob, int node,
unsigned osc_frequency_mhz, struct fdt_usb *config){ const char *phy, *mode;
-- 1.7.10.4
Dear Simon Glass,
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Acked-by: Simon Glass sjg@chromium.org
Simon, can you please pick up this one separatelly through your tree? I already agreed with Tom to rip this apart as it's not really a series, but rather a dump of random patches and cleanups. This is basically the first chapter of my crusade towards making you crazy from breakage ... I mean ... cleaning up drivers scattered across arch/ directory and moving them to drivers/ directory ...
Best regards, Marek Vasut
Marek,
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Monday, July 23, 2012 11:24 PM To: Simon Glass Cc: u-boot@lists.denx.de; u-boot-dm@lists.denx.de; Tom Warren; Wolfgang Denk; Albert Aribaud Subject: Re: [PATCH 08/10] dm: tegra: Staticize local functions in usb.c
Dear Simon Glass,
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Acked-by: Simon Glass sjg@chromium.org
Simon, can you please pick up this one separatelly through your tree? I already agreed with Tom to rip this apart as it's not really a series, but rather a dump of random patches and cleanups. This is basically the first chapter of my crusade towards making you crazy from breakage ... I mean ... cleaning up drivers scattered across arch/ directory and moving them to drivers/ directory ...
Simon doesn't manage the Tegra repo, I do. Simon is the most prodigious Tegra submitter by far, but he's a Google employee, not an Nvidian.
I don't recall any conversation with you WRT this patch series ('rip this apart'?), and see nothing in my archived U-Boot emails about it - is there another Tom (Rini? or Rix?) that you had this convo with?
Regardless, I'll apply this to u-boot-tegra/master & /next since the changes are trivial. Note that any future Tegra changes will need to be rebased against master, as Allen's SPL rewrite/rework caused a lot of files to move around.
Tom
Dear Tom Warren,
Marek,
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Monday, July 23, 2012 11:24 PM To: Simon Glass Cc: u-boot@lists.denx.de; u-boot-dm@lists.denx.de; Tom Warren; Wolfgang Denk; Albert Aribaud Subject: Re: [PATCH 08/10] dm: tegra: Staticize local functions in usb.c
Dear Simon Glass,
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Acked-by: Simon Glass sjg@chromium.org
Simon, can you please pick up this one separatelly through your tree? I already agreed with Tom to rip this apart as it's not really a series, but rather a dump of random patches and cleanups. This is basically the first chapter of my crusade towards making you crazy from breakage ... I mean ... cleaning up drivers scattered across arch/ directory and moving them to drivers/ directory ...
Simon doesn't manage the Tegra repo, I do. Simon is the most prodigious Tegra submitter by far, but he's a Google employee, not an Nvidian.
Hehe ... and I always kept torturing Simon about since I had trouble remembering this, sorry Simon ;-)
I don't recall any conversation with you WRT this patch series ('rip this apart'?)
Well, let patches in this series be picked up by various people.
, and see nothing in my archived U-Boot emails about it - is there another Tom (Rini? or Rix?) that you had this convo with?
About what?
Regardless, I'll apply this to u-boot-tegra/master & /next since the changes are trivial.
Ok, thanks
Note that any future Tegra changes will need to be rebased against master, as Allen's SPL rewrite/rework caused a lot of files to move around.
I don't expect more right now.
Tom
Best regards, Marek Vasut
Best regards, Marek Vasut
Marek,
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Tuesday, July 24, 2012 12:43 PM To: Tom Warren Cc: Simon Glass; u-boot@lists.denx.de; u-boot-dm@lists.denx.de; Wolfgang Denk; Albert Aribaud Subject: Re: [PATCH 08/10] dm: tegra: Staticize local functions in usb.c
Dear Tom Warren,
Marek,
-----Original Message----- From: Marek Vasut [mailto:marex@denx.de] Sent: Monday, July 23, 2012 11:24 PM To: Simon Glass Cc: u-boot@lists.denx.de; u-boot-dm@lists.denx.de; Tom Warren; Wolfgang Denk; Albert Aribaud Subject: Re: [PATCH 08/10] dm: tegra: Staticize local functions in usb.c
Dear Simon Glass,
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Acked-by: Simon Glass sjg@chromium.org
Simon, can you please pick up this one separatelly through your tree? I already agreed with Tom to rip this apart as it's not really a series, but rather a dump of random patches and cleanups. This is basically the first chapter of my crusade towards making you crazy from breakage ... I mean ... cleaning up drivers scattered across arch/ directory and moving them to drivers/ directory ...
Simon doesn't manage the Tegra repo, I do. Simon is the most prodigious Tegra submitter by far, but he's a Google employee, not an
Nvidian.
Hehe ... and I always kept torturing Simon about since I had trouble remembering this, sorry Simon ;-)
I don't recall any conversation with you WRT this patch series ('rip this apart'?)
Well, let patches in this series be picked up by various people.
, and see nothing in my archived U-Boot emails about it - is there another Tom (Rini? or Rix?) that you had this convo with?
About what?
Regardless, I'll apply this to u-boot-tegra/master & /next since the changes are trivial.
Ok, thanks
Note that any future Tegra changes will need to be rebased against master, as Allen's SPL rewrite/rework caused a lot of files to move around.
I don't expect more right now.
Tom
Best regards, Marek Vasut
Best regards, Marek Vasut
Applied to u-boot-tegra/master (and /next).
Tom
On Sat, Jul 21, 2012 at 4:02 PM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Simon Glass sjg@chromium.org Cc: Tom Warren twarren@nvidia.com Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
Ooops.
Acked-by: Simon Glass sjg@chromium.org
arch/arm/cpu/armv7/tegra2/usb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c index 5f2b243..ea7f701 100644 --- a/arch/arm/cpu/armv7/tegra2/usb.c +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -158,7 +158,8 @@ static void set_host_mode(struct fdt_usb *config) } }
-void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +static void usbf_reset_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr){ /* Reset the USB controller with 2us delay */ reset_periph(config->periph_id, 2); @@ -382,8 +383,8 @@ int tegrausb_stop_port(void) return 0; }
-int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
struct fdt_usb *config)+static int fdt_decode_usb(const void *blob, int node,
unsigned osc_frequency_mhz, struct fdt_usb *config){ const char *phy, *mode;
-- 1.7.10.4
Signed-off-by: Marek Vasut marex@denx.de Cc: Bryan Hundven bryanhundven@gmail.com Cc: Michael Schwingen rincewind@discworld.dascon.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Joe Hershberger joe.hershberger@ni.com --- Makefile | 2 +- {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAcc.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccCommon.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccControlInterface.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccDataPlane.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccMac.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccMii.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBAPI.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBAPISupport.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBCore.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBEvents.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBFeatures.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBFirewall.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBHashtable.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBLearning.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBMem.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBNPEAdaptor.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBPortUpdate.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBReports.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBSearch.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBSpanningTree.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBUtil.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBVlan.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBWiFi.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxEthMii.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxFeatureCtrl.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDl.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlImageMgr.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlNpeMgr.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlNpeMgrUtils.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMh.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhConfig.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhReceive.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhSend.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhSolicitedCbMgr.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhUnsolicitedCbMgr.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalBufferMgt.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalIoMem.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsCacheMMU.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsMsgQ.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsSemaphore.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsServices.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsThread.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrAqmIf.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrDispatcher.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrInit.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrQAccess.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrQCfg.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/Makefile | 2 +- {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAssert.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmSch.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmTypes.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmdAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmdAccCtrl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmm.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxDmaAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccDataPlane_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccMac_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccMii_p.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxEthAccQueueAssign_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAcc_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDB.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBLocks_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBLog_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBMessages_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBPortDefs.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBQoS.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDB_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthMii.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthMii_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthNpe.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxFeatureCtrl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxHssAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxI2cDrv.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeA.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlImageMgr_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlMacros_p.h | 0 .../cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgrEcRegisters_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgrUtils_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgr_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMh.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhConfig_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhMacros_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhReceive_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhSend_p.h | 0 .../cpu/ixp => drivers/net}/npe/include/IxNpeMhSolicitedCbMgr_p.h | 0 .../cpu/ixp => drivers/net}/npe/include/IxNpeMhUnsolicitedCbMgr_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMicrocode.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBufLib.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBuffMgt.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBuffPoolMgt.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsCacheMMU.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsPrintf.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServices.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesComponents.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesEndianess.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesMemAccess.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesMemMap.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsal.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalAssert.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackward.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardAssert.h | 0 .../cpu/ixp => drivers/net}/npe/include/IxOsalBackwardBufferMgt.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardCacheMMU.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardMemMap.h | 0 .../cpu/ixp => drivers/net}/npe/include/IxOsalBackwardOsServices.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardOssl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBufferMgt.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsalBufferMgtDefault.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalConfig.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalEndianess.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalIoMem.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalMemAccess.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOem.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOs.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsAssert.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsBufferMgt.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsIxp400.h | 0 .../net}/npe/include/IxOsalOsIxp400CustomizedMapping.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsTypes.h | 0 .../arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsUtilitySymbols.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalTypes.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalUtilitySymbols.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxParityENAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxPerfProfAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgr.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrAqmIf_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrDefines_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrDispatcher_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrLog_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrQAccess_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrQCfg_p.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQueueAssignments.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxSspAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTimeSyncAcc.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTimerCtrl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTypes.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxUART.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/IxVersionId.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_error.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_macros.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_os_type.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_ossl.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_symbols.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_types.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/npe.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/include/os_datatypes.h | 0 {arch/arm/cpu/ixp => drivers/net}/npe/miiphy.c | 0 {arch/arm/cpu/ixp => drivers/net}/npe/npe.c | 0 151 files changed, 2 insertions(+), 2 deletions(-) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAcc.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccCommon.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccControlInterface.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccDataPlane.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccMac.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthAccMii.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBAPI.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBAPISupport.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBCore.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBEvents.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBFeatures.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBFirewall.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBHashtable.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBLearning.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBMem.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBNPEAdaptor.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBPortUpdate.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBReports.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBSearch.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBSpanningTree.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBUtil.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBVlan.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthDBWiFi.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxEthMii.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxFeatureCtrl.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDl.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlImageMgr.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlNpeMgr.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeDlNpeMgrUtils.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMh.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhConfig.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhReceive.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhSend.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhSolicitedCbMgr.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxNpeMhUnsolicitedCbMgr.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalBufferMgt.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalIoMem.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsCacheMMU.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsMsgQ.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsSemaphore.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsServices.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxOsalOsThread.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrAqmIf.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrDispatcher.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrInit.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrQAccess.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/IxQMgrQCfg.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/Makefile (96%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAssert.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmSch.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmTypes.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmdAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmdAccCtrl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxAtmm.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxDmaAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccDataPlane_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccMac_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccMii_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAccQueueAssign_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthAcc_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDB.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBLocks_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBLog_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBMessages_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBPortDefs.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDBQoS.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthDB_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthMii.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthMii_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxEthNpe.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxFeatureCtrl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxHssAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxI2cDrv.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeA.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlImageMgr_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlMacros_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgrEcRegisters_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgrUtils_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeDlNpeMgr_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMh.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhConfig_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhMacros_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhReceive_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhSend_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhSolicitedCbMgr_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMhUnsolicitedCbMgr_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxNpeMicrocode.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBufLib.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBuffMgt.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsBuffPoolMgt.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsCacheMMU.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsPrintf.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServices.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesComponents.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesEndianess.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesMemAccess.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsServicesMemMap.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsal.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalAssert.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackward.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardAssert.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardBufferMgt.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardCacheMMU.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardMemMap.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardOsServices.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBackwardOssl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBufferMgt.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalBufferMgtDefault.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalConfig.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalEndianess.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalIoMem.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalMemAccess.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOem.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOs.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsAssert.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsBufferMgt.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsIxp400.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsIxp400CustomizedMapping.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsTypes.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalOsUtilitySymbols.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalTypes.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxOsalUtilitySymbols.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxParityENAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxPerfProfAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgr.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrAqmIf_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrDefines_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrDispatcher_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrLog_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrQAccess_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQMgrQCfg_p.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxQueueAssignments.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxSspAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTimeSyncAcc.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTimerCtrl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxTypes.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxUART.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/IxVersionId.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_error.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_macros.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_os_type.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_ossl.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_symbols.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/ix_types.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/npe.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/include/os_datatypes.h (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/miiphy.c (100%) rename {arch/arm/cpu/ixp => drivers/net}/npe/npe.c (100%)
diff --git a/Makefile b/Makefile index 6e8b5a7..622d74c 100644 --- a/Makefile +++ b/Makefile @@ -239,7 +239,7 @@ ifdef SOC LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).o endif ifeq ($(CPU),ixp) -LIBS += arch/arm/cpu/ixp/npe/libnpe.o +LIBS += drivers/net/npe/libnpe.o endif ifeq ($(CONFIG_OF_EMBED),y) LIBS += dts/libdts.o diff --git a/arch/arm/cpu/ixp/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAcc.c rename to drivers/net/npe/IxEthAcc.c diff --git a/arch/arm/cpu/ixp/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAccCommon.c rename to drivers/net/npe/IxEthAccCommon.c diff --git a/arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAccControlInterface.c rename to drivers/net/npe/IxEthAccControlInterface.c diff --git a/arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAccDataPlane.c rename to drivers/net/npe/IxEthAccDataPlane.c diff --git a/arch/arm/cpu/ixp/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAccMac.c rename to drivers/net/npe/IxEthAccMac.c diff --git a/arch/arm/cpu/ixp/npe/IxEthAccMii.c b/drivers/net/npe/IxEthAccMii.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthAccMii.c rename to drivers/net/npe/IxEthAccMii.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBAPI.c rename to drivers/net/npe/IxEthDBAPI.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c rename to drivers/net/npe/IxEthDBAPISupport.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBCore.c rename to drivers/net/npe/IxEthDBCore.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBEvents.c rename to drivers/net/npe/IxEthDBEvents.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBFeatures.c rename to drivers/net/npe/IxEthDBFeatures.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBFirewall.c rename to drivers/net/npe/IxEthDBFirewall.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBHashtable.c rename to drivers/net/npe/IxEthDBHashtable.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBLearning.c rename to drivers/net/npe/IxEthDBLearning.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBMem.c rename to drivers/net/npe/IxEthDBMem.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBNPEAdaptor.c rename to drivers/net/npe/IxEthDBNPEAdaptor.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBPortUpdate.c rename to drivers/net/npe/IxEthDBPortUpdate.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBReports.c rename to drivers/net/npe/IxEthDBReports.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBSearch.c rename to drivers/net/npe/IxEthDBSearch.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBSpanningTree.c rename to drivers/net/npe/IxEthDBSpanningTree.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBUtil.c rename to drivers/net/npe/IxEthDBUtil.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBVlan.c rename to drivers/net/npe/IxEthDBVlan.c diff --git a/arch/arm/cpu/ixp/npe/IxEthDBWiFi.c b/drivers/net/npe/IxEthDBWiFi.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthDBWiFi.c rename to drivers/net/npe/IxEthDBWiFi.c diff --git a/arch/arm/cpu/ixp/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxEthMii.c rename to drivers/net/npe/IxEthMii.c diff --git a/arch/arm/cpu/ixp/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxFeatureCtrl.c rename to drivers/net/npe/IxFeatureCtrl.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeDl.c rename to drivers/net/npe/IxNpeDl.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeDlImageMgr.c rename to drivers/net/npe/IxNpeDlImageMgr.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeDlNpeMgr.c rename to drivers/net/npe/IxNpeDlNpeMgr.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/drivers/net/npe/IxNpeDlNpeMgrUtils.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c rename to drivers/net/npe/IxNpeDlNpeMgrUtils.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMh.c rename to drivers/net/npe/IxNpeMh.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMhConfig.c rename to drivers/net/npe/IxNpeMhConfig.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhReceive.c b/drivers/net/npe/IxNpeMhReceive.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMhReceive.c rename to drivers/net/npe/IxNpeMhReceive.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMhSend.c rename to drivers/net/npe/IxNpeMhSend.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c b/drivers/net/npe/IxNpeMhSolicitedCbMgr.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMhSolicitedCbMgr.c rename to drivers/net/npe/IxNpeMhSolicitedCbMgr.c diff --git a/arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c b/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxNpeMhUnsolicitedCbMgr.c rename to drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c b/drivers/net/npe/IxOsalBufferMgt.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalBufferMgt.c rename to drivers/net/npe/IxOsalBufferMgt.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalIoMem.c b/drivers/net/npe/IxOsalIoMem.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalIoMem.c rename to drivers/net/npe/IxOsalIoMem.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c b/drivers/net/npe/IxOsalOsCacheMMU.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalOsCacheMMU.c rename to drivers/net/npe/IxOsalOsCacheMMU.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c b/drivers/net/npe/IxOsalOsMsgQ.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalOsMsgQ.c rename to drivers/net/npe/IxOsalOsMsgQ.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalOsSemaphore.c rename to drivers/net/npe/IxOsalOsSemaphore.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsServices.c b/drivers/net/npe/IxOsalOsServices.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalOsServices.c rename to drivers/net/npe/IxOsalOsServices.c diff --git a/arch/arm/cpu/ixp/npe/IxOsalOsThread.c b/drivers/net/npe/IxOsalOsThread.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxOsalOsThread.c rename to drivers/net/npe/IxOsalOsThread.c diff --git a/arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c b/drivers/net/npe/IxQMgrAqmIf.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxQMgrAqmIf.c rename to drivers/net/npe/IxQMgrAqmIf.c diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c rename to drivers/net/npe/IxQMgrDispatcher.c diff --git a/arch/arm/cpu/ixp/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxQMgrInit.c rename to drivers/net/npe/IxQMgrInit.c diff --git a/arch/arm/cpu/ixp/npe/IxQMgrQAccess.c b/drivers/net/npe/IxQMgrQAccess.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxQMgrQAccess.c rename to drivers/net/npe/IxQMgrQAccess.c diff --git a/arch/arm/cpu/ixp/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c similarity index 100% rename from arch/arm/cpu/ixp/npe/IxQMgrQCfg.c rename to drivers/net/npe/IxQMgrQCfg.c diff --git a/arch/arm/cpu/ixp/npe/Makefile b/drivers/net/npe/Makefile similarity index 96% rename from arch/arm/cpu/ixp/npe/Makefile rename to drivers/net/npe/Makefile index 14ab3c7..d13391b 100644 --- a/arch/arm/cpu/ixp/npe/Makefile +++ b/drivers/net/npe/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libnpe.o
-LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux +LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux CFLAGS += $(LOCAL_CFLAGS) CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend HOSTCFLAGS += $(LOCAL_CFLAGS) diff --git a/arch/arm/cpu/ixp/npe/include/IxAssert.h b/drivers/net/npe/include/IxAssert.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAssert.h rename to drivers/net/npe/include/IxAssert.h diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmSch.h b/drivers/net/npe/include/IxAtmSch.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAtmSch.h rename to drivers/net/npe/include/IxAtmSch.h diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmTypes.h b/drivers/net/npe/include/IxAtmTypes.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAtmTypes.h rename to drivers/net/npe/include/IxAtmTypes.h diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h b/drivers/net/npe/include/IxAtmdAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAtmdAcc.h rename to drivers/net/npe/include/IxAtmdAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAtmdAccCtrl.h rename to drivers/net/npe/include/IxAtmdAccCtrl.h diff --git a/arch/arm/cpu/ixp/npe/include/IxAtmm.h b/drivers/net/npe/include/IxAtmm.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxAtmm.h rename to drivers/net/npe/include/IxAtmm.h diff --git a/arch/arm/cpu/ixp/npe/include/IxDmaAcc.h b/drivers/net/npe/include/IxDmaAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxDmaAcc.h rename to drivers/net/npe/include/IxDmaAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc.h b/drivers/net/npe/include/IxEthAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAcc.h rename to drivers/net/npe/include/IxEthAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h b/drivers/net/npe/include/IxEthAccDataPlane_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAccDataPlane_p.h rename to drivers/net/npe/include/IxEthAccDataPlane_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h b/drivers/net/npe/include/IxEthAccMac_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAccMac_p.h rename to drivers/net/npe/include/IxEthAccMac_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h b/drivers/net/npe/include/IxEthAccMii_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAccMii_p.h rename to drivers/net/npe/include/IxEthAccMii_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h b/drivers/net/npe/include/IxEthAccQueueAssign_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAccQueueAssign_p.h rename to drivers/net/npe/include/IxEthAccQueueAssign_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h rename to drivers/net/npe/include/IxEthAcc_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDB.h rename to drivers/net/npe/include/IxEthDB.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h b/drivers/net/npe/include/IxEthDBLocks_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDBLocks_p.h rename to drivers/net/npe/include/IxEthDBLocks_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h b/drivers/net/npe/include/IxEthDBLog_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDBLog_p.h rename to drivers/net/npe/include/IxEthDBLog_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h b/drivers/net/npe/include/IxEthDBMessages_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDBMessages_p.h rename to drivers/net/npe/include/IxEthDBMessages_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h b/drivers/net/npe/include/IxEthDBPortDefs.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDBPortDefs.h rename to drivers/net/npe/include/IxEthDBPortDefs.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h b/drivers/net/npe/include/IxEthDBQoS.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDBQoS.h rename to drivers/net/npe/include/IxEthDBQoS.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthDB_p.h rename to drivers/net/npe/include/IxEthDB_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthMii.h rename to drivers/net/npe/include/IxEthMii.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthMii_p.h b/drivers/net/npe/include/IxEthMii_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthMii_p.h rename to drivers/net/npe/include/IxEthMii_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxEthNpe.h b/drivers/net/npe/include/IxEthNpe.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxEthNpe.h rename to drivers/net/npe/include/IxEthNpe.h diff --git a/arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxFeatureCtrl.h rename to drivers/net/npe/include/IxFeatureCtrl.h diff --git a/arch/arm/cpu/ixp/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxHssAcc.h rename to drivers/net/npe/include/IxHssAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h b/drivers/net/npe/include/IxI2cDrv.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxI2cDrv.h rename to drivers/net/npe/include/IxI2cDrv.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/drivers/net/npe/include/IxNpeA.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeA.h rename to drivers/net/npe/include/IxNpeA.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDl.h b/drivers/net/npe/include/IxNpeDl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDl.h rename to drivers/net/npe/include/IxNpeDl.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h b/drivers/net/npe/include/IxNpeDlImageMgr_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDlImageMgr_p.h rename to drivers/net/npe/include/IxNpeDlImageMgr_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h b/drivers/net/npe/include/IxNpeDlMacros_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDlMacros_p.h rename to drivers/net/npe/include/IxNpeDlMacros_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrEcRegisters_p.h rename to drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgrUtils_p.h rename to drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeDlNpeMgr_p.h rename to drivers/net/npe/include/IxNpeDlNpeMgr_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMh.h b/drivers/net/npe/include/IxNpeMh.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMh.h rename to drivers/net/npe/include/IxNpeMh.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h b/drivers/net/npe/include/IxNpeMhConfig_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhConfig_p.h rename to drivers/net/npe/include/IxNpeMhConfig_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h b/drivers/net/npe/include/IxNpeMhMacros_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhMacros_p.h rename to drivers/net/npe/include/IxNpeMhMacros_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h b/drivers/net/npe/include/IxNpeMhReceive_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhReceive_p.h rename to drivers/net/npe/include/IxNpeMhReceive_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h b/drivers/net/npe/include/IxNpeMhSend_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhSend_p.h rename to drivers/net/npe/include/IxNpeMhSend_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h b/drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhSolicitedCbMgr_p.h rename to drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h b/drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMhUnsolicitedCbMgr_p.h rename to drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h b/drivers/net/npe/include/IxNpeMicrocode.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxNpeMicrocode.h rename to drivers/net/npe/include/IxNpeMicrocode.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBufLib.h b/drivers/net/npe/include/IxOsBufLib.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsBufLib.h rename to drivers/net/npe/include/IxOsBufLib.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h b/drivers/net/npe/include/IxOsBuffMgt.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsBuffMgt.h rename to drivers/net/npe/include/IxOsBuffMgt.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h b/drivers/net/npe/include/IxOsBuffPoolMgt.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsBuffPoolMgt.h rename to drivers/net/npe/include/IxOsBuffPoolMgt.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h b/drivers/net/npe/include/IxOsCacheMMU.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsCacheMMU.h rename to drivers/net/npe/include/IxOsCacheMMU.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsPrintf.h b/drivers/net/npe/include/IxOsPrintf.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsPrintf.h rename to drivers/net/npe/include/IxOsPrintf.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServices.h b/drivers/net/npe/include/IxOsServices.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsServices.h rename to drivers/net/npe/include/IxOsServices.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h b/drivers/net/npe/include/IxOsServicesComponents.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsServicesComponents.h rename to drivers/net/npe/include/IxOsServicesComponents.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h b/drivers/net/npe/include/IxOsServicesEndianess.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsServicesEndianess.h rename to drivers/net/npe/include/IxOsServicesEndianess.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h b/drivers/net/npe/include/IxOsServicesMemAccess.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsServicesMemAccess.h rename to drivers/net/npe/include/IxOsServicesMemAccess.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h b/drivers/net/npe/include/IxOsServicesMemMap.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsServicesMemMap.h rename to drivers/net/npe/include/IxOsServicesMemMap.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsal.h b/drivers/net/npe/include/IxOsal.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsal.h rename to drivers/net/npe/include/IxOsal.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalAssert.h b/drivers/net/npe/include/IxOsalAssert.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalAssert.h rename to drivers/net/npe/include/IxOsalAssert.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackward.h b/drivers/net/npe/include/IxOsalBackward.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackward.h rename to drivers/net/npe/include/IxOsalBackward.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h b/drivers/net/npe/include/IxOsalBackwardAssert.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardAssert.h rename to drivers/net/npe/include/IxOsalBackwardAssert.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/drivers/net/npe/include/IxOsalBackwardBufferMgt.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h rename to drivers/net/npe/include/IxOsalBackwardBufferMgt.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h b/drivers/net/npe/include/IxOsalBackwardCacheMMU.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardCacheMMU.h rename to drivers/net/npe/include/IxOsalBackwardCacheMMU.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/drivers/net/npe/include/IxOsalBackwardMemMap.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardMemMap.h rename to drivers/net/npe/include/IxOsalBackwardMemMap.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h b/drivers/net/npe/include/IxOsalBackwardOsServices.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardOsServices.h rename to drivers/net/npe/include/IxOsalBackwardOsServices.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h b/drivers/net/npe/include/IxOsalBackwardOssl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBackwardOssl.h rename to drivers/net/npe/include/IxOsalBackwardOssl.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h b/drivers/net/npe/include/IxOsalBufferMgt.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBufferMgt.h rename to drivers/net/npe/include/IxOsalBufferMgt.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h b/drivers/net/npe/include/IxOsalBufferMgtDefault.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalBufferMgtDefault.h rename to drivers/net/npe/include/IxOsalBufferMgtDefault.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalConfig.h b/drivers/net/npe/include/IxOsalConfig.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalConfig.h rename to drivers/net/npe/include/IxOsalConfig.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h b/drivers/net/npe/include/IxOsalEndianess.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalEndianess.h rename to drivers/net/npe/include/IxOsalEndianess.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h b/drivers/net/npe/include/IxOsalIoMem.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalIoMem.h rename to drivers/net/npe/include/IxOsalIoMem.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h b/drivers/net/npe/include/IxOsalMemAccess.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalMemAccess.h rename to drivers/net/npe/include/IxOsalMemAccess.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOem.h b/drivers/net/npe/include/IxOsalOem.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOem.h rename to drivers/net/npe/include/IxOsalOem.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOs.h b/drivers/net/npe/include/IxOsalOs.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOs.h rename to drivers/net/npe/include/IxOsalOs.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h b/drivers/net/npe/include/IxOsalOsAssert.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsAssert.h rename to drivers/net/npe/include/IxOsalOsAssert.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h b/drivers/net/npe/include/IxOsalOsBufferMgt.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsBufferMgt.h rename to drivers/net/npe/include/IxOsalOsBufferMgt.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h b/drivers/net/npe/include/IxOsalOsIxp400.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400.h rename to drivers/net/npe/include/IxOsalOsIxp400.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h b/drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsIxp400CustomizedMapping.h rename to drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h b/drivers/net/npe/include/IxOsalOsTypes.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsTypes.h rename to drivers/net/npe/include/IxOsalOsTypes.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h b/drivers/net/npe/include/IxOsalOsUtilitySymbols.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalOsUtilitySymbols.h rename to drivers/net/npe/include/IxOsalOsUtilitySymbols.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalTypes.h b/drivers/net/npe/include/IxOsalTypes.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalTypes.h rename to drivers/net/npe/include/IxOsalTypes.h diff --git a/arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h b/drivers/net/npe/include/IxOsalUtilitySymbols.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxOsalUtilitySymbols.h rename to drivers/net/npe/include/IxOsalUtilitySymbols.h diff --git a/arch/arm/cpu/ixp/npe/include/IxParityENAcc.h b/drivers/net/npe/include/IxParityENAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxParityENAcc.h rename to drivers/net/npe/include/IxParityENAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h b/drivers/net/npe/include/IxPerfProfAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxPerfProfAcc.h rename to drivers/net/npe/include/IxPerfProfAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/drivers/net/npe/include/IxQMgr.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgr.h rename to drivers/net/npe/include/IxQMgr.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/drivers/net/npe/include/IxQMgrAqmIf_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrAqmIf_p.h rename to drivers/net/npe/include/IxQMgrAqmIf_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h b/drivers/net/npe/include/IxQMgrDefines_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrDefines_p.h rename to drivers/net/npe/include/IxQMgrDefines_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h b/drivers/net/npe/include/IxQMgrDispatcher_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h rename to drivers/net/npe/include/IxQMgrDispatcher_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h b/drivers/net/npe/include/IxQMgrLog_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrLog_p.h rename to drivers/net/npe/include/IxQMgrLog_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h b/drivers/net/npe/include/IxQMgrQAccess_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrQAccess_p.h rename to drivers/net/npe/include/IxQMgrQAccess_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h b/drivers/net/npe/include/IxQMgrQCfg_p.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQMgrQCfg_p.h rename to drivers/net/npe/include/IxQMgrQCfg_p.h diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/drivers/net/npe/include/IxQueueAssignments.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h rename to drivers/net/npe/include/IxQueueAssignments.h diff --git a/arch/arm/cpu/ixp/npe/include/IxSspAcc.h b/drivers/net/npe/include/IxSspAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxSspAcc.h rename to drivers/net/npe/include/IxSspAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h b/drivers/net/npe/include/IxTimeSyncAcc.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxTimeSyncAcc.h rename to drivers/net/npe/include/IxTimeSyncAcc.h diff --git a/arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h b/drivers/net/npe/include/IxTimerCtrl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxTimerCtrl.h rename to drivers/net/npe/include/IxTimerCtrl.h diff --git a/arch/arm/cpu/ixp/npe/include/IxTypes.h b/drivers/net/npe/include/IxTypes.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxTypes.h rename to drivers/net/npe/include/IxTypes.h diff --git a/arch/arm/cpu/ixp/npe/include/IxUART.h b/drivers/net/npe/include/IxUART.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxUART.h rename to drivers/net/npe/include/IxUART.h diff --git a/arch/arm/cpu/ixp/npe/include/IxVersionId.h b/drivers/net/npe/include/IxVersionId.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/IxVersionId.h rename to drivers/net/npe/include/IxVersionId.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_error.h b/drivers/net/npe/include/ix_error.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_error.h rename to drivers/net/npe/include/ix_error.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_macros.h b/drivers/net/npe/include/ix_macros.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_macros.h rename to drivers/net/npe/include/ix_macros.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_os_type.h b/drivers/net/npe/include/ix_os_type.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_os_type.h rename to drivers/net/npe/include/ix_os_type.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_ossl.h b/drivers/net/npe/include/ix_ossl.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_ossl.h rename to drivers/net/npe/include/ix_ossl.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_symbols.h b/drivers/net/npe/include/ix_symbols.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_symbols.h rename to drivers/net/npe/include/ix_symbols.h diff --git a/arch/arm/cpu/ixp/npe/include/ix_types.h b/drivers/net/npe/include/ix_types.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/ix_types.h rename to drivers/net/npe/include/ix_types.h diff --git a/arch/arm/cpu/ixp/npe/include/npe.h b/drivers/net/npe/include/npe.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/npe.h rename to drivers/net/npe/include/npe.h diff --git a/arch/arm/cpu/ixp/npe/include/os_datatypes.h b/drivers/net/npe/include/os_datatypes.h similarity index 100% rename from arch/arm/cpu/ixp/npe/include/os_datatypes.h rename to drivers/net/npe/include/os_datatypes.h diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/drivers/net/npe/miiphy.c similarity index 100% rename from arch/arm/cpu/ixp/npe/miiphy.c rename to drivers/net/npe/miiphy.c diff --git a/arch/arm/cpu/ixp/npe/npe.c b/drivers/net/npe/npe.c similarity index 100% rename from arch/arm/cpu/ixp/npe/npe.c rename to drivers/net/npe/npe.c
Hi Marek,
On Sat, Jul 21, 2012 at 10:02 AM, Marek Vasut marex@denx.de wrote:
Signed-off-by: Marek Vasut marex@denx.de Cc: Bryan Hundven bryanhundven@gmail.com Cc: Michael Schwingen rincewind@discworld.dascon.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Joe Hershberger joe.hershberger@ni.com
Applied, thanks.
-Joe
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com --- include/configs/devkit8000.h | 1 + include/configs/omap3_beagle.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap4_common.h | 1 + include/configs/tam3517-common.h | 1 + 5 files changed, 5 insertions(+)
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e529099..1f44a42 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -315,6 +315,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_MMC_SUPPORT diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 382b791..cdcfbe0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -421,6 +421,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_OMAP3_ID_NAND #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index f6afb7a..92bd8fc 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -326,6 +326,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index bc73f21..6f298a1 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -279,6 +279,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_THUMB_BUILD diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 94006e7..24f6f7e 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -252,6 +252,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
On Sat, Jul 21, 2012 at 05:02:27PM +0200, Marek Vasut wrote:
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
The change is fine so
Acked-by: Tom Rini trini@ti.com
But please re-order in the series so that there is no breakage. I do hate bisect failing run-time when we know we could have not :)
Dear Tom Rini,
On Sat, Jul 21, 2012 at 05:02:27PM +0200, Marek Vasut wrote:
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
The change is fine so
Acked-by: Tom Rini trini@ti.com
But please re-order in the series so that there is no breakage. I do hate bisect failing run-time when we know we could have not :)
Sure, if you can pick 10/10 first, 06/10 afterwards as we discussed on IRC, that'd be great. This is not really a series and I should have posted it as such, I admit.
Best regards, Marek Vasut
On Tue, Jul 24, 2012 at 12:03:22AM +0200, Marek Vasut wrote:
Dear Tom Rini,
On Sat, Jul 21, 2012 at 05:02:27PM +0200, Marek Vasut wrote:
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
The change is fine so
Acked-by: Tom Rini trini@ti.com
But please re-order in the series so that there is no breakage. I do hate bisect failing run-time when we know we could have not :)
Sure, if you can pick 10/10 first, 06/10 afterwards as we discussed on IRC, that'd be great. This is not really a series and I should have posted it as such, I admit.
As we discussed, I've taken 10/10 and 06/10 (in that order to prevent build breakage) and applied to u-boot-ti/master. I also updated them trivially to deal with am335x also using the GPIO driver now.
Dear Tom Rini,
On Tue, Jul 24, 2012 at 12:03:22AM +0200, Marek Vasut wrote:
Dear Tom Rini,
On Sat, Jul 21, 2012 at 05:02:27PM +0200, Marek Vasut wrote:
This fixes the breakage with SPL on most OMAP boards after the GPIO driver was moved.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de Cc: Tom Rini trini@ti.com
The change is fine so
Acked-by: Tom Rini trini@ti.com
But please re-order in the series so that there is no breakage. I do hate bisect failing run-time when we know we could have not :)
Sure, if you can pick 10/10 first, 06/10 afterwards as we discussed on IRC, that'd be great. This is not really a series and I should have posted it as such, I admit.
As we discussed, I've taken 10/10 and 06/10 (in that order to prevent build breakage) and applied to u-boot-ti/master. I also updated them trivially to deal with am335x also using the GPIO driver now.
Thanks Tom. btw we should cut the cross-list posting short ...
Best regards, Marek Vasut
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
Marek: please stop adding random ID's to the Subject:. Thanks.
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
Marek: please stop adding random ID's to the Subject:. Thanks.
Best regards,
Wolfgang Denk
Best regards, Marek Vasut
Dear Marek Vasut,
In message 201209021815.02418.marex@denx.de you wrote:
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
But not in the subject. If you want to be friendly to Albert and save him the efforts of cleaning this up, then resubmit after adding some tag to the commit message yourself.
Marek: please stop adding random ID's to the Subject:. Thanks.
Thanks.
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
Dear Marek Vasut,
In message 201209021815.02418.marex@denx.de you wrote:
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
But not in the subject. If you want to be friendly to Albert and save him the efforts of cleaning this up, then resubmit after adding some tag to the commit message yourself.
Yea, I'll rebase on current ToT and resubmit
Marek: please stop adding random ID's to the Subject:. Thanks.
Thanks.
Best regards,
Wolfgang Denk
Best regards, Marek Vasut
On Sun, Sep 02, 2012 at 06:15:02PM +0200, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
You shouldn't need any. At the end of the project just do: $ git log --author=(regex|that|catches|everyone) --since=project-start
Dear Tom Rini,
On Sun, Sep 02, 2012 at 06:15:02PM +0200, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut
wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
You shouldn't need any. At the end of the project just do: $ git log --author=(regex|that|catches|everyone) --since=project-start
What about me generating gazilion of other patches?
Best regards, Marek Vasut
On 09/05/2012 07:44 PM, Marek Vasut wrote:
Dear Tom Rini,
On Sun, Sep 02, 2012 at 06:15:02PM +0200, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut
wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
You shouldn't need any. At the end of the project just do: $ git log --author=(regex|that|catches|everyone) --since=project-start
What about me generating gazilion of other patches?
Use your denx.de for work and your gmail or university email for the project?
Dear Tom Rini,
On 09/05/2012 07:44 PM, Marek Vasut wrote:
Dear Tom Rini,
On Sun, Sep 02, 2012 at 06:15:02PM +0200, Marek Vasut wrote:
Dear Wolfgang Denk,
Dear Albert,
In message 1342882947-9174-1-git-send-email-marex@denx.de Marek Vasut
wrote:
This stuff has been rotting in the tree for a year now. Remove it.
Signed-off-by: Marek Vasut marex@denx.de Cc: Wolfgang Denk wd@denx.de Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: U-Boot DM u-boot-dm@lists.denx.de
In case you are going to apply any of these patches, please do make sure to drop the "dm: " string from all these subjects.
At least add some ID so I can mine these patches back when we finish the project. If you drop them, I won't have any way to tell.
You shouldn't need any. At the end of the project just do: $ git log --author=(regex|that|catches|everyone) --since=project-start
What about me generating gazilion of other patches?
Use your denx.de for work and your gmail or university email for the project?
I don't have university email ... but I'll figure it out somehow.
Best regards, Marek Vasut
participants (10)
-
Albert ARIBAUD -
Joe Hershberger -
Marek Vasut -
Minkyu Kang -
Simon Glass -
Simon Glass -
Tom Rini -
Tom Rini -
Tom Warren -
Wolfgang Denk