[U-Boot] [PATCH v3 00/13] net: Add Allwinner EMAC CLK, RESET support
This is v2 version for Allwinner EMAC CLK, RESET support, which was initially be a part of previous series[1].
Changes for v3: - rebase on master - collecet review tags from Simon - fixed the comment by Simon, keep clk_get_by_indexed_prop() and call clk_get_by_index_tail Changes for v2: - rebase on master - add dm tests for new clk and reset functions.
Any inputs? Jagan.
[1] https://patchwork.ozlabs.org/cover/1039666/
Jagan Teki (13): clk: sunxi: Implement A10 EMAC clocks net: sunxi_emac: Add CLK support net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle clk: Get the CLK by index without device clk: Use clk_get_by_index_tail() test/dm: clk: Add clk_get_by_index[_nodev] test reset: Get the RESET by index without device test/dm: reset: Add reset_get_by_index[_nodev] test clk: sunxi: Implement EMAC, GMAC clocks, resets net: sun8i_emac: Add CLK and RESET support clk: sunxi: h3: Implement EPHY CLK and RESET net: sun8i_emac: Add EPHY CLK and RESET support board: sunxi: gmac: Remove Ethernet clock and reset
board/sunxi/gmac.c | 8 -- drivers/clk/clk-uclass.c | 75 ++++++++++---- drivers/clk/sunxi/clk_a10.c | 1 + drivers/clk/sunxi/clk_a10s.c | 1 + drivers/clk/sunxi/clk_a31.c | 2 + drivers/clk/sunxi/clk_a64.c | 2 + drivers/clk/sunxi/clk_a83t.c | 2 + drivers/clk/sunxi/clk_h3.c | 6 ++ drivers/clk/sunxi/clk_h6.c | 4 + drivers/clk/sunxi/clk_r40.c | 3 + drivers/net/sun8i_emac.c | 184 ++++++++++++++++++++++++----------- drivers/net/sunxi_emac.c | 28 ++++-- drivers/reset/reset-uclass.c | 53 ++++++---- include/clk.h | 15 +++ include/reset.h | 16 +++ test/dm/clk.c | 21 ++++ test/dm/reset.c | 23 +++++ 17 files changed, 336 insertions(+), 108 deletions(-)
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 1 + drivers/clk/sunxi/clk_a10s.c | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index b8b57e2b31..15ffe5ecb3 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -22,6 +22,7 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), + [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index c6fcede822..33d41d47b0 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -19,6 +19,7 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sunxi_emac.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 8dbd3c50c1..9a5f7fd3c7 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> #include <linux/err.h> #include <malloc.h> @@ -157,6 +158,7 @@ struct sunxi_sramc_regs {
struct emac_eth_dev { struct emac_regs *regs; + struct clk clk; struct mii_dev *bus; struct phy_device *phydev; int link_printed; @@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, return 0; }
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv) +static int sunxi_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct sunxi_sramc_regs *sram = (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; struct emac_regs *regs = priv->regs; - int pin; + int pin, ret;
/* Map SRAM to EMAC */ setbits_le32(&sram->ctrl1, 0x5 << 2); @@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv) sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
/* Set up clock gating */ - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + ret = clk_enable(&priv->clk); + if (ret) { + dev_err(dev, "failed to enable emac clock\n"); + return ret; + }
/* Set MII clock */ clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); + + return 0; }
static int sunxi_emac_eth_start(struct udevice *dev) @@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct emac_eth_dev *priv = dev_get_priv(dev); + int ret;
priv->regs = (struct emac_regs *)pdata->iobase; - sunxi_emac_board_setup(priv); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) { + dev_err(dev, "failed to get emac clock\n"); + return ret; + } + + ret = sunxi_emac_board_setup(priv); + if (ret) + return ret;
return sunxi_emac_init_phy(priv, dev); }
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
- reg = readl(priv->sysctl_reg + 0x30); + if (priv->variant == R40_GMAC) { + /* Select RGMII for R40 */ + reg = readl(priv->sysctl_reg + 0x164); + reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII | + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
- if (priv->variant == R40_GMAC) + writel(reg, priv->sysctl_reg + 0x164); return 0; + } + + reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, ®); @@ -662,13 +670,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* De-assert EMAC */ setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); - - /* Select RGMII for R40 */ - setbits_le32(&ccm->gmac_clk_cfg, - CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | - CCM_GMAC_CTRL_GPIT_RGMII); - setbits_le32(&ccm->gmac_clk_cfg, - CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); } else { /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); @@ -850,25 +851,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }
- if (priv->variant != R40_GMAC) { - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); - if (offset < 0) { - debug("%s: cannot find syscon node\n", __func__); - return -EINVAL; - } - reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); - if (!reg) { - debug("%s: cannot find reg property in syscon node\n", - __func__); - return -EINVAL; - } - priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, - offset, reg); - if (priv->sysctl_reg == FDT_ADDR_T_NONE) { - debug("%s: Cannot find syscon base address\n", - __func__); - return -EINVAL; - } + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; }
pdata->phy_interface = -1;
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == R40_GMAC) {/* Select RGMII for R40 */reg = readl(priv->sysctl_reg + 0x164);
Please don't add more magic numbers. #define with register name.
reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |CCM_GMAC_CTRL_GPIT_RGMII |CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
if (priv->variant == R40_GMAC)
writel(reg, priv->sysctl_reg + 0x164);
Same.
return 0;
}reg = readl(priv->sysctl_reg + 0x30); if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, ®);@@ -662,13 +670,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* De-assert EMAC */ setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
/* Select RGMII for R40 */setbits_le32(&ccm->gmac_clk_cfg,CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |CCM_GMAC_CTRL_GPIT_RGMII);setbits_le32(&ccm->gmac_clk_cfg,CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); } else { /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));@@ -850,25 +851,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }
if (priv->variant != R40_GMAC) {offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");if (offset < 0) {debug("%s: cannot find syscon node\n", __func__);return -EINVAL;}reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);if (!reg) {debug("%s: cannot find reg property in syscon node\n",__func__);return -EINVAL;}priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,offset, reg);if (priv->sysctl_reg == FDT_ADDR_T_NONE) {debug("%s: Cannot find syscon base address\n",__func__);return -EINVAL;}
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");if (offset < 0) {debug("%s: cannot find syscon node\n", __func__);return -EINVAL;}reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);if (!reg) {debug("%s: cannot find reg property in syscon node\n",__func__);return -EINVAL;}priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,offset, reg);if (priv->sysctl_reg == FDT_ADDR_T_NONE) {debug("%s: Cannot find syscon base address\n", __func__);return -EINVAL; } pdata->phy_interface = -1;-- 2.18.0.321.gffc6fa0e3
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == R40_GMAC) {/* Select RGMII for R40 */reg = readl(priv->sysctl_reg + 0x164);Please don't add more magic numbers. #define with register name.
I do prefer the same, but kept it as same as original. and there are other place do have similar reg magic numbers. Will clean it up all in separate patch. would that be okay?
On Tue, Mar 5, 2019 at 10:17 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == R40_GMAC) {/* Select RGMII for R40 */reg = readl(priv->sysctl_reg + 0x164);Please don't add more magic numbers. #define with register name.
I do prefer the same, but kept it as same as original. and there are other place do have similar reg magic numbers. Will clean it up all in separate patch. would that be okay?
OK. This cam in after the merge window closed, right? If so, please move the cleanup patch before this one in the next version.
Thanks. -Joe
On Tue, Mar 5, 2019 at 10:55 PM Joe Hershberger joe.hershberger@ni.com wrote:
On Tue, Mar 5, 2019 at 10:17 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == R40_GMAC) {/* Select RGMII for R40 */reg = readl(priv->sysctl_reg + 0x164);Please don't add more magic numbers. #define with register name.
I do prefer the same, but kept it as same as original. and there are other place do have similar reg magic numbers. Will clean it up all in separate patch. would that be okay?
OK. This cam in after the merge window closed, right? If so, please move the cleanup patch before this one in the next version.
It's been in ML many releases, but I will send PR in next MW. mean while I'll push it on my sunxi/next and will send separate patch about the cleanup. will that be fine?
On Thu, Mar 7, 2019 at 10:22 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Tue, Mar 5, 2019 at 10:55 PM Joe Hershberger joe.hershberger@ni.com wrote:
On Tue, Mar 5, 2019 at 10:17 AM Jagan Teki jagan@amarulasolutions.com wrote:
On Sat, Mar 2, 2019 at 12:29 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Wed, Feb 27, 2019 at 12:59 PM Jagan Teki jagan@amarulasolutions.com wrote:
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index c9798445c7..a7fb7ac405 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, int ret; u32 reg;
reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == R40_GMAC) {/* Select RGMII for R40 */reg = readl(priv->sysctl_reg + 0x164);Please don't add more magic numbers. #define with register name.
I do prefer the same, but kept it as same as original. and there are other place do have similar reg magic numbers. Will clean it up all in separate patch. would that be okay?
OK. This cam in after the merge window closed, right? If so, please move the cleanup patch before this one in the next version.
It's been in ML many releases, but I will send PR in next MW. mean while I'll push it on my sunxi/next and will send separate patch about the cleanup. will that be fine?
Sure, that's fine.
Thanks! -Joe
Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index()
Cc: Stephen Warren swarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Simon Glass sjg@chromium.org --- drivers/clk/clk-uclass.c | 61 +++++++++++++++++++++++++++++++++++++++- include/clk.h | 15 ++++++++++ 2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 844b87cc33..d9236c5b51 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -54,6 +54,46 @@ static int clk_of_xlate_default(struct clk *clk, return 0; }
+static int clk_get_by_index_tail(int ret, ofnode node, + struct ofnode_phandle_args *args, + const char *list_name, int index, + struct clk *clk) +{ + struct udevice *dev_clk; + const struct clk_ops *ops; + + assert(clk); + clk->dev = NULL; + if (ret) + goto err; + + ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + clk->dev = dev_clk; + + ops = clk_dev_ops(dev_clk); + + if (ops->of_xlate) + ret = ops->of_xlate(clk, args); + else + ret = clk_of_xlate_default(clk, args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + return clk_request(dev_clk, clk); +err: + debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n", + __func__, ofnode_get_name(node), list_name, index, ret); + return ret; +} + static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, int index, struct clk *clk) { @@ -100,7 +140,26 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) { - return clk_get_by_indexed_prop(dev, "clocks", index, clk); + struct ofnode_phandle_args args; + int ret; + + ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, + index, &args); + + return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", + index > 0, clk); +} + +int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) +{ + struct ofnode_phandle_args args; + int ret; + + ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0, + index > 0, &args); + + return clk_get_by_index_tail(ret, node, &args, "clocks", + index > 0, clk); }
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) diff --git a/include/clk.h b/include/clk.h index 8e366163f9..d24e99713a 100644 --- a/include/clk.h +++ b/include/clk.h @@ -8,6 +8,7 @@ #ifndef _CLK_H_ #define _CLK_H_
+#include <dm/ofnode.h> #include <linux/errno.h> #include <linux/types.h>
@@ -100,6 +101,20 @@ int clk_get_by_index_platdata(struct udevice *dev, int index, */ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+/** + * clock_get_by_index_nodev - Get/request a clock by integer index + * without a device. + * + * This is a version of clk_get_by_index() that does not use a device. + * + * @node: The client ofnode. + * @index: The index of the clock to request, within the client's list of + * clocks. + * @clock A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk); + /** * clock_get_bulk - Get/request all clocks of a device. *
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop().
Cc: Stephen Warren swarren@nvidia.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v3: - use clk_get_by_index_tail() from clk_get_by_indexed_prop()
drivers/clk/clk-uclass.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index d9236c5b51..79b3b0494c 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -99,8 +99,6 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, { int ret; struct ofnode_phandle_args args; - struct udevice *dev_clk; - const struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
@@ -115,27 +113,9 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, return ret; }
- ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk); - if (ret) { - debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", - __func__, ret); - return ret; - } - - clk->dev = dev_clk; - - ops = clk_dev_ops(dev_clk);
- if (ops->of_xlate) - ret = ops->of_xlate(clk, &args); - else - ret = clk_of_xlate_default(clk, &args); - if (ret) { - debug("of_xlate() failed: %d\n", ret); - return ret; - } - - return clk_request(dev_clk, clk); + return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", + index > 0, clk); }
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
On Wed, 27 Feb 2019 at 11:57, Jagan Teki jagan@amarulasolutions.com wrote:
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop().
Cc: Stephen Warren swarren@nvidia.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Changes for v3:
- use clk_get_by_index_tail() from clk_get_by_indexed_prop()
drivers/clk/clk-uclass.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Add sample dm clk test for clk_get_by_index and clk_get_by_index_nodev functionality code.
Cc: Stephen Warren swarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Simon Glass sjg@chromium.org --- test/dm/clk.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/test/dm/clk.c b/test/dm/clk.c index 898c034e27..29ef6ef41b 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -4,12 +4,33 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> #include <asm/clk.h> #include <dm/test.h> #include <linux/err.h> #include <test/ut.h>
+/* Base test of the clk uclass */ +static int dm_test_clk_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct clk clk_method1; + struct clk clk_method2; + + /* Get the device using the clk device */ + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev)); + + /* Get the same clk port in 2 different ways and compare */ + ut_assertok(clk_get_by_index(dev, 1, &clk_method1)); + ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2)); + ut_asserteq(clk_method1.id, clk_method2.id); + + return 0; +} + +DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT); + static int dm_test_clk(struct unit_test_state *uts) { struct udevice *dev_fixed, *dev_clk, *dev_test;
Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode.
So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index()
Cc: Stephen Warren swarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Simon Glass sjg@chromium.org --- drivers/reset/reset-uclass.c | 53 ++++++++++++++++++++++++------------ include/reset.h | 16 +++++++++++ 2 files changed, 52 insertions(+), 17 deletions(-)
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 89e39c6b5a..ee1a423ffb 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -29,41 +29,34 @@ static int reset_of_xlate_default(struct reset_ctl *reset_ctl, return 0; }
-int reset_get_by_index(struct udevice *dev, int index, - struct reset_ctl *reset_ctl) +static int reset_get_by_index_tail(int ret, ofnode node, + struct ofnode_phandle_args *args, + const char *list_name, int index, + struct reset_ctl *reset_ctl) { - struct ofnode_phandle_args args; - int ret; struct udevice *dev_reset; struct reset_ops *ops;
- debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index, - reset_ctl); + assert(reset_ctl); reset_ctl->dev = NULL; - - ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, - index, &args); - if (ret) { - debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n", - __func__, ret); + if (ret) return ret; - }
- ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node, + ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node, &dev_reset); if (ret) { debug("%s: uclass_get_device_by_ofnode() failed: %d\n", __func__, ret); - debug("%s %d\n", ofnode_get_name(args.node), args.args[0]); + debug("%s %d\n", ofnode_get_name(args->node), args->args[0]); return ret; } ops = reset_dev_ops(dev_reset);
reset_ctl->dev = dev_reset; if (ops->of_xlate) - ret = ops->of_xlate(reset_ctl, &args); + ret = ops->of_xlate(reset_ctl, args); else - ret = reset_of_xlate_default(reset_ctl, &args); + ret = reset_of_xlate_default(reset_ctl, args); if (ret) { debug("of_xlate() failed: %d\n", ret); return ret; @@ -78,6 +71,32 @@ int reset_get_by_index(struct udevice *dev, int index, return 0; }
+int reset_get_by_index(struct udevice *dev, int index, + struct reset_ctl *reset_ctl) +{ + struct ofnode_phandle_args args; + int ret; + + ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, + index, &args); + + return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets", + index > 0, reset_ctl); +} + +int reset_get_by_index_nodev(ofnode node, int index, + struct reset_ctl *reset_ctl) +{ + struct ofnode_phandle_args args; + int ret; + + ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0, + index > 0, &args); + + return reset_get_by_index_tail(ret, node, &args, "resets", + index > 0, reset_ctl); +} + int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) { int i, ret, err, count; diff --git a/include/reset.h b/include/reset.h index 65aa7a4ce5..57bbc0b49d 100644 --- a/include/reset.h +++ b/include/reset.h @@ -6,6 +6,7 @@ #ifndef _RESET_H #define _RESET_H
+#include <dm/ofnode.h> #include <linux/errno.h>
/** @@ -99,6 +100,21 @@ struct reset_ctl_bulk { int reset_get_by_index(struct udevice *dev, int index, struct reset_ctl *reset_ctl);
+/** + * reset_get_by_index_nodev - Get/request a reset signal by integer index + * without a device. + * + * This is a version of reset_get_by_index() that does not use a device. + * + * @node: The client ofnode. + * @index: The index of the reset signal to request, within the client's + * list of reset signals. + * @reset_ctl A pointer to a reset control struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int reset_get_by_index_nodev(ofnode node, int index, + struct reset_ctl *reset_ctl); + /** * reset_get_bulk - Get/request all reset signals of a device. *
Add sample dm reset test for reset_get_by_index and reset_get_by_index_nodev functionality code.
Cc: Stephen Warren swarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Simon Glass sjg@chromium.org --- test/dm/reset.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/test/dm/reset.c b/test/dm/reset.c index c02866a2f0..c61daed490 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -5,6 +5,7 @@
#include <common.h> #include <dm.h> +#include <reset.h> #include <dm/test.h> #include <asm/reset.h> #include <test/ut.h> @@ -15,6 +16,28 @@ /* This is the other reset phandle specifier handled by bulk */ #define OTHER_RESET_ID 2
+/* Base test of the reset uclass */ +static int dm_test_reset_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct reset_ctl reset_method1; + struct reset_ctl reset_method2; + + /* Get the device using the reset device */ + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev)); + + /* Get the same reset port in 2 different ways and compare */ + ut_assertok(reset_get_by_index(dev, 1, &reset_method1)); + ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1, + &reset_method2)); + ut_asserteq(reset_method1.id, reset_method2.id); + + return 0; +} + +DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_FDT); + static int dm_test_reset(struct unit_test_state *uts) { struct udevice *dev_reset;
- Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a31.c | 2 ++ drivers/clk/sunxi/clk_a64.c | 2 ++ drivers/clk/sunxi/clk_a83t.c | 2 ++ drivers/clk/sunxi/clk_h3.c | 2 ++ drivers/clk/sunxi/clk_h6.c | 4 ++++ drivers/clk/sunxi/clk_r40.c | 3 +++ 6 files changed, 15 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index fa6e3eeef0..4ec3c2ae89 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -17,6 +17,7 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), + [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)), @@ -57,6 +58,7 @@ static struct ccu_reset a31_resets[] = { [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), + [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)), [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)), [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)), [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 322d6cd557..f94e8aa754 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -16,6 +16,7 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), @@ -49,6 +50,7 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 36f7e14c45..2be87a31fd 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -16,6 +16,7 @@ static struct ccu_clk_gate a83t_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), @@ -47,6 +48,7 @@ static struct ccu_reset a83t_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 5f99ef7342..f5ae1e9555 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -16,6 +16,7 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), @@ -55,6 +56,7 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 71f0c78656..0bb00f449a 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -26,6 +26,8 @@ static struct ccu_clk_gate h6_gates[] = {
[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), + + [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)), };
static struct ccu_reset h6_resets[] = { @@ -39,6 +41,8 @@ static struct ccu_reset h6_resets[] = {
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)), [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), + + [RST_BUS_EMAC] = RESET(0x97c, BIT(16)), };
static const struct ccu_desc h6_ccu_desc = { diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 92907281f1..30beac98bb 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -29,6 +29,8 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -60,6 +62,7 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), + [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)), [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
On Wed, Feb 27, 2019 at 1:00 PM Jagan Teki jagan@amarulasolutions.com wrote:
- Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sun8i_emac.c | 57 +++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 15 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a7fb7ac405..98bd7a5823 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -14,12 +14,14 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <common.h> +#include <clk.h> #include <dm.h> #include <fdt_support.h> #include <linux/err.h> #include <malloc.h> #include <miiphy.h> #include <net.h> +#include <reset.h> #include <dt-bindings/pinctrl/sun4i-a10.h> #ifdef CONFIG_DM_GPIO #include <asm-generic/gpio.h> @@ -135,6 +137,8 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; + struct clk tx_clk; + struct reset_ctl tx_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -647,9 +651,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) return _sun8i_write_hwaddr(priv, pdata->enetaddr); }
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int ret; + + ret = clk_enable(&priv->tx_clk); + if (ret) { + dev_err(dev, "failed to enable TX clock\n"); + return ret; + } + + if (reset_valid(&priv->tx_rst)) { + ret = reset_deassert(&priv->tx_rst); + if (ret) { + dev_err(dev, "failed to deassert TX reset\n"); + goto err_tx_clk; + } + }
if (priv->variant == H3_EMAC) { /* Only H3/H5 have clock controls for internal EPHY */ @@ -664,19 +683,11 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } }
- if (priv->variant == R40_GMAC) { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); - } else { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + return 0;
- /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - } +err_tx_clk: + clk_disable(&priv->tx_clk); + return ret; }
#if defined(CONFIG_DM_GPIO) @@ -803,10 +814,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev) struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); + int ret;
priv->mac_reg = (void *)pdata->iobase;
- sun8i_emac_board_setup(priv); + ret = sun8i_emac_board_setup(priv); + if (ret) + return ret; + sun8i_emac_set_syscon(sun8i_pdata, priv);
sun8i_mdio_init(dev->name, dev); @@ -835,8 +850,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) int offset = 0; #ifdef CONFIG_DM_GPIO int reset_flags = GPIOD_IS_OUT; - int ret = 0; #endif + int ret;
pdata->iobase = devfdt_get_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { @@ -851,6 +866,18 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }
+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk); + if (ret) { + dev_err(dev, "failed to get TX clock\n"); + return ret; + } + + ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get TX reset\n"); + return ret; + } + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); if (offset < 0) { debug("%s: cannot find syscon node\n", __func__);
On Wed, Feb 27, 2019 at 1:03 PM Jagan Teki jagan@amarulasolutions.com wrote:
Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respetive clock and reset reg and bits.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_h3.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f5ae1e9555..6111a13f1c 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -34,6 +34,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
+ [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), + [CLK_SPI0] = GATE(0x0a0, BIT(31)), [CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -69,6 +71,8 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
+ [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
On Wed, Feb 27, 2019 at 1:02 PM Jagan Teki jagan@amarulasolutions.com wrote:
EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respetive
Please fix typo in log above. respetive -> respective
clock and reset reg and bits.
Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sun8i_emac.c | 74 +++++++++++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 17 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 98bd7a5823..c0a440886e 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -138,7 +138,9 @@ struct emac_eth_dev { struct phy_device *phydev; struct mii_dev *bus; struct clk tx_clk; + struct clk ephy_clk; struct reset_ctl tx_rst; + struct reset_ctl ephy_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -653,7 +655,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int ret;
ret = clk_enable(&priv->tx_clk); @@ -670,16 +671,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv) } }
- if (priv->variant == H3_EMAC) { - /* Only H3/H5 have clock controls for internal EPHY */ - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, - BIT(AHB_GATE_OFFSET_EPHY)); - - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, - BIT(AHB_RESET_OFFSET_EPHY)); + /* Only H3/H5 have clock controls for internal EPHY */ + if (clk_valid(&priv->ephy_clk)) { + ret = clk_enable(&priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to enable EPHY TX clock\n"); + return ret; + } + } + + if (reset_valid(&priv->ephy_rst)) { + ret = reset_deassert(&priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to deassert EPHY TX clock\n"); + return ret; } }
@@ -839,6 +844,44 @@ static const struct eth_ops sun8i_emac_eth_ops = { .stop = sun8i_emac_eth_stop, };
+static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv) +{ + int node, ret; + + /* look for mdio-mux node for internal PHY node */ + node = fdt_path_offset(gd->fdt_blob, + "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1"); + if (node < 0) { + debug("failed to get mdio-mux with internal PHY\n"); + return node; + } + + ret = fdt_node_check_compatible(gd->fdt_blob, node, + "allwinner,sun8i-h3-mdio-internal"); + if (ret < 0) { + debug("failed to find mdio-internal node\n"); + return ret; + } + + ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0, + &priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to get EPHY TX clock\n"); + return ret; + } + + ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0, + &priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to get EPHY TX reset\n"); + return ret; + } + + priv->use_internal_phy = true; + + return 0; +} + static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); @@ -920,12 +963,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) }
if (priv->variant == H3_EMAC) { - int parent = fdt_parent_offset(gd->fdt_blob, offset); - - if (parent >= 0 && - !fdt_node_check_compatible(gd->fdt_blob, parent, - "allwinner,sun8i-h3-mdio-internal")) - priv->use_internal_phy = true; + ret = sun8i_get_ephy_nodes(priv); + if (ret) + return ret; }
priv->interface = pdata->phy_interface;
On Wed, Feb 27, 2019 at 1:03 PM Jagan Teki jagan@amarulasolutions.com wrote:
Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework.
Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- board/sunxi/gmac.c | 8 -------- 1 file changed, 8 deletions(-)
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 826650c89b..d8fdf7728e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -12,14 +12,6 @@ void eth_init_board(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); -#else - setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); -#endif - /* Set MII clock */ #ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
participants (3)
-
Jagan Teki -
Joe Hershberger -
Simon Glass