[U-Boot] [PATCH 1/2] net: phy: mv88e61xx: Force CPU port link up
When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link.
Cc: Kevin Smith kevin.smith@elecsyscorp.com Signed-off-by: Chris Packham judge.packham@gmail.com ---
drivers/net/phy/mv88e61xx.c | 51 ++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 17040bd6ccdd..ea54a1531053 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -705,6 +705,31 @@ unforce: return res; }
+static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + if (port == CONFIG_MV88E61XX_CPU_PORT) + val |= PORT_REG_PHYS_CTRL_LINK_VALUE | + PORT_REG_PHYS_CTRL_LINK_FORCE; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_set_cpu_port(struct phy_device *phydev) { int val; @@ -748,6 +773,11 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) if (val < 0) return val; } + } else { + val = mv88e61xx_fixed_port_setup(phydev, + CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; }
return 0; @@ -810,27 +840,6 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; }
-static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) -{ - int val; - - val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); - if (val < 0) - return val; - - val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | - PORT_REG_PHYS_CTRL_FC_VALUE); - val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | - PORT_REG_PHYS_CTRL_PCS_AN_RST | - PORT_REG_PHYS_CTRL_FC_FORCE | - PORT_REG_PHYS_CTRL_DUPLEX_VALUE | - PORT_REG_PHYS_CTRL_DUPLEX_FORCE | - PORT_REG_PHYS_CTRL_SPD1000; - - return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, - val); -} - static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val;
The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.
For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.
Signed-off-by: Chris Packham judge.packham@gmail.com ---
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 14 ++++++++++++-- configs/SBx81LIFKW_defconfig | 6 ++++++ include/configs/SBx81LIFKW.h | 5 ----- 3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index 3cacdc837234..e58bbf07ef15 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -164,9 +164,15 @@ int board_init(void) return 0; }
-#ifdef CONFIG_MV88E61XX_SWITCH -/* Configure and enable Switch and PHY */ +#ifdef CONFIG_RESET_PHY_R +/* automatically defined by kirkwood config.h */ void reset_phy(void) +{ +} +#endif + +#ifdef CONFIG_MV88E61XX_SWITCH +int mv88e61xx_hw_reset(struct phy_device *phydev) { /* Ensure the 88e6097 gets at least 10ms Reset */ @@ -174,6 +180,10 @@ void reset_phy(void) mdelay(20); kw_gpio_set_value(MV88E6097_RESET, 1); mdelay(20); + + phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; + + return 0; } #endif
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index ec9df1ac691c..348f861a143b 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_NTPSERVER=y +CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_OF_CONTROL=y @@ -29,5 +30,10 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_MV88E61XX_SWITCH=y +CONFIG_MV88E61XX_CPU_PORT=10 +CONFIG_MV88E61XX_PHY_PORTS=0x003 +CONFIG_MV88E61XX_FIXED_PORTS=0x300 CONFIG_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 756eaa47fa92..bcc2c201d222 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -103,15 +103,10 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi over miiphy interface */ -#define CONFIG_PHYLIB #define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ #define CONFIG_PHY_BASE_ADR 0x01 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch */ -#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ -#define CONFIG_MV88E61XX_PHY_PORTS 0x303 /* Pt0,1,8,9 */ -#define CONFIG_MV88E61XX_CPU_PORT 10 /* 10(CPU) */ #endif /* CONFIG_CMD_NET */
/*
On 03.06.2018 06:21, Chris Packham wrote:
The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.
For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.
Signed-off-by: Chris Packham judge.packham@gmail.com
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 14 ++++++++++++-- configs/SBx81LIFKW_defconfig | 6 ++++++ include/configs/SBx81LIFKW.h | 5 ----- 3 files changed, 18 insertions(+), 7 deletions(-)
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On 03.06.2018 06:21, Chris Packham wrote:
The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.
For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.
Signed-off-by: Chris Packham judge.packham@gmail.com
Applied to u-boot-marvell/master.
Thanks, Stefan
On Sat, Jun 2, 2018 at 11:21 PM, Chris Packham judge.packham@gmail.com wrote:
When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link.
Cc: Kevin Smith kevin.smith@elecsyscorp.com Signed-off-by: Chris Packham judge.packham@gmail.com
Signed-off-by: Joe Hershberger joe.hershberger@ni.com
On Wed, Jun 6, 2018 at 5:30 PM, Joe Hershberger joe.hershberger@ni.com wrote:
On Sat, Jun 2, 2018 at 11:21 PM, Chris Packham judge.packham@gmail.com wrote:
When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link.
Cc: Kevin Smith kevin.smith@elecsyscorp.com Signed-off-by: Chris Packham judge.packham@gmail.com
Signed-off-by: Joe Hershberger joe.hershberger@ni.com
Make that,
Acked-by: Joe Hershberger joe.hershberger@ni.com
Hi Chris,
https://patchwork.ozlabs.org/patch/924667/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git
Thanks! -Joe
participants (3)
-
Chris Packham -
Joe Hershberger -
Stefan Roese