At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this.

Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

doc/device-tree-bindings/pci/x86-pci.txt | 7 ++++- drivers/pci/pci-uclass.c | 33 +++++++++++++++++++++++- include/dt-bindings/pci/pci.h | 12 +++++++++ include/pci.h | 1 - 4 files changed, 50 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/pci/pci.h

diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt index 95e370b3e72..cf4e5ed595a 100644 --- a/doc/device-tree-bindings/pci/x86-pci.txt +++ b/doc/device-tree-bindings/pci/x86-pci.txt @@ -20,6 +20,10 @@ For PCI devices the following optional property is available: output to be lost. This should not generally be used in production code, although it is often harmless.

+- u-boot,pci-pre-reloc : List of vendor/device IDs to bind before relocation, even + if they are not bridges. This is useful if the device is needed (e.g. a + UART). The format is 0xvvvvdddd where d is the device ID and v is the + vendor ID.

Example:

@@ -32,7 +36,8 @@ pci { 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xefff>; u-boot,skip-auto-config-until-reloc; - + u-boot,pci-pre-reloc = < + PCI_VENDEV(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2)>;

serial: serial@18,2 { reg = <0x0200c210 0 0 0 0>; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index dffe5297944..ec3797746ba 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -19,6 +19,7 @@ #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) #include <asm/fsp/fsp_support.h> #endif +#include <dt-bindings/pci/pci.h> #include <linux/delay.h> #include "pci_internal.h"

@@ -673,6 +674,34 @@ static bool pci_match_one_id(const struct pci_device_id *id, return false; }

+/** + * pci_need_device_pre_reloc() - Check if a device should be bound + * + * This checks a list of vendor/device-ID values indicating devices that should + * be bound before relocation. + * + * @bus: Bus to check + * @vendor: Vendor ID to check + * @device: Device ID to check + * @return true if the vendor/device is in the list, false if not + */ +static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor, + uint device) +{ + u32 vendev; + int index; + + for (index = 0; + !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index, + &vendev); + index++) { + if (vendev == PCI_VENDEV(vendor, device)) + return true; + } + + return false; +} + /** * pci_find_and_bind_driver() - Find and bind the right PCI driver * @@ -761,7 +790,9 @@ static int pci_find_and_bind_driver(struct udevice *parent, * precious memory space as on some platforms as that space is pretty * limited (ie: using Cache As RAM). */ - if (!(gd->flags & GD_FLG_RELOC) && !bridge) + if (!(gd->flags & GD_FLG_RELOC) && !bridge && + !pci_need_device_pre_reloc(parent, find_id->vendor, + find_id->device)) return log_msg_ret("notbr", -EPERM);

/* Bind a generic driver so that the device can be used */ diff --git a/include/dt-bindings/pci/pci.h b/include/dt-bindings/pci/pci.h new file mode 100644 index 00000000000..e7290277b90 --- /dev/null +++ b/include/dt-bindings/pci/pci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides common constants for PCI bindings. + */ + +#ifndef _DT_BINDINGS_PCI_PCI_H +#define _DT_BINDINGS_PCI_PCI_H + +/* Encode a vendor and device ID into a single cell */ +#define PCI_VENDEV(v, d) (((v) << 16) | (d)) + +#endif /* _DT_BINDINGS_PCI_PCI_H */ diff --git a/include/pci.h b/include/pci.h index f2dfbda5b08..fe7064b2a44 100644 --- a/include/pci.h +++ b/include/pci.h @@ -578,7 +578,6 @@ typedef int pci_dev_t; #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) -#define PCI_VENDEV(v, d) (((v) << 16) | (d)) #define PCI_ANY_ID (~0)

/* Convert from Linux format to U-Boot format */

At present this driver relies on coreboot to provide information about the console UART. However if coreboot is not compiled with the UART enabled, the information is left out. This configuration is quite common, e.g. with shipping x86-based Chrome OS Chromebooks.

Add a way to determine the UART settings in this case, using a hard-coded list of PCI IDs.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++---- include/pci_ids.h | 1 + 2 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c index de09c8681f5..4b4619432d8 100644 --- a/drivers/serial/serial_coreboot.c +++ b/drivers/serial/serial_coreboot.c @@ -11,19 +11,71 @@ #include <serial.h> #include <asm/cb_sysinfo.h>

+static const struct pci_device_id ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2) }, + {}, +}; + +/* + * Coreboot only sets up the UART if it uses it and doesn't bother to put the + * details in sysinfo if it doesn't. Try to guess in that case, using devices + * we know about + * + * @plat: Platform data to fill in + * @return 0 if found, -ve if no UART was found + */ +static int guess_uart(struct ns16550_plat *plat) +{ + struct udevice *bus, *dev; + ulong addr; + int index; + int ret; + + ret = uclass_first_device_err(UCLASS_PCI, &bus); + if (ret) + return ret; + index = 0; + ret = pci_bus_find_devices(bus, ids, &index, &dev); + if (ret) + return ret; + addr = dm_pci_read_bar32(dev, 0); + plat->base = addr; + plat->reg_shift = 2; + plat->reg_width = 4; + plat->clock = 1843200; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + + return 0; +} + static int coreboot_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); struct cb_serial *cb_info = lib_sysinfo.serial;

- plat->base = cb_info->baseaddr; - plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0; - plat->reg_width = cb_info->regwidth; - plat->clock = cb_info->input_hertz; - plat->fcr = UART_FCR_DEFVAL; - plat->flags = 0; - if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED) - plat->flags |= NS16550_FLAG_IO; + if (cb_info) { + plat->base = cb_info->baseaddr; + plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0; + plat->reg_width = cb_info->regwidth; + plat->clock = cb_info->input_hertz; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED) + plat->flags |= NS16550_FLAG_IO; + } else if (CONFIG_IS_ENABLED(PCI)) { + int ret; + + ret = guess_uart(plat); + if (ret) { + /* + * Returning an error will cause U-Boot to complain that + * there is no UART, which may panic. So stay silent and + * pray that the video console will work. + */ + log_debug("Cannot detect UART\n"); + } + }

return 0; } diff --git a/include/pci_ids.h b/include/pci_ids.h index 7ecedc7f04c..d91c1d08f1a 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2987,6 +2987,7 @@ #define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 #define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f +#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0 #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 #define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5

These headers are not actually used. Drop them so that this driver can be used by other boards, e.g. coreboot.

Signed-off-by: Simon Glass sjg@chromium.org

Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

drivers/tpm/cr50_i2c.c | 2 -- 1 file changed, 2 deletions(-)

diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 76432bdec1f..7a2b5a4faa5 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -18,8 +18,6 @@ #include <acpi/acpi_device.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/iomap.h> -#include <asm/arch/pm.h> #include <linux/delay.h> #include <dm/acpi.h>

These constants conflict with error codes returned by the MP implementation when something is wrong. In particular, mp_first_cpu() returns MP_SELECT_BSP when running without multiprocessing enabled. Since this is -2, it is interpreted as an error by callers, which expect a positive CPU number for the first CPU.

Correct this by using a different range for the pre-defined CPU numbers, above zero and out of the range of possible CPU values. For now it is safe to assume there are no more than 64K CPUs.

This fixes the 'mtrr' command when CONFIG_SMP is not enabled.

Signed-off-by: Simon Glass sjg@chromium.org

Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

arch/x86/include/asm/mp.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 1a3ae8e3950..e48ba051d92 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -10,18 +10,22 @@

#include <asm/atomic.h> #include <asm/cache.h> +#include <linux/bitops.h>

struct udevice;

enum { - /* Indicates that the function should run on all CPUs */ - MP_SELECT_ALL = -1, + /* + * Indicates that the function should run on all CPUs. We use a large + * number, above the number of real CPUs we expect to find. + */ + MP_SELECT_ALL = BIT(16),

/* Run on boot CPUs */ - MP_SELECT_BSP = -2, + MP_SELECT_BSP,

/* Run on non-boot CPUs */ - MP_SELECT_APS = -3, + MP_SELECT_APS, };

typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);

The BIOS version may not be present, e.g. on a Chrome OS build. Add the BIOS date as well, so we get some sort of indication of coreboot's vintage.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Reorder declaration and use bios_date for the variable name

board/coreboot/coreboot/coreboot.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 175d3ce691a..11294d6e870 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -37,6 +37,7 @@ int show_board_info(void) goto fallback;

const char *bios_ver = smbios_string(bios, t0->bios_ver); + const char *bios_date = smbios_string(bios, t0->bios_release_date); const char *model = smbios_string(system, t1->product_name); const char *manufacturer = smbios_string(system, t1->manufacturer);

@@ -46,6 +47,8 @@ int show_board_info(void) printf("Vendor: %s\n", manufacturer); printf("Model: %s\n", model); printf("BIOS Version: %s\n", bios_ver); + if (bios_date) + printf("BIOS date: %s\n", bios_date);

return 0;

Set up coral so that it can boot from coreboot, even though it is a bare-metal build. This helps with testing since the same image can be used in both cases.

Signed-off-by: Simon Glass sjg@chromium.org

Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v2: - Add missing newline in the error path - Use (ret) instead of (ret != 0) to fit with U-Boot style

board/google/chromebook_coral/coral.c | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)

diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 3f9235c903b..85cba50d4e5 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -10,17 +10,21 @@ #include <command.h> #include <cros_ec.h> #include <dm.h> +#include <init.h> #include <log.h> #include <sysinfo.h> #include <acpi/acpigen.h> #include <asm-generic/gpio.h> #include <asm/acpi_nhlt.h> +#include <asm/cb_sysinfo.h> #include <asm/intel_gnvs.h> #include <asm/intel_pinctrl.h> #include <dm/acpi.h> #include <linux/delay.h> #include "variant_gpio.h"

+DECLARE_GLOBAL_DATA_PTR; + struct cros_gpio_info { const char *linux_name; enum cros_gpio_t type; @@ -28,6 +32,30 @@ struct cros_gpio_info { int flags; };

+int misc_init_f(void) +{ + if (!ll_boot_init()) { + printf("Running as secondary loader"); + if (gd->arch.coreboot_table) { + int ret; + + printf(" (found coreboot table at %lx)", + gd->arch.coreboot_table); + + ret = get_coreboot_info(&lib_sysinfo); + if (ret) { + printf("\nFailed to parse coreboot tables (err=%d)\n", + ret); + return ret; + } + } + + printf("\n"); + } + + return 0; +} + int arch_misc_init(void) { return 0;

Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be defined TARGET_COREBOOT.

Signed-off-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

arch/x86/cpu/coreboot/Kconfig | 2 +- board/coreboot/coreboot/Kconfig | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 497d6284ac1..b97c2779041 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -1,4 +1,4 @@ -if TARGET_COREBOOT +if VENDOR_COREBOOT

config SYS_COREBOOT bool diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 5bd6465d989..05e9b3b6f75 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -1,4 +1,4 @@ -if TARGET_COREBOOT +if VENDOR_COREBOOT

config SYS_BOARD default "coreboot" @@ -9,9 +9,6 @@ config SYS_VENDOR config SYS_SOC default "coreboot"

-config SYS_CONFIG_NAME - default "coreboot" - config SYS_TEXT_BASE default 0x01110000

@@ -31,4 +28,11 @@ config SYS_CAR_SIZE help This option specifies the board specific Cache-As-RAM (CAR) size.

+endif # CONFIG_VENDOR_COREBOOT + +if TARGET_COREBOOT + +config SYS_CONFIG_NAME + default "coreboot" + endif

Add information about memory usage when U-Boot is started from coreboot. This is useful when debugging. Also, since coreboot takes a chunk of memory in the middle of SDRAM for use by PCI devices, it can help avoid overwriting this with a loaded kernel by accident.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Convert table to reST format

doc/board/coreboot/coreboot.rst | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 9c44c025a48..3792f9e1c8d 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -50,3 +50,24 @@ works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It can be useful for running UEFI applications, for example.

This has only been lightly tested. + + +Memory map +---------- + + ========== ================================================================== + Address Region at that address + ========== ================================================================== + ffffffff Top of ROM (and last byte of 32-bit address space) + 7a9fd000 Typical top of memory available to U-Boot + (use cbsysinfo to see where memory range 'table' starts) + 10000000 Memory reserved by coreboot for mapping PCI devices + (typical size 2151000, includes framebuffer) + 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup + 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc) + 110000 CONFIG_BLOBLIST_ADDR (before being relocated) + 100000 CONFIG_PRE_CON_BUF_ADDR + f0000 ACPI tables set up by U-Boot + (typically redirects to 7ab10030 or similar) + 500 Location of coreboot sysinfo table, used during startup + ========== ==================================================================

All the x86 devicetree files are built at once, whichever board is actually being built. If coreboot is the target build, CONFIG_ROM_SIZE is not defined and samus cannot build Chromium OS verified boot. Add this condition to avoid errors about CONFIG_ROM_SIZE being missing.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Jaehoon Chung jh80.chung@samsung.com ---

Changes in v2: - Add 'cros' tag since this not a generic x86 change

arch/x86/dts/chromebook_coral.dts | 2 +- arch/x86/dts/chromebook_samus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index c8cb4e21c6d..66c31efb6cd 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -10,7 +10,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"

-#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-16mb-rw.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index adaeb1ea355..ad35ab2e3fd 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -11,7 +11,7 @@

#include "smbios.dtsi"

-#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-8mb-rw.dtsi"