[PATCH 1/8] Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig
This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
And we remove the entries from the README for a number of already converted items.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 51 ------------------- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2081ardb_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + drivers/ddr/fsl/Kconfig | 7 +++ include/configs/kontron_sl28.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls2080a_common.h | 3 -- include/configs/lx2160a_common.h | 1 - include/fsl_ddr.h | 5 -- 23 files changed, 22 insertions(+), 63 deletions(-)
diff --git a/README b/README index 6b6f7227336a..ebfdced4a725 100644 --- a/README +++ b/README @@ -363,68 +363,17 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base.
- CONFIG_SYS_FSL_DDRC_GEN1 - Freescale DDR1 controller. - - CONFIG_SYS_FSL_DDRC_GEN2 - Freescale DDR2 controller. - - CONFIG_SYS_FSL_DDRC_GEN3 - Freescale DDR3 controller. - - CONFIG_SYS_FSL_DDRC_GEN4 - Freescale DDR4 controller. - - CONFIG_SYS_FSL_DDRC_ARM_GEN3 - Freescale DDR3 controller for ARM-based SoCs. - - CONFIG_SYS_FSL_DDR1 - Board config to use DDR1. It can be enabled for SoCs with - Freescale DDR1 or DDR2 controllers, depending on the board - implemetation. - - CONFIG_SYS_FSL_DDR2 - Board config to use DDR2. It can be enabled for SoCs with - Freescale DDR2 or DDR3 controllers, depending on the board - implementation. - - CONFIG_SYS_FSL_DDR3 - Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 or DDR3L controllers. - - CONFIG_SYS_FSL_DDR3L - Board config to use DDR3L. It can be enabled for SoCs with - DDR3L controllers. - CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller).
CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_BE - Defines the DDR controller register space as Big Endian - - CONFIG_SYS_FSL_DDR_LE - Defines the DDR controller register space as Little Endian - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs.
- CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS - Number of controllers used as main memory. - - CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS - Number of controllers used for other than main memory. - - CONFIG_SYS_FSL_SEC_BE - Defines the SEC controller register space as Big Endian - - CONFIG_SYS_FSL_SEC_LE - Defines the SEC controller register space as Little Endian - - MIPS CPU options: CONFIG_XWAY_SWAP_BYTES
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1f86070b8a2c..91a5863c97fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -193,6 +193,7 @@ config ARCH_LS2080A select FSL_IFC select FSL_LAYERSCAPE select FSL_LSCH3 + select SYS_FSL_OTHER_DDR_NUM_CTRLS select GICV3 select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index afb4e48e7e85..034f15760b43 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 15dadeb4e420..d8efe46f3c6c 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -57,6 +57,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 9fc1801c15da..a0fbb7d3c347 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -77,6 +77,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index d2dd95ea792d..9925333678b1 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -58,6 +58,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e2e4cfdd9364..9d852531092d 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -72,6 +72,7 @@ CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 5378876f11b9..46dde0b6b8b4 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 6570a466e0c5..87129967f258 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 7c87f890c2c2..da463ebf42b4 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -81,6 +81,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index a426d6d48fb1..cc4bbaca436b 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -59,6 +59,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index f082fa52bcc5..c5cc05bd3a49 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -64,6 +64,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 1972fc908f54..008ee1f023d9 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index dedc191edc06..bcf869ff1274 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 1674a2ce0916..f633af34bb05 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -59,6 +59,7 @@ CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 071db6b1d2e4..3d8e201db1ab 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -66,6 +66,7 @@ CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DIMM_SLOTS_PER_CTLR=2 +CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_FSL_DDR_INTLV_256B=y diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 22400a9b8bab..7f8f3570dd8c 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -40,6 +40,9 @@ config FSL_DDR_SYNC_REFRESH config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE bool
+config SYS_FSL_OTHER_DDR_NUM_CTRLS + bool + menu "Freescale DDR controllers" depends on SYS_FSL_DDR
@@ -63,6 +66,10 @@ config DIMM_SLOTS_PER_CTLR int "Number of DIMM slots per controller" default 1
+config SYS_FSL_DDR_MAIN_NUM_CTRLS + int "Number of controllers used as main memory" + default SYS_NUM_DDR_CTLRS + config SYS_FSL_DDR_VER int default 50 if SYS_FSL_DDR_VER_50 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 2373abf3e31d..38063ba4842d 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/* early stack pointer */
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index b104524becb1..8413e68f3a79 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/* * SMP Definitinos diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 4b8462da7bcd..21afe80e70de 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 /* * SMP Definitinos */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index ba5af6c34d34..e170b5aa2c70 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -21,15 +21,12 @@ #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
/* * SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS - /* * This is not an accurate number. It is used in start.S. The frequency * will be udpated later when get_bus_freq(0) is available. diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 61870717e8e1..d39c0032c4a1 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 025d7a1e74b6..24229f6bc448 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -14,11 +14,6 @@
struct cmd_tbl;
-#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS -/* All controllers are for main memory */ -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS -#endif - #ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v)
We can determine which of these we need given CPU_BIG_ENDIAN being enabled or not, so move that logic to Kconfig from config.mk.
Cc: Alexey Brodkin alexey.brodkin@synopsys.com Cc: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com Signed-off-by: Tom Rini trini@konsulko.com --- This is not a size neutral patch as apparently before we were not fully populating SYS_BIG_ENDIAN to all of the codebase, so testing this on nsim_700be or nsim_hs38be would be a good idea. --- README | 4 ---- arch/Kconfig | 2 ++ arch/arc/config.mk | 6 ------ 3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/README b/README index ebfdced4a725..ff0534137716 100644 --- a/README +++ b/README @@ -351,10 +351,6 @@ The following options need to be configured: clocks to the sysclock, ddrclock and usbclock.
- Generic CPU options: - CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN - - Defines the endianess of the CPU. Implementation of those - values is arch specific.
CONFIG_SYS_FSL_DDR Freescale DDR driver in use. This type of DDR controller is diff --git a/arch/Kconfig b/arch/Kconfig index 6495e780fec9..c4dc47dccb43 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -53,6 +53,8 @@ config ARC select SUPPORT_OF_CONTROL select SYS_CACHE_SHIFT_7 select TIMER + select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN + select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
config ARM bool "ARM architecture" diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 118472b2d0ba..2b70945ac342 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -2,12 +2,6 @@ # # Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-ifndef CONFIG_CPU_BIG_ENDIAN -CONFIG_SYS_LITTLE_ENDIAN = 1 -else -CONFIG_SYS_BIG_ENDIAN = 1 -endif - ifdef CONFIG_SYS_LITTLE_ENDIAN KBUILD_LDFLAGS += -EL PLATFORM_CPPFLAGS += -mlittle-endian
On Sun, Jul 31, 2022 at 09:08:23PM -0400, Tom Rini wrote:
We can determine which of these we need given CPU_BIG_ENDIAN being enabled or not, so move that logic to Kconfig from config.mk.
Cc: Alexey Brodkin alexey.brodkin@synopsys.com Cc: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE
Signed-off-by: Tom Rini trini@konsulko.com --- README | 15 --------------- arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 ----- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ------ arch/arm/include/asm/arch-ls102xa/config.h | 3 --- arch/m68k/cpu/mcf52x2/start.S | 4 ---- arch/m68k/cpu/mcf530x/start.S | 4 ---- arch/powerpc/include/asm/config_mpc85xx.h | 10 ---------- arch/powerpc/include/asm/immap_85xx.h | 13 ------------- include/configs/P2041RDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/bk4r1.h | 7 ------- include/configs/corenet_ds.h | 1 - include/configs/eb_cpu5282.h | 2 -- include/configs/km/km-mpc8309.h | 5 ----- include/configs/ls1021atsn.h | 4 ---- include/configs/m53menlo.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53cx9020.h | 1 - include/configs/mx53loco.h | 1 - include/configs/socrates.h | 1 - include/configs/usbarmory.h | 1 - include/configs/vf610twr.h | 1 - 24 files changed, 90 deletions(-)
diff --git a/README b/README index ff0534137716..05c84141ebbe 100644 --- a/README +++ b/README @@ -330,21 +330,6 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround.
- CONFIG_SYS_FSL_DSP_DDR_ADDR - This value denotes start offset of DDR memory which is - connected exclusively to the DSP cores. - - CONFIG_SYS_FSL_DSP_M2_RAM_ADDR - This value denotes start offset of M2 memory - which is directly connected to the DSP core. - - CONFIG_SYS_FSL_DSP_M3_RAM_ADDR - This value denotes start offset of M3 memory which is directly - connected to the DSP core. - - CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - This value denotes start offset of DSP CCSR space. - CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1791b978704d..587d585412bb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -94,8 +94,6 @@ #define EPU_EPCTR5 0x700060a14ULL #define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_ERRATUM_A008751 - #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1088A) @@ -218,9 +216,6 @@ #define DCSR_DCFG_SBEESR2 0x20140534 #define DCSR_DCFG_MBEESR2 0x20140544
-#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE - /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FSL_QMAN_V3 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index f2dbcdc8164f..1fb1191a65ea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -166,12 +166,6 @@ struct sys_info { };
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 -#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 -#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 -#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 -#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 #define CONFIG_SYS_FSL_FM1_ADDR \ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 868456f1f139..1b2be8fcde79 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,9 +79,6 @@ #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif
-#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE - #define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index d3cdc4217617..4488a6e4c7fb 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -303,10 +303,6 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ - defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) - halt -#endif jsr (%a1)
/******************************************************************************/ diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 0daff5d0c4cf..287e8e7873c5 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -226,10 +226,6 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \ - defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) - halt -#endif jsr (%a1)
/******************************************************************************/ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 458c0a8d3653..543b0c55358e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -137,19 +137,12 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#elif defined(CONFIG_ARCH_T4240) @@ -202,7 +195,6 @@ #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -212,7 +204,6 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_DSP_CPUS 2 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 @@ -288,7 +279,6 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b8bc58448217..7e88779227a4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1464,7 +1464,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -1477,8 +1476,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 -#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -2576,20 +2573,10 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-#if defined(CONFIG_ARCH_BSC9132) -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ - (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) -#endif - #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_SCFG_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) -#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) -#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index de5f42b10117..1ba48e587215 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -326,7 +326,6 @@
#ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif
/* diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 3da9831a028e..9d43d87338a9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -434,7 +434,6 @@ */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif
/* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 813d8fae9c8c..9a9920a88055 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -391,7 +391,6 @@ */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif
/* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 332f34e1ff22..4280c2df1fab 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -397,7 +397,6 @@
#ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 925a68787c91..b3e1fddc02fc 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -55,13 +55,6 @@
#define IMX_FEC1_BASE ENET1_BASE_ADDR
-/* QSPI Configs*/ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (SZ_16M) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SYS_FSL_QSPI_LE -#endif - /* boot command, including the target-defined one if any */
/* Extra env settings (including the target-defined ones if any) */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a4fb2b53dc9f..5f3fd89c21bb 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -319,7 +319,6 @@
#ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif
/* diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 249da66237b5..79cacd7dacc6 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -8,8 +8,6 @@ #ifndef _CONFIG_EB_CPU5282_H_ #define _CONFIG_EB_CPU5282_H_
-#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP - /*----------------------------------------------------------------------* * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h index af35e8e79267..0468ed5e831a 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -49,11 +49,6 @@ /* GPR_1 */ #define CONFIG_SYS_GPR1 0x50008060
-#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 2fbd495e1193..f318eb58603d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -75,10 +75,6 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0
-/* QSPI */ -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - /* PCIe */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index b3348bc63bb9..0499e633512b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -38,7 +38,6 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 #endif
/* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index a423dd28b07d..fbc9a0416938 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -35,7 +35,6 @@ * MMC Configs * */ #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index f1d751f15a24..d58d1534a3bd 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -18,7 +18,6 @@
/* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* bootz: zImage/initrd.img support */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9ceed12e4872..60ec34cf8e06 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -15,7 +15,6 @@
/* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 498deb4e3fc7..762ba44542d3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -103,7 +103,6 @@ /* FPGA and NAND */ #define CONFIG_SYS_FPGA_BASE 0xc0000000 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 2632d56cb1c2..08a6f5fbccdc 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -21,7 +21,6 @@
/* SD/MMC */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 32d9df0a00ce..c13f2ba196e6 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -21,7 +21,6 @@ #endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_FEC_MXC_PHYADDR 0
On Sun, Jul 31, 2022 at 09:08:24PM -0400, Tom Rini wrote:
This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This converts the following to Kconfig: CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Signed-off-by: Tom Rini trini@konsulko.com --- configs/pico-imx6_defconfig | 1 + configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + configs/warp_defconfig | 1 + drivers/mmc/Kconfig | 4 ++++ include/configs/pico-imx6.h | 1 - include/configs/warp.h | 1 - include/configs/warp7.h | 1 - 8 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 086b3ee3ab25..45f72d7e1e61 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -72,6 +72,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index a50a1c8bc770..d1c049925411 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 40f9e502e92f..d0b4e747dd23 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 4c9f7051fefc..63f2f21a1e60 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y CONFIG_FSL_USDHC=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c5e1a1b09817..0dcec8adcee8 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -864,6 +864,10 @@ config FSL_ESDHC_IMX This selects support for the i.MX eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs.
+config SYS_FSL_ESDHC_HAS_DDR_MODE + bool "i.MX eSDHC controller supports DDR mode" + depends on FSL_ESDHC_IMX + config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index df4dc4d496c6..dcbcd8d24495 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -22,7 +22,6 @@
/* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/warp.h b/include/configs/warp.h index 7cb9743fddb3..d2c4391935eb 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -18,7 +18,6 @@
/* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* Watchdog */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h index c00ca4a11172..7e9b25b07b20 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -15,7 +15,6 @@
/* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
On Sun, Jul 31, 2022 at 09:08:25PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 11 ----------- arch/arm/include/asm/arch-imx8/imx-regs.h | 1 - arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/arm/include/asm/arch-mx6/imx-regs.h | 1 - arch/arm/include/asm/arch-mx7/imx-regs.h | 1 - arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1 - arch/powerpc/include/asm/config_mpc85xx.h | 5 ----- drivers/crypto/fsl/Kconfig | 5 +++++ 9 files changed, 5 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 587d585412bb..1b108dde5355 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -94,8 +94,6 @@ #define EPU_EPCTR5 0x700060a14ULL #define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - #elif defined(CONFIG_ARCH_LS1088A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } @@ -129,7 +127,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ @@ -165,8 +162,6 @@
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - #elif defined(CONFIG_ARCH_LS1028A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } @@ -204,7 +199,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* SEC */ -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
/* DCFG - GUR */
@@ -258,12 +252,9 @@ #define GIC_ADDR_BIT 31 #define SCFG_GIC400_ALIGN 0x1570188
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 - #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@@ -281,8 +272,6 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01410000 #define GICC_BASE 0x01420000 - -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index 2d64b0604b92..3d32b7a02a18 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -48,6 +48,5 @@ #define USB_PHY0_BASE_ADDR 0x5b100000
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 6969cde26cc8..ff3b9ddd9f77 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -92,7 +92,6 @@ #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !defined(__ASSEMBLY__) #include <asm/types.h> #include <linux/bitops.h> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 1b2be8fcde79..0e32828b4f1e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -82,7 +82,6 @@ #define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index a8a5bf7a5754..56b3a58d478a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -244,7 +244,6 @@ #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 5cab12f30d88..1e9d11b7a5c1 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -221,7 +221,6 @@ #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/mach-imx/regs-lcdif.h> #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index cb0c2c15c03b..ffa170f4d255 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -234,7 +234,6 @@ #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 543b0c55358e..b5b59a015046 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -286,13 +286,8 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
-#if !defined(CONFIG_ARCH_C29X) -#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#endif - #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index e03fcdd9c7e4..b04c70183d24 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -10,6 +10,11 @@ config FSL_CAAM Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses Job Ring as interface to communicate with CAAM.
+config SYS_FSL_MAX_NUM_OF_SEC + int "Number of job rings in the CAAM" + depends on FSL_CAAM + default 1 + config CAAM_64BIT bool default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
On Sun, Jul 31, 2022 at 09:08:26PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS
Signed-off-by: Tom Rini trini@konsulko.com --- arch/Kconfig.nxp | 6 ++++++ arch/arm/cpu/armv7/ls102xa/clock.c | 4 ---- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 ---- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 5 ----- arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ---- arch/powerpc/include/asm/config_mpc85xx.h | 8 -------- configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028aqds_tfa_lpuart_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + configs/ls1088aqds_defconfig | 1 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_ifc_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + configs/ten64_tfa_defconfig | 1 + 70 files changed, 69 insertions(+), 28 deletions(-)
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index a96245c37230..8c5a6f63a9a5 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -227,6 +227,12 @@ config VOL_MONITOR_ISL68233_SET
endif
+config SYS_FSL_NUM_CC_PLLS + int "Number of clock control PLLs" + depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A + default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2 + default 6 if FSL_LSCH3 || MPC85xx + config SYS_FSL_ESDHC_BE bool
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index c5e6118cba5d..86b5b21ef862 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -13,10 +13,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#endif - void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 840e6d412b30..898ed09b310a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -18,10 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#endif - void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 1c04a5b5b7ea..58080d0047dd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -21,11 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS -#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 -#endif - - void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1b108dde5355..1850008a6d16 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -95,7 +95,6 @@ #define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_PAGE_SIZE 0x10000
@@ -141,7 +140,6 @@ #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_PAGE_SIZE 0x10000
@@ -163,7 +161,6 @@ /* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_FSL_TZASC_400
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 4b6f3d28baa6..6686b7c93cb5 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -20,10 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
- -#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS -#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 -#endif /* --------------------------------------------------------------- */
void get_sys_info(sys_info_t *sys_info) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b5b59a015046..0d31e70a7696 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -71,7 +71,6 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -87,7 +86,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -103,7 +101,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM2_DTSEC 4 @@ -120,7 +117,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -159,7 +155,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #endif -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SRDS_3 @@ -183,7 +178,6 @@ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 @@ -211,7 +205,6 @@
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 @@ -256,7 +249,6 @@ #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index da15a1cdb56e..0e8c2aa00bc2 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 96be038967d8..5b9f5a44690d 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 91f0ac56981b..0a061610c09a 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 78398207e5ba..b5a5163aa116 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index dd399466728a..7afb7a45ec85 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index bff11680216a..35e2e4f161d9 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index a0b55b0bb95d..2e50dc44f788 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -15,6 +15,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 2eb1f7f951b3..b494dfa82234 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -15,6 +15,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 35945812a7c8..b8728788886b 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 0d27e49c8ddb..cdd956b9f98d 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index ef75108eb977..6b22602e67c3 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index cf2d5de9547c..b36f525cc19c 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 81f04aecf22a..4111901fc401 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index fd28f3d8c775..5d493ee89c5e 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 5933485c65b1..dbcb02765d6c 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 200536a7fb0d..a7ec1a2d5b26 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -20,6 +20,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 281cc7169b9c..aed61e6dec54 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -20,6 +20,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index c7b337a66813..e5d4182179cd 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -22,6 +22,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 4983a5223183..08eff9a429ae 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -14,6 +14,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 30669d88e84c..7dd7cb8fb191 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -25,6 +25,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 17629f13498b..9fec1eb88cdd 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -25,6 +25,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 4c62d9316d21..878a37dacaeb 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index f68c87411e7b..1353f3311b9d 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -27,6 +27,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index ef29f474c94f..6b166c50d54f 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 62263b2fd4da..7c797c8aaa02 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -19,6 +19,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xqds_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_MP=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index a1db4a4bf8fa..d058a3300cbc 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -24,6 +24,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 6e9c70822221..73107ab97992 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -24,6 +24,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 719f022e8b07..2e07b6a46e24 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -26,6 +26,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 1117c015eeac..17f22cf894a1 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 10991e196469..9d3e9ef1e3a0 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -25,6 +25,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 0aa715dcac36..8e87cf0f3418 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -25,6 +25,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 07114a07c20b..4ba18893c478 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -27,6 +27,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 99b9c7931772..853d29703d9a 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -19,6 +19,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 CONFIG_MP=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index df3b5f3bc6fb..ab126a5d959b 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -24,6 +24,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=5 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index dc73dcdc1df6..06561d9d5556 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=5 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index dcc0b2987d1b..82ec1a963397 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y # CONFIG_DEEP_SLEEP is not set CONFIG_PCIE1=y +CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 CONFIG_MP=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index aaca8966c8f9..b0b5fb11ca76 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -24,6 +24,7 @@ CONFIG_ARMV8_PSCI=y CONFIG_ARMV8_PSCI_RELOCATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 752dca28dfb2..cf6452427f72 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index bb0e76df9bb1..8c30a1866cb1 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -17,6 +17,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 7025f114479a..c79aef5e16bb 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -16,6 +16,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 31773689a75a..c9bb579de95f 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index c953706216b9..269dd635b3c4 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -17,6 +17,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_ENV_ADDR=0x20500000 CONFIG_AHCI=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index aca271aa9f5f..48258e33a4ea 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -16,6 +16,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 9bed029a349f..d3d5cf42f5b5 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -16,6 +16,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 4a56e43e2bf5..13cae3954705 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -18,6 +18,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index d203fb9b13d1..1140cc1cc929 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 1bd83af10189..e947273a0182 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index c59de47ab63c..b4b7a4e6ff48 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index aa9bc8a46c36..32025068bbaa 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -16,6 +16,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 2459212c36f5..9f055caa8f23 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -18,6 +18,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index fc222b5dd2c3..9469e60f7760 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index eba206dd7bba..1554bd2fb869 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 347cc604105d..aabd4fb51550 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 362b4bea2b53..078f52978b88 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -21,6 +21,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 84aea7fb17cf..096144515b09 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 7fce30b3311e..1d480e7621f6 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -23,6 +23,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 42efefa41630..0a4e9d1955b8 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -22,6 +22,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 85ee4ca84589..8b958530c533 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -24,6 +24,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 547c8682e55c..e5d1c2415c53 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -24,6 +24,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 421008489bdf..2be5952302e8 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index dd1c0760987d..a94e29e4755a 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -23,6 +23,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 70faef837209..4592d4b34264 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -23,6 +23,7 @@ CONFIG_VID=y CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv" CONFIG_VOL_MONITOR_LTC3882_READ=y CONFIG_VOL_MONITOR_LTC3882_SET=y +CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y CONFIG_MP=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index dad6c2d9318d..9d58c4fcfacb 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -13,6 +13,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_TEN64_CONTROLLER=y CONFIG_AHCI=y +CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_DISTRO_DEFAULTS=y CONFIG_MP=y CONFIG_FIT_VERBOSE=y
On Sun, Jul 31, 2022 at 09:08:27PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This converts the following to Kconfig: CONFIG_SYS_FSL_PCIE_COMPAT
To do this, introduce a choice and option for each of the strings used and set CONFIG_SYS_FSL_PCIE_COMPAT based on that.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 5 --- arch/powerpc/cpu/mpc85xx/Kconfig | 37 +++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 12 -------- 3 files changed, 37 insertions(+), 17 deletions(-)
diff --git a/README b/README index 05c84141ebbe..4ef9e8c3ac7e 100644 --- a/README +++ b/README @@ -300,11 +300,6 @@ The following options need to be configured: system clock. On most PQ3 devices this is 8, on newer QorIQ devices it can be 16 or 32. The ratio varies from SoC to Soc.
- CONFIG_SYS_FSL_PCIE_COMPAT - - Defines the string to utilize when trying to match PCIe device - tree nodes for the given platform. - CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set, diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index a1704c211564..796a5477b0e6 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -206,6 +206,7 @@ config ARCH_B4420 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -236,6 +237,7 @@ config ARCH_B4860 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -273,6 +275,7 @@ config ARCH_BSC9132 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -381,6 +384,7 @@ config ARCH_P1010 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -462,6 +466,7 @@ config ARCH_P1023 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -549,6 +554,7 @@ config ARCH_P2041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -578,6 +584,7 @@ config ARCH_P3041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -611,6 +618,7 @@ config ARCH_P4080 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_NMG_CPU_A011 select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_PCIE_COMPAT_P4080_PCIE select SYS_P4080_ERRATUM_CPU22 select SYS_P4080_ERRATUM_PCIE_A003 select SYS_P4080_ERRATUM_SERDES8 @@ -647,6 +655,7 @@ config ARCH_P5040 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -677,6 +686,7 @@ config ARCH_T1024 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -704,6 +714,7 @@ config ARCH_T1040 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -730,6 +741,7 @@ config ARCH_T1042 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -758,6 +770,7 @@ config ARCH_T2080 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -790,6 +803,7 @@ config ARCH_T4240 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -1257,6 +1271,29 @@ config SYS_FSL_CPC config SYS_CACHE_STASHING bool "Enable cache stashing"
+config SYS_FSL_PCIE_COMPAT_P4080_PCIE + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + bool + +config SYS_FSL_PCIE_COMPAT + string + depends on FSL_CORENET + default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE + default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + help + Defines the string to utilize when trying to match PCIe device tree + nodes for the given platform. + config SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up" depends on MPC85xx diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0d31e70a7696..f972bee74708 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -27,7 +27,6 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
@@ -50,7 +49,6 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
/* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -76,7 +74,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -91,7 +88,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -108,7 +104,6 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -124,7 +119,6 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -139,7 +133,6 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#elif defined(CONFIG_ARCH_T4240) #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -166,7 +159,6 @@ #define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -183,7 +175,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#ifdef CONFIG_ARCH_B4860 @@ -217,7 +208,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE @@ -240,7 +230,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE @@ -268,7 +257,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
On Sun, Jul 31, 2022 at 09:08:28PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_FSL_PCIE_COMPAT
To do this, introduce a choice and option for each of the strings used and set CONFIG_SYS_FSL_PCIE_COMPAT based on that.
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This converts the following to Kconfig: CONFIG_FSL_NGPIXIS CONFIG_SYS_FSL_QMAN_V3 CONFIG_SYS_FSL_RAID_ENGINE CONFIG_SYS_FSL_RMU CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRIO_LIODN CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_USB1_PHY_ENABLE CONFIG_SYS_FSL_USB2_PHY_ENABLE CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Signed-off-by: Tom Rini trini@konsulko.com --- README | 6 -- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 + .../include/asm/arch-fsl-layerscape/config.h | 2 - arch/powerpc/cpu/mpc85xx/Kconfig | 70 +++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu.c | 3 - arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 -- arch/powerpc/include/asm/config_mpc85xx.h | 42 ----------- drivers/net/Kconfig | 4 ++ drivers/usb/host/Kconfig | 6 ++ include/configs/P3041DS.h | 2 - include/configs/P4080DS.h | 1 - include/configs/P5040DS.h | 3 - 12 files changed, 82 insertions(+), 63 deletions(-)
diff --git a/README b/README index 4ef9e8c3ac7e..a6c306149c73 100644 --- a/README +++ b/README @@ -294,12 +294,6 @@ The following options need to be configured: the "64" category of the Power ISA). This is necessary for ePAPR compliance, among other possible reasons.
- CONFIG_SYS_FSL_TBCLK_DIV - - Defines the core time base clock divider ratio compared to the - system clock. On most PQ3 devices this is 8, on newer QorIQ - devices it can be 16 or 32. The ratio varies from SoC to Soc. - CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 91a5863c97fb..8a7bbb4a6559 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -85,6 +85,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC @@ -123,6 +124,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 1850008a6d16..5824778ca286 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -209,7 +209,6 @@
/* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -256,7 +255,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 796a5477b0e6..65db15085712 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -25,6 +25,7 @@ config TARGET_P3041DS select PHYS_64BIT select ARCH_P3041 select BOARD_LATE_INIT if CHAIN_OF_TRUST + select FSL_NGPIXIS imply CMD_SATA imply PANIC_HANG
@@ -33,6 +34,7 @@ config TARGET_P4080DS select PHYS_64BIT select ARCH_P4080 select BOARD_LATE_INIT if CHAIN_OF_TRUST + select FSL_NGPIXIS imply CMD_SATA imply PANIC_HANG
@@ -41,6 +43,8 @@ config TARGET_P5040DS select PHYS_64BIT select ARCH_P5040 select BOARD_LATE_INIT if CHAIN_OF_TRUST + select FSL_NGPIXIS + select SYS_FSL_RAID_ENGINE imply CMD_SATA imply PANIC_HANG
@@ -209,6 +213,8 @@ config ARCH_B4420 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB1_PHY_ENABLE select SYS_PPC64 select FSL_IFC imply CMD_EEPROM @@ -240,6 +246,9 @@ config ARCH_B4860 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SRIO_LIODN + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB1_PHY_ENABLE select SYS_PPC64 select FSL_IFC imply CMD_EEPROM @@ -352,6 +361,7 @@ config ARCH_MPC8548 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC + select SYS_FSL_RMU select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB @@ -387,6 +397,7 @@ config ARCH_P1010 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_USB1_PHY_ENABLE select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC imply CMD_EEPROM @@ -524,6 +535,7 @@ config ARCH_P2020 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_RMU select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB @@ -557,6 +569,8 @@ config ARCH_P2041 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_USB1_PHY_ENABLE + select SYS_FSL_USB2_PHY_ENABLE select FSL_ELBC imply CMD_NAND
@@ -587,6 +601,8 @@ config ARCH_P3041 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_USB1_PHY_ENABLE + select SYS_FSL_USB2_PHY_ENABLE select FSL_ELBC imply CMD_NAND imply CMD_SATA @@ -628,6 +644,7 @@ config ARCH_P4080 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_RMU select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -658,6 +675,8 @@ config ARCH_P5040 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_USB1_PHY_ENABLE + select SYS_FSL_USB2_PHY_ENABLE select SYS_PPC64 select FSL_ELBC imply CMD_SATA @@ -689,6 +708,9 @@ config ARCH_T1024 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SINGLE_SOURCE_CLK + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB_DUAL_PHY_ENABLE select FSL_IFC imply CMD_EEPROM imply CMD_NAND @@ -717,6 +739,9 @@ config ARCH_T1040 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SINGLE_SOURCE_CLK + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB_DUAL_PHY_ENABLE select FSL_IFC imply CMD_MTDPARTS imply CMD_NAND @@ -744,6 +769,9 @@ config ARCH_T1042 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SINGLE_SOURCE_CLK + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB_DUAL_PHY_ENABLE select FSL_IFC imply CMD_MTDPARTS imply CMD_NAND @@ -773,6 +801,9 @@ config ARCH_T2080 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SRIO_LIODN + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -806,6 +837,9 @@ config ARCH_T4240 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SRIO_LIODN + select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN + select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -1094,6 +1128,12 @@ config FSL_PCIE_DISABLE_ASPM config FSL_PCIE_RESET bool
+config SYS_FSL_RAID_ENGINE + bool + +config SYS_FSL_RMU + bool + config SYS_FSL_QORIQ_CHASSIS1 bool
@@ -1259,6 +1299,9 @@ config FSL_CORENET bool select SYS_FSL_CPC
+config FSL_NGPIXIS + bool + config SYS_CPC_REINIT_F bool help @@ -1294,6 +1337,33 @@ config SYS_FSL_PCIE_COMPAT Defines the string to utilize when trying to match PCIe device tree nodes for the given platform.
+config SYS_FSL_SINGLE_SOURCE_CLK + bool + +config SYS_FSL_SRIO_LIODN + bool + +config SYS_FSL_TBCLK_DIV + int + default 32 if ARCH_P2041 || ARCH_P3041 + default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \ + ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \ + ARCH_T1024 || ARCH_T2080 + default 8 + help + Defines the core time base clock divider ratio compared to the system + clock. On most PQ3 devices this is 8, on newer QorIQ devices it can + be 16 or 32. The ratio varies from SoC to Soc. + +config SYS_FSL_USB1_PHY_ENABLE + bool + +config SYS_FSL_USB2_PHY_ENABLE + bool + +config SYS_FSL_USB_DUAL_PHY_ENABLE + bool + config SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up" depends on MPC85xx diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ba9736ebef45..a44bf2171a9d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -333,9 +333,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* * Get timebase clock frequency */ -#ifndef CONFIG_SYS_FSL_TBCLK_DIV -#define CONFIG_SYS_FSL_TBCLK_DIV 8 -#endif __weak unsigned long get_tbclk(void) { unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 21b35db08df1..bdd73389d902 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -31,10 +31,6 @@ ulong cpu_init_f(void) return 0; }
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV -#define CONFIG_SYS_FSL_TBCLK_DIV 8 -#endif - void udelay(unsigned long usec) { u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f972bee74708..d3d4e9c053f4 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -20,15 +20,12 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
/* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) @@ -65,7 +62,6 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ @@ -73,10 +69,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -87,10 +79,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -103,11 +91,9 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
@@ -118,10 +104,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131) @@ -135,7 +117,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240) -#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_ARCH_T4240 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 @@ -158,24 +139,17 @@ #define CONFIG_SYS_FM1_CLK 3 #define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_LIODN -#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) -#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 @@ -186,7 +160,6 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_DSP_CPUS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } @@ -195,7 +168,6 @@ #endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) -#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 @@ -206,17 +178,12 @@ #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 -#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024) -#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 @@ -228,17 +195,12 @@ #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 -#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 @@ -246,7 +208,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -256,9 +217,6 @@ #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 93e7dbe97661..73db3ca70216 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -838,6 +838,10 @@ config SYS_DPAA_QBMAN help QBman fixups to allow deep sleep in DPAA 1 SOCs
+config SYS_FSL_QMAN_V3 + bool # QMAN version 3 + depends on SYS_DPAA_QBMAN + config TSEC_ENET select PHYLIB bool "Enable Three-Speed Ethernet Controller" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index c3b97f48f0f2..a0f48f09a7f3 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -282,9 +282,15 @@ config EHCI_HCD_INIT_AFTER_RESET config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" select EHCI_HCD_INIT_AFTER_RESET + select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ + !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) ---help--- Enables support for the on-chip EHCI controller on FSL chips.
+config SYS_FSL_USB_INTERNAL_UTMI_PHY + bool + depends on USB_EHCI_FSL + config USB_EHCI_TXFIFO_THRESH hex depends on USB_EHCI_TEGRA diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index bc8aa3ce0549..42e507bac0bb 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -7,8 +7,6 @@ * P3041 DS board configuration file * */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - #define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_SRIO diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 6375c65d483b..fd558398e4a1 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -7,7 +7,6 @@ * P4080 DS board configuration file * Also supports P4040 DS */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index fb73f0b95390..c8fc879d2f88 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -7,9 +7,6 @@ * P5040 DS board configuration file * */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
On Sun, Jul 31, 2022 at 09:08:29PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_FSL_NGPIXIS CONFIG_SYS_FSL_QMAN_V3 CONFIG_SYS_FSL_RAID_ENGINE CONFIG_SYS_FSL_RMU CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRIO_LIODN CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_USB1_PHY_ENABLE CONFIG_SYS_FSL_USB2_PHY_ENABLE CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Sun, Jul 31, 2022 at 09:08:22PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
And we remove the entries from the README for a number of already converted items.
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
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Tom Rini