This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted.

Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the [ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 3 --- drivers/mtd/spi/spi_flash.c | 62 ++----------------------------------------- 2 files changed, 2 insertions(+), 63 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 007a5a085caf..7418c76b272c 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,7 +77,6 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 -#define CMD_WRITE_EVCR 0x61

/* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -91,7 +90,6 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 -#define CMD_READ_EVCR 0x65

/* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -106,7 +104,6 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) -#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 44d9e9ba0105..e52728da9a09 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif

-#ifdef CONFIG_SPI_FLASH_STMICRO -static int read_evcr(struct spi_flash *flash, u8 *evcr) -{ - int ret; - const u8 cmd = CMD_READ_EVCR; - - ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); - if (ret < 0) { - debug("SF: error reading EVCR\n"); - return ret; - } - - return 0; -} - -static int write_evcr(struct spi_flash *flash, u8 evcr) -{ - u8 cmd; - int ret; - - cmd = CMD_WRITE_EVCR; - ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); - if (ret < 0) { - debug("SF: error while writing EVCR register\n"); - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { @@ -895,34 +864,6 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif

-#ifdef CONFIG_SPI_FLASH_STMICRO -static int micron_quad_enable(struct spi_flash *flash) -{ - u8 qeb_status; - int ret; - - ret = read_evcr(flash, &qeb_status); - if (ret < 0) - return ret; - - if (!(qeb_status & STATUS_QEB_MICRON)) - return 0; - - ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); - if (ret < 0) - return ret; - - /* read EVCR and check it */ - ret = read_evcr(flash, &qeb_status); - if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { - printf("SF: Micron EVCR Quad bit not clear\n"); - return -EINVAL; - } - - return ret; -} -#endif - static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { @@ -937,7 +878,8 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - return micron_quad_enable(flash); + debug("SF: QEB is volatile for %02x flash\n", idcode0); + return 0; #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0);

Since spi_claim_bus() and spi_release_bus() are now called outside spi_flash_read_common(), this latest function is just a useless alias for spi_flash_cmd_read(). So we remove it.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 6 ------ drivers/mtd/spi/spi_flash.c | 30 +++++++++--------------------- 2 files changed, 9 insertions(+), 27 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index dd8152721fe1..96c9255cb03d 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -207,12 +207,6 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf);

-/* - * Same as spi_flash_cmd_read(). Used as common part of the ->read() operation. - */ -int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len); - /* Flash read operation, support all possible read commands */ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 740ecd44473a..b1ebc65f37d7 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -32,11 +32,12 @@ static void spi_flash_addr(u32 addr, u8 *cmd)

static int read_sr(struct spi_flash *flash, u8 *rs) { + struct spi_slave *spi = flash->spi; int ret; u8 cmd;

cmd = CMD_READ_STATUS; - ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); + ret = spi_flash_cmd_read(spi, &cmd, 1, rs, 1); if (ret < 0) { debug("SF: fail to read status register\n"); return ret; @@ -47,10 +48,11 @@ static int read_sr(struct spi_flash *flash, u8 *rs)

static int read_fsr(struct spi_flash *flash, u8 *fsr) { + struct spi_slave *spi = flash->spi; int ret; const u8 cmd = CMD_FLAG_STATUS;

- ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); + ret = spi_flash_cmd_read(spi, &cmd, 1, fsr, 1); if (ret < 0) { debug("SF: fail to read flag status register\n"); return ret; @@ -77,11 +79,12 @@ static int write_sr(struct spi_flash *flash, u8 ws) #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) static int read_cr(struct spi_flash *flash, u8 *rc) { + struct spi_slave *spi = flash->spi; int ret; u8 cmd;

cmd = CMD_READ_CONFIG; - ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); + ret = spi_flash_cmd_read(spi, &cmd, 1, rc, 1); if (ret < 0) { debug("SF: fail to read config register\n"); return ret; @@ -136,6 +139,7 @@ bar_end:

static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) { + struct spi_slave *spi = flash->spi; u8 curr_bank = 0; int ret;

@@ -152,8 +156,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) flash->bank_write_cmd = CMD_EXTNADDR_WREAR; }

- ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, - &curr_bank, 1); + ret = spi_flash_cmd_read(spi, &flash->bank_read_cmd, 1, &curr_bank, 1); if (ret) { debug("SF: fail to read bank addr register\n"); return ret; @@ -414,21 +417,6 @@ release: return ret; }

-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len) -{ - struct spi_slave *spi = flash->spi; - int ret; - - ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); - if (ret < 0) { - debug("SF: read cmd failed\n"); - return ret; - } - - return ret; -} - /* * TODO: remove the weak after all the other spi_flash_copy_mmap * implementations removed from drivers @@ -496,7 +484,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,

spi_flash_addr(read_addr, cmd);

- ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); + ret = spi_flash_cmd_read(spi, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); break;

This patch exports a new function so future drivers can use it.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 3 +++ drivers/mtd/spi/spi_flash.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 25fc5a112d92..e2a4449dbf40 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -190,6 +190,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); }

+/* Wait for Busy/Write in Progress flag to be cleared */ +int spi_flash_wait_ready(struct spi_flash *flash); + /* * Used for spi_flash register update operation * - spi_flash_cmd_write_enable diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index e43e74fd95cd..6f30ff6f8d7c 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -249,6 +249,11 @@ static int spi_flash_cmd_wait_ready(struct spi_flash *flash, return -ETIMEDOUT; }

+int spi_flash_wait_ready(struct spi_flash *flash) +{ + return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); +} + int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, size_t len, const void *buf) { @@ -267,7 +272,7 @@ int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, return ret; }

- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_wait_ready(flash); if (ret < 0) { debug("SF: write register timed out\n"); return ret;

This patch splits the generic algorithm to write data from the actual implementation which is specific to each UCLASS_SPI_FLASH driver.

For now, the sf_probe.c driver is the only instance of this driver class using this generic algorithm but other driver instances are to come. This patch will ease their implementation.

Please note that the sf_dataflash.c driver has its own implementation of the .write hook (of the struct dm_spi_flash_ops) which is not compatible with this generic algorithm. This is why we can't simply change the prototype of .write hook and create a spi_flash_write() wrapper.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 5 +++++ drivers/mtd/spi/spi_flash.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 3c6bac3464f8..592c23cd4ce1 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -214,6 +214,11 @@ int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, size_t len, int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf);

+typedef int (*spi_flash_write_fn)(struct spi_flash *, u32, size_t, + const void *); +int spi_flash_write_alg(struct spi_flash *flash, u32 offset, size_t len, + const void *buf, spi_flash_write_fn write_fn); + /* Flash read operation, support all possible read commands */ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 20b8c31c09e0..3c8224c2b084 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -366,14 +366,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) return spi_flash_erase_alg(flash, offset, len, spi_flash_erase_impl); }

-int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, - size_t len, const void *buf) +int spi_flash_write_alg(struct spi_flash *flash, u32 offset, size_t len, + const void *buf, spi_flash_write_fn write_fn) { struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1;

page_size = flash->page_size; @@ -393,7 +392,6 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, } }

- cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { write_addr = offset;

@@ -419,13 +417,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, break; }

- spi_flash_addr(write_addr, cmd); - - debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + debug("SF: 0x%p => cmd = { 0x%02x 0x%06x } chunk_len = %zu\n", + buf + actual, flash->write_cmd, write_addr, chunk_len);

- ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), - buf + actual, chunk_len); + ret = write_fn(flash, write_addr, chunk_len, buf + actual); if (ret < 0) { debug("SF: write failed\n"); break; @@ -446,6 +441,25 @@ release: return ret; }

+static int spi_flash_write_impl(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + struct spi_slave *spi = flash->spi; + u8 cmd[SPI_FLASH_CMD_LEN]; + size_t cmdsz = sizeof(cmd); + + cmd[0] = flash->write_cmd; + spi_flash_addr(offset, cmd); + return spi_flash_cmd_write(spi, cmd, cmdsz, buf, len); +} + +int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return spi_flash_write_alg(flash, offset, len, buf, + spi_flash_write_impl); +} + /* * TODO: remove the weak after all the other spi_flash_copy_mmap * implementations removed from drivers

This patch finalizes the split of internal register and memory data SPI commands. Indeed some (Q)SPI controllers such as the Atmel QSPI controller need to make the difference between register read/write SPI commands and data read/write/erase SPI commands.

It follows an interface close to the one used by the spi-nor.c driver in Linux: - read_reg: read out the register - write_reg: write data to the register - read: read data from the SPI flash - write: write data into the SPI flash - erase: erase sectors of the SPI flash

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf-uclass.c | 11 +++++++ drivers/mtd/spi/sf_internal.h | 13 ++++++-- drivers/mtd/spi/sf_probe.c | 18 +++++++++++ drivers/mtd/spi/spi_flash.c | 70 ++++++++++++++++++++++++------------------- include/spi_flash.h | 58 +++++++++++++++++++++++++++++++++++ 5 files changed, 137 insertions(+), 33 deletions(-)

diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 19de964e6121..ebae9b1edb15 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -13,6 +13,17 @@

DECLARE_GLOBAL_DATA_PTR;

+int spi_flash_read_reg_dm(struct udevice *dev, u8 opcode, size_t len, void *buf) +{ + return sf_get_ops(dev)->read_reg(dev, opcode, len, buf); +} + +int spi_flash_write_reg_dm(struct udevice *dev, u8 opcode, size_t len, + const void *buf) +{ + return sf_get_ops(dev)->write_reg(dev, opcode, len, buf); +} + int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) { return sf_get_ops(dev)->read(dev, offset, len, buf); diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 569863a31684..15a5fa9c2afd 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -12,6 +12,7 @@

#include <linux/types.h> #include <linux/compiler.h> +#include <spi_flash.h>

/* Dual SPI flash memories - see SPI_COMM_DUAL_... */ enum spi_dual_flash { @@ -185,13 +186,13 @@ int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); /* Enable writing on the SPI flash */ static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) { - return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + return spi_flash_write_reg(flash, CMD_WRITE_ENABLE, 0, NULL); }

/* Disable writing on the SPI flash */ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) { - return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); + return spi_flash_write_reg(flash, CMD_WRITE_DISABLE, 0, NULL); }

/* Wait for Busy/Write in Progress flag to be cleared */ @@ -206,6 +207,10 @@ int spi_flash_wait_ready(struct spi_flash *flash); int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, size_t len, const void *buf);

+/* Flash write register operation */ +int spi_flash_cmd_write_reg_ops(struct spi_flash *flash, u8 opcode, size_t len, + const void *buf); + /* * Flash write operation, support all possible write commands. * Write the requested data out breaking it up into multiple write @@ -219,6 +224,10 @@ typedef int (*spi_flash_write_fn)(struct spi_flash *, u32, size_t, int spi_flash_write_alg(struct spi_flash *flash, u32 offset, size_t len, const void *buf, spi_flash_write_fn write_fn);

+/* Flash read register operation */ +int spi_flash_cmd_read_reg_ops(struct spi_flash *flash, u8 opcode, size_t len, + void *buf); + /* Flash read operation, support all possible read commands */ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7b296378d2be..fbd7d4740b51 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -111,6 +111,22 @@ void spi_flash_free(struct spi_flash *flash)

#else /* defined CONFIG_DM_SPI_FLASH */

+static int spi_flash_std_read_reg(struct udevice *dev, u8 opcode, size_t len, + void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_cmd_read_reg_ops(flash, opcode, len, buf); +} + +static int spi_flash_std_write_reg(struct udevice *dev, u8 opcode, size_t len, + const void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_cmd_write_reg_ops(flash, opcode, len, buf); +} + static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len, void *buf) { @@ -157,6 +173,8 @@ static int spi_flash_std_probe(struct udevice *dev) }

static const struct dm_spi_flash_ops spi_flash_std_ops = { + .read_reg = spi_flash_std_read_reg, + .write_reg = spi_flash_std_write_reg, .read = spi_flash_std_read, .write = spi_flash_std_write, .erase = spi_flash_std_erase, diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 4be99ea0b424..4f269eacc591 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -32,12 +32,9 @@ static void spi_flash_addr(u32 addr, u8 *cmd)

static int read_sr(struct spi_flash *flash, u8 *rs) { - struct spi_slave *spi = flash->spi; int ret; - u8 cmd;

- cmd = CMD_READ_STATUS; - ret = spi_flash_cmd_read(spi, &cmd, 1, rs, 1); + ret = spi_flash_read_reg(flash, CMD_READ_STATUS, 1, rs); if (ret < 0) { debug("SF: fail to read status register\n"); return ret; @@ -48,11 +45,9 @@ static int read_sr(struct spi_flash *flash, u8 *rs)

static int read_fsr(struct spi_flash *flash, u8 *fsr) { - struct spi_slave *spi = flash->spi; int ret; - const u8 cmd = CMD_FLAG_STATUS;

- ret = spi_flash_cmd_read(spi, &cmd, 1, fsr, 1); + ret = spi_flash_read_reg(flash, CMD_FLAG_STATUS, 1, fsr); if (ret < 0) { debug("SF: fail to read flag status register\n"); return ret; @@ -77,12 +72,9 @@ static int write_sr(struct spi_flash *flash, u8 ws) #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) static int read_cr(struct spi_flash *flash, u8 *rc) { - struct spi_slave *spi = flash->spi; int ret; - u8 cmd;

- cmd = CMD_READ_CONFIG; - ret = spi_flash_cmd_read(spi, &cmd, 1, rc, 1); + ret = spi_flash_read_reg(flash, CMD_READ_CONFIG, 1, rc); if (ret < 0) { debug("SF: fail to read config register\n"); return ret; @@ -134,7 +126,6 @@ bar_end:

static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) { - struct spi_slave *spi = flash->spi; u8 curr_bank = 0; int ret;

@@ -151,7 +142,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) flash->bank_write_cmd = CMD_EXTNADDR_WREAR; }

- ret = spi_flash_cmd_read(spi, &flash->bank_read_cmd, 1, &curr_bank, 1); + ret = spi_flash_read_reg(flash, flash->bank_read_cmd, &curr_bank, 1); if (ret) { debug("SF: fail to read bank addr register\n"); return ret; @@ -257,7 +248,6 @@ int spi_flash_wait_ready(struct spi_flash *flash) int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, size_t len, const void *buf) { - struct spi_slave *spi = flash->spi; int ret;

ret = spi_flash_cmd_write_enable(flash); @@ -266,7 +256,7 @@ int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, return ret; }

- ret = spi_flash_cmd_write(spi, &opcode, 1, buf, len); + ret = spi_flash_write_reg(flash, opcode, len, buf); if (ret < 0) { debug("SF: write cmd failed\n"); return ret; @@ -281,6 +271,14 @@ int spi_flash_update_reg(struct spi_flash *flash, u8 opcode, return 0; }

+int spi_flash_cmd_write_reg_ops(struct spi_flash *flash, u8 opcode, size_t len, + const void *buf) +{ + struct spi_slave *spi = flash->spi; + + return spi_flash_cmd_write(spi, &opcode, 1, buf, len); +} + int spi_flash_erase_alg(struct spi_flash *flash, u32 offset, size_t len, spi_flash_erase_fn erase_fn) { @@ -460,6 +458,14 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, spi_flash_write_impl); }

+int spi_flash_cmd_read_reg_ops(struct spi_flash *flash, u8 opcode, + size_t len, void *buf) +{ + struct spi_slave *spi = flash->spi; + + return spi_flash_cmd_read(spi, &opcode, 1, buf, len); +} + /* * TODO: remove the weak after all the other spi_flash_copy_mmap * implementations removed from drivers @@ -982,8 +988,25 @@ int spi_flash_scan(struct spi_flash *flash) CMD_READ_DUAL_IO_FAST, CMD_READ_QUAD_IO_FAST };

+ /* Assign spi_flash ops */ +#ifndef CONFIG_DM_SPI_FLASH + flash->read_reg = spi_flash_cmd_read_reg_ops; + flash->write_reg = spi_flash_cmd_write_reg_ops; + flash->write = spi_flash_cmd_write_ops; +#if defined(CONFIG_SPI_FLASH_SST) + if (flash->flags & SNOR_F_SST_WR) { + if (spi->mode & SPI_TX_BYTE) + flash->write = sst_write_bp; + else + flash->write = sst_write_wp; + } +#endif + flash->erase = spi_flash_cmd_erase_ops; + flash->read = spi_flash_cmd_read_ops; +#endif + /* Read the ID codes */ - ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + ret = spi_flash_read_reg(flash, CMD_READ_ID, sizeof(idcode), idcode); if (ret) { printf("SF: Failed to get idcodes\n"); return ret; @@ -1032,21 +1055,6 @@ int spi_flash_scan(struct spi_flash *flash) if (params->flags & SST_WR) flash->flags |= SNOR_F_SST_WR;

- /* Assign spi_flash ops */ -#ifndef CONFIG_DM_SPI_FLASH - flash->write = spi_flash_cmd_write_ops; -#if defined(CONFIG_SPI_FLASH_SST) - if (flash->flags & SNOR_F_SST_WR) { - if (spi->mode & SPI_TX_BYTE) - flash->write = sst_write_bp; - else - flash->write = sst_write_wp; - } -#endif - flash->erase = spi_flash_cmd_erase_ops; - flash->read = spi_flash_cmd_read_ops; -#endif - /* lock hooks are flash specific - assign them based on idcode0 */ switch (idcode[0]) { #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) diff --git a/include/spi_flash.h b/include/spi_flash.h index d0ce9e721ad0..31d11e55571d 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -52,6 +52,9 @@ struct spi_slave; * @flash_lock: lock a region of the SPI Flash * @flash_unlock: unlock a region of the SPI Flash * @flash_is_locked: check if a region of the SPI Flash is completely locked + * @read_reg: Flash read_reg ops: Send cmd to read len bytes into buf + * @write_reg: Flash write_reg ops: Send cmd to write len bytes from + * buf * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read * @write: Flash write ops: Write len bytes from buf into offset @@ -101,6 +104,10 @@ struct spi_flash { * if required, perhaps with a way of scanning through the list to * find the driver that matches the device. */ + int (*read_reg)(struct spi_flash *flash, u8 opcode, size_t len, + void *buf); + int (*write_reg)(struct spi_flash *flash, u8 opcode, size_t len, + const void *buf); int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); int (*write)(struct spi_flash *flash, u32 offset, size_t len, const void *buf); @@ -109,6 +116,9 @@ struct spi_flash { };

struct dm_spi_flash_ops { + int (*read_reg)(struct udevice *dev, u8 opcode, size_t len, void *buf); + int (*write_reg)(struct udevice *dev, u8 opcode, size_t len, + const void *buf); int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf); int (*write)(struct udevice *dev, u32 offset, size_t len, const void *buf); @@ -120,6 +130,30 @@ struct dm_spi_flash_ops {

#ifdef CONFIG_DM_SPI_FLASH /** + * spi_flash_read_reg_dm() - Send register command and read data result + * + * @dev: SPI flash device + * @opcode: Register command op code + * @len: Number of bytes to read as register command output + * @buf: Buffer to fill with the register command output + * @return 0 if OK, -ve on error + */ +int spi_flash_read_reg_dm(struct udevice *dev, u8 opcode, size_t len, + void *buf); + +/** + * spi_flash_write_reg_dm() - Send register command with data + * + * @dev: SPI flash device + * @opcode: Register command op code + * @len: Number of bytes to write as register command input + * @buf: Buffer filled with the register command input + * @return 0 if OK, -ve on error + */ +int spi_flash_write_reg_dm(struct udevice *dev, u8 opcode, size_t len, + const void *buf); + +/** * spi_flash_read_dm() - Read data from SPI flash * * @dev: SPI flash device @@ -165,6 +199,18 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, /* Compatibility function - this is the old U-Boot API */ void spi_flash_free(struct spi_flash *flash);

+static inline int spi_flash_read_reg(struct spi_flash *flash, u8 opcode, + size_t len, void *buf) +{ + return spi_flash_read_reg_dm(flash->dev, opcode, len, buf); +} + +static inline int spi_flash_write_reg(struct spi_flash *flash, u8 opcode, + size_t len, const void *buf) +{ + return spi_flash_write_reg_dm(flash->dev, opcode, len, buf); +} + static inline int spi_flash_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) { @@ -208,6 +254,18 @@ struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,

void spi_flash_free(struct spi_flash *flash);

+static inline int spi_flash_read_reg(struct spi_flash *flash, u8 opcode, + size_t len, void *buf) +{ + return flash->read_reg(flash, opcode, len, buf); +} + +static inline int spi_flash_write_reg(struct spi_flash *flash, u8 opcode, + size_t len, const void *buf) +{ + return flash->write_reg(flash, opcode, len, buf); +} + static inline int spi_flash_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) {

It looks odd to compute a logical AND between the e_rd_cmd field of struct spi_flash_params and the mode_rx field of struct spi_slave.

Indeed, these two fields don't use the same range of values. mode_rx is limited to SPI_RX_{SLOW, FAST, DUAL, QUAD}. Even completed with the SPI_TX_{DUAL, QUAD} flags from the mode field, this is not enough to find out whether the SPI controller driver supports Fast Read 4-4-4 (Micron, Macronix, Winbond) commands. With only the SPI_RX_QUAD and the SPI_TX_QUAD, how to make the difference between Fast Read 1-4-4 and Fast Read 4-4-4 ?

On the other hand, the e_rd_cmd field already provides a more accurate knowledge of the Fast Read commands supported by the SPI flash memory.

Then this patch provides a safe convertion from mode_rx + mode values into e_rd_cmd values to be used by the sf_probe.c driver: this driver never try using the Fast Read 4-4-4 command. Other drivers will provide an exhaustive list of supported Fast Read commands.

Hence a more accurate op code is chosen according to both the SPI flash memory and the SPI controller capabilities.

Please note that we cannot simply extend the SPI_TX_* and SPI_RX_* flags of the struct spi_slave since they are set according DT properties shared with Linux: spi-tx-bus-width and spi-rx-bus-width.

These two DT properties don't allow us to make the difference between the SPI 1-4-4 and SPI 4-4-4 protocols.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 14 +++++++++++--- drivers/mtd/spi/sf_params.c | 32 ++++++++++++++++---------------- drivers/mtd/spi/sf_probe.c | 19 ++++++++++++++++++- drivers/mtd/spi/spi_flash.c | 9 ++++++--- 4 files changed, 51 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index c5966fb37ac8..8b8521369e4e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -29,12 +29,19 @@ enum spi_read_cmds { QUAD_OUTPUT_FAST = BIT(3), DUAL_IO_FAST = BIT(4), QUAD_IO_FAST = BIT(5), + DUAL_CMD_FAST = BIT(6), + QUAD_CMD_FAST = BIT(7), };

/* Normal - Extended - Full command set */ #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) -#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) -#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) +#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST) +#define RD_DUAL (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) +#define RD_DCMD (RD_DUAL | DUAL_CMD_FAST) +#define RD_QUAD (RD_NORM | QUAD_OUTPUT_FAST | QUAD_IO_FAST) +#define RD_QCMD (RD_QUAD | QUAD_CMD_FAST) +#define RD_FULL (RD_DUAL | RD_QUAD) +#define RD_FCMD (RD_DCMD | RD_QCMD)

/* sf param flags */ enum { @@ -240,6 +247,7 @@ void spi_flash_mtd_unregister(void); /** * spi_flash_scan - scan the SPI FLASH * @flash: the spi flash structure + * @e_rd_cmd: Enum list for read commands supported by the SPI controller * * The drivers can use this fuction to scan the SPI FLASH. * In the scanning, it will try to get all the necessary information to @@ -247,6 +255,6 @@ void spi_flash_mtd_unregister(void); * * Return: 0 for success, others for failure. */ -int spi_flash_scan(struct spi_flash *flash); +int spi_flash_scan(struct spi_flash *flash, u8 e_rd_cmd);

#endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 4f37e33eb068..d3103dbc8742 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -47,10 +47,10 @@ const struct spi_flash_params spi_flash_params_table[] = { {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_QCMD, WR_QPP}, + {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_QCMD, WR_QPP}, + {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_QCMD, WR_QPP}, + {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_QCMD, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, @@ -83,18 +83,18 @@ const struct spi_flash_params spi_flash_params_table[] = { {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FCMD, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FCMD, WR_QPP}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FCMD, WR_QPP | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FCMD, WR_QPP | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FCMD, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FCMD, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FCMD, WR_QPP | E_FSR | SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 837535fdb7a5..8a0345bc1994 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -26,6 +26,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash) { struct spi_slave *spi = flash->spi; + u8 mode_rx, e_rd_cmd; int ret;

/* Setup spi_slave */ @@ -34,6 +35,22 @@ static int spi_flash_probe_slave(struct spi_flash *flash) return -ENODEV; }

+ /* Convert SPI mode_rx and mode to SPI flash read commands */ + mode_rx = spi->mode_rx; + if (mode_rx & SPI_RX_QUAD) { + e_rd_cmd = RD_NORM | QUAD_OUTPUT_FAST; + if (spi->mode & SPI_TX_QUAD) + e_rd_cmd |= QUAD_IO_FAST; + } else if (mode_rx & SPI_RX_DUAL) { + e_rd_cmd = RD_NORM | DUAL_OUTPUT_FAST; + if (spi->mode & SPI_TX_DUAL) + e_rd_cmd |= DUAL_IO_FAST; + } else if ((mode_rx & (SPI_RX_SLOW | SPI_RX_FAST)) == SPI_RX_SLOW) { + e_rd_cmd = ARRAY_SLOW; + } else { + e_rd_cmd = RD_NORM; + } + /* Claim spi bus */ ret = spi_claim_bus(spi); if (ret) { @@ -41,7 +58,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash) return ret; }

- ret = spi_flash_scan(flash); + ret = spi_flash_scan(flash, e_rd_cmd); if (ret) goto err_read_id;

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 7f5341a87c07..5ba148bd3626 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -987,7 +987,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) } #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */

-int spi_flash_scan(struct spi_flash *flash) +int spi_flash_scan(struct spi_flash *flash, u8 e_rd_cmd) { struct spi_slave *spi = flash->spi; const struct spi_flash_params *params; @@ -1000,7 +1000,10 @@ int spi_flash_scan(struct spi_flash *flash) CMD_READ_DUAL_OUTPUT_FAST, CMD_READ_QUAD_OUTPUT_FAST, CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_IO_FAST }; + CMD_READ_QUAD_IO_FAST, + CMD_READ_DUAL_IO_FAST, /* same op code as for DUAL_IO_FAST */ + CMD_READ_QUAD_IO_FAST, /* same op code as for QUAD_IO_FAST */ + };

/* Assign spi_flash ops */ #ifndef CONFIG_DM_SPI_FLASH @@ -1115,7 +1118,7 @@ int spi_flash_scan(struct spi_flash *flash) flash->sector_size = flash->erase_size;

/* Look for the fastest read cmd */ - cmd = fls(params->e_rd_cmd & spi->mode_rx); + cmd = fls(params->e_rd_cmd & e_rd_cmd); if (cmd) { cmd = spi_read_cmds_array[cmd - 1]; flash->read_cmd = cmd;

This patch adds a helper function to ease the conversion between a number of dummy clock cycles and number of bytes.

Actually this number of bytes depends on both the number of dummy clock cycles and SPI protocol used by (Fast) Read commands.

This new function is exported so it can be used by other drivers.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/sf_internal.h | 6 ++++++ drivers/mtd/spi/spi_flash.c | 11 +++++++++++ 2 files changed, 17 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 26d359707d5b..86a0276f8518 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -240,6 +240,12 @@ typedef int (*spi_flash_read_fn)(struct spi_flash *, u32, size_t, void *); int spi_flash_read_alg(struct spi_flash *flash, u32 offset, size_t len, void *data, spi_flash_read_fn read_fn);

+/* + * Helper function to compute the number of dummy bytes from both the number + * of dummy cycles and the SPI protocol used for (Fast) Read operations. + */ +int spi_flash_set_dummy_byte(struct spi_flash *flash, u8 num_dummy_cycles); + #ifdef CONFIG_SPI_FLASH_MTD int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5d641bbb8301..01a073d81eb9 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -882,6 +882,17 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) } #endif

+int spi_flash_set_dummy_byte(struct spi_flash *flash, u8 num_dummy_cycles) +{ + u8 dummy_bits = num_dummy_cycles; + + dummy_bits *= SPI_FLASH_PROTO_ADR_FROM_PROTO(flash->read_proto); + if (dummy_bits & 0x7) + return -EINVAL; + + flash->dummy_byte = dummy_bits >> 3; + return 0; +}

#ifdef CONFIG_SPI_FLASH_MACRONIX static int macronix_quad_enable(struct spi_flash *flash)

This patch provides support of Micron QSPI memories.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/sf_internal.h | 24 +++++ drivers/mtd/spi/sf_micron.c | 222 ++++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash.c | 13 +-- 4 files changed, 251 insertions(+), 9 deletions(-) create mode 100644 drivers/mtd/spi/sf_micron.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index c665836f9560..90266d619ddf 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif

obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o +obj-$(CONFIG_SPI_FLASH_STMICRO) += sf_micron.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index a98c011218ce..afee8b69ca6b 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -142,6 +142,24 @@ enum spi_nor_option_flags { # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ #endif

+/* Micron specific */ +#ifdef CONFIG_SPI_FLASH_STMICRO + +/* Volatile Configuration Register (VCR) */ +#define CMD_MICRON_WR_VCR 0x81 +#define CMD_MICRON_RD_VCR 0x85 +#define MICRON_VCR_XIP BIT(3) +#define MICRON_VCR_DUMMIES 0xf0 +#define MICRON_VCR_DUMMIES_(x) (((x) << 4) & MICRON_VCR_DUMMIES) + +/* Enhanced Volatile Configuraiton Register (EVCR) */ +#define CMD_MICRON_WR_EVCR 0x61 +#define CMD_MICRON_RD_EVCR 0x65 +#define MICRON_EVCR_QUAD_DIS BIT(7) +#define MICRON_EVCR_DUAL_DIS BIT(6) +#endif + + /** * struct spi_flash_params - SPI/QSPI flash device params structure * @@ -264,6 +282,12 @@ int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); #endif

+#ifdef CONFIG_SPI_FLASH_STMICRO +int spi_flash_setup_micron(struct spi_flash *flash, + const struct spi_flash_params *params, + int best_match); +#endif + /** * spi_flash_scan - scan the SPI FLASH * @flash: the spi flash structure diff --git a/drivers/mtd/spi/sf_micron.c b/drivers/mtd/spi/sf_micron.c new file mode 100644 index 000000000000..b399b6ff52fe --- /dev/null +++ b/drivers/mtd/spi/sf_micron.c @@ -0,0 +1,222 @@ +/* + * Micron SPI NOR flash support + * + * Copyright (C) 2016 Cyrille Pitchen cyrille.pitchen@atmel.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spi.h> +#include <spi_flash.h> + +#include "sf_internal.h" + +static int spi_flash_micron_set_dummy_cycles(struct spi_flash *flash, + u8 num_dummy_cycles) +{ + u8 vcr, mask, value; + int ret; + + /* Set the number of dummy cycles and disable XIP */ + mask = (MICRON_VCR_DUMMIES | MICRON_VCR_XIP); + value = MICRON_VCR_DUMMIES_(num_dummy_cycles) | MICRON_VCR_XIP; + + /* Check current VCR value */ + ret = spi_flash_read_reg(flash, CMD_MICRON_RD_VCR, 1, &vcr); + if (ret) + goto end; + + if ((vcr & mask) == value) + goto end; + + /* VCR update is needed */ + vcr = (vcr & ~mask) | value; + ret = spi_flash_update_reg(flash, CMD_MICRON_WR_VCR, 1, &vcr); + if (ret) + goto end; + + /* Verify update */ + ret = spi_flash_read_reg(flash, CMD_MICRON_RD_VCR, 1, &vcr); + if (ret) + goto end; + + if ((vcr & mask) != value) + ret = -EIO; + +end: + if (ret) + printf("SF: failed to set the dummy cycles on Micron memory!\n"); + + return ret; +} + +static int spi_flash_micron_set_protocol(struct spi_flash *flash, + enum spi_flash_protocol proto, + u8 mask, u8 value) +{ + u8 evcr; + int ret; + + /* Check current EVCR value */ + ret = spi_flash_read_reg(flash, CMD_MICRON_RD_EVCR, 1, &evcr); + if (ret) + goto end; + + if ((evcr & mask) == value) + goto end; + + /* EVCR update is needed */ + ret = spi_flash_cmd_write_enable(flash); + if (ret) + goto end; + + evcr = (evcr & ~mask) | value; + ret = spi_flash_write_reg(flash, CMD_MICRON_WR_EVCR, 1, &evcr); + if (ret) + goto end; + + /* + * Don't forget to update the protocol HERE otherwise next commands + * will fail. + */ + flash->reg_proto = proto; + + /* Wait for ready status */ + ret = spi_flash_wait_ready(flash); + if (ret) + goto end; + + /* Verify update */ + ret = spi_flash_read_reg(flash, CMD_MICRON_RD_EVCR, 1, &evcr); + if (ret) + goto end; + + if ((evcr & mask) != value) + ret = -EIO; + +end: + if (ret) { + printf("SF: failed to set I/O mode on Micron memory!\n"); + return ret; + } + + flash->read_proto = proto; + flash->write_proto = proto; + flash->erase_proto = proto; + return 0; +} + +static inline int spi_flash_micron_set_ext_spi_mode(struct spi_flash *flash) +{ + enum spi_flash_protocol proto = SPI_FLASH_PROTO_1_1_1; + u8 mask = (MICRON_EVCR_QUAD_DIS | MICRON_EVCR_DUAL_DIS); + u8 value = mask; + + return spi_flash_micron_set_protocol(flash, proto, mask, value); +} + +static inline int spi_flash_micron_set_dual_mode(struct spi_flash *flash) +{ + enum spi_flash_protocol proto = SPI_FLASH_PROTO_2_2_2; + u8 mask = (MICRON_EVCR_QUAD_DIS | MICRON_EVCR_DUAL_DIS); + u8 value = MICRON_EVCR_QUAD_DIS; + + return spi_flash_micron_set_protocol(flash, proto, mask, value); +} + +static inline int spi_flash_micron_set_quad_mode(struct spi_flash *flash) +{ + enum spi_flash_protocol proto = SPI_FLASH_PROTO_4_4_4; + u8 mask = MICRON_EVCR_QUAD_DIS; + u8 value = 0; + + return spi_flash_micron_set_protocol(flash, proto, mask, value); +} + +int spi_flash_setup_micron(struct spi_flash *flash, + const struct spi_flash_params *params, + int best_match) +{ + u16 read_cmd = best_match ? (1 << (best_match - 1)) : ARRAY_FAST; + u8 dummy_cycles = (read_cmd == ARRAY_SLOW) ? 0 : 8; + int ret = 0; + + /* Configure (Fast) Read operations */ + switch (read_cmd) { + case QUAD_CMD_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_4_4_4) + ret = spi_flash_micron_set_quad_mode(flash); + flash->read_cmd = CMD_READ_QUAD_IO_FAST; + break; + + case QUAD_IO_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_1_1_1) + ret = spi_flash_micron_set_ext_spi_mode(flash); + flash->read_proto = SPI_FLASH_PROTO_1_4_4; + flash->read_cmd = CMD_READ_QUAD_IO_FAST; + break; + + case QUAD_OUTPUT_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_1_1_1) + ret = spi_flash_micron_set_ext_spi_mode(flash); + flash->read_proto = SPI_FLASH_PROTO_1_1_4; + flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; + break; + + case DUAL_CMD_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_2_2_2) + ret = spi_flash_micron_set_dual_mode(flash); + flash->read_cmd = CMD_READ_DUAL_IO_FAST; + break; + + case DUAL_IO_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_1_1_1) + ret = spi_flash_micron_set_ext_spi_mode(flash); + flash->read_proto = SPI_FLASH_PROTO_1_2_2; + flash->read_cmd = CMD_READ_DUAL_IO_FAST; + break; + + case DUAL_OUTPUT_FAST: + if (flash->reg_proto != SPI_FLASH_PROTO_1_1_1) + ret = spi_flash_micron_set_ext_spi_mode(flash); + flash->read_proto = SPI_FLASH_PROTO_1_1_2; + flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; + break; + + case ARRAY_FAST: + flash->read_proto = SPI_FLASH_PROTO_1_1_1; + flash->read_cmd = CMD_READ_ARRAY_FAST; + break; + + case ARRAY_SLOW: + flash->read_proto = SPI_FLASH_PROTO_1_1_1; + flash->read_cmd = CMD_READ_ARRAY_SLOW; + break; + + default: + return -EINVAL; + } + + if (ret) + return ret; + + /* Configure Page Program operations */ + if (flash->write_proto == SPI_FLASH_PROTO_4_4_4 || + flash->write_proto == SPI_FLASH_PROTO_2_2_2) { + flash->write_cmd = CMD_PAGE_PROGRAM; + } else if ((flash->spi->mode & SPI_TX_QUAD) && + (params->flags & WR_QPP)) { + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + flash->write_proto = SPI_FLASH_PROTO_1_1_4; + } else { + flash->write_cmd = CMD_PAGE_PROGRAM; + flash->write_proto = SPI_FLASH_PROTO_1_1_1; + } + + /* Set number of dummy cycles for Fast Read operations */ + if (params->e_rd_cmd & (QUAD_CMD_FAST | DUAL_CMD_FAST)) + ret = spi_flash_micron_set_dummy_cycles(flash, dummy_cycles); + return ret ? : spi_flash_set_dummy_byte(flash, dummy_cycles); +} diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 50250491d228..922afc811a0b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1022,11 +1022,6 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) case SPI_FLASH_CFI_MFR_WINBOND: return spansion_quad_enable(flash); #endif -#ifdef CONFIG_SPI_FLASH_STMICRO - case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; -#endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); return -1; @@ -1113,10 +1108,10 @@ static int spi_flash_setup(struct spi_flash *flash, * manufacturer. */ switch (params->jedec >> 16) { - /* - * TODO: Manufacturer dedicated setup will be added HERE by - * further patches. - */ +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + return spi_flash_setup_micron(flash, params, match); +#endif

default: return spi_flash_setup_deprecated(flash, params, match);

This patch adds support of the Atmel QSPI controller.

Signed-off-by: Cyrille Pitchen cyrille.pitchen@atmel.com --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/atmel_qspi_flash.c | 432 +++++++++++++++++++++++++++++++++++++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/atmel_qspi.c | 150 +++++++++++++ drivers/spi/atmel_qspi.h | 145 +++++++++++++ 6 files changed, 738 insertions(+) create mode 100644 drivers/mtd/spi/atmel_qspi_flash.c create mode 100644 drivers/spi/atmel_qspi.c create mode 100644 drivers/spi/atmel_qspi.h

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 90266d619ddf..207e1d556f3f 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SPI_FLASH_STMICRO) += sf_micron.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o +obj-$(CONFIG_ATMEL_QSPI) += atmel_qspi_flash.o diff --git a/drivers/mtd/spi/atmel_qspi_flash.c b/drivers/mtd/spi/atmel_qspi_flash.c new file mode 100644 index 000000000000..97f85ae2e30c --- /dev/null +++ b/drivers/mtd/spi/atmel_qspi_flash.c @@ -0,0 +1,432 @@ +#include <common.h> +#include <errno.h> +#include <spi.h> +#include <spi_flash.h> + +#include "sf_internal.h" +#include "../../spi/atmel_qspi.h" + +struct atmel_qspi_command { + union { + struct { + unsigned int instruction:1; + unsigned int address:3; + unsigned int mode:1; + unsigned int dummy:1; + unsigned int data:1; + unsigned int reserved:25; + } bits; + unsigned int word; + } enable; + unsigned char instruction; + unsigned char mode; + unsigned char num_mode_cycles; + unsigned char num_dummy_cycles; + unsigned int address; + + size_t buf_len; + const void *tx_buf; + void *rx_buf; + + enum spi_flash_protocol protocol; + u32 ifr_tfrtype; +}; + + +static void atmel_qspi_memcpy_fromio(void *dst, unsigned long src, size_t len) +{ + u8 *d = (u8 *)dst; + + while (len--) { + *d++ = readb(src); + src++; + } +} + +static void atmel_qspi_memcpy_toio(unsigned long dst, const void *src, + size_t len) +{ + const u8 *s = (const u8 *)src; + + while (len--) { + writeb(*s, dst); + dst++; + s++; + } +} + +static int atmel_qpsi_set_ifr_width(enum spi_flash_protocol proto, u32 *ifr) +{ + u32 ifr_width; + + switch (proto) { + case SPI_FLASH_PROTO_1_1_1: + ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI; + break; + + case SPI_FLASH_PROTO_1_1_2: + ifr_width = QSPI_IFR_WIDTH_DUAL_OUTPUT; + break; + + case SPI_FLASH_PROTO_1_2_2: + ifr_width = QSPI_IFR_WIDTH_DUAL_IO; + break; + + case SPI_FLASH_PROTO_2_2_2: + ifr_width = QSPI_IFR_WIDTH_DUAL_CMD; + break; + + case SPI_FLASH_PROTO_1_1_4: + ifr_width = QSPI_IFR_WIDTH_QUAD_OUTPUT; + break; + + case SPI_FLASH_PROTO_1_4_4: + ifr_width = QSPI_IFR_WIDTH_QUAD_IO; + break; + + case SPI_FLASH_PROTO_4_4_4: + ifr_width = QSPI_IFR_WIDTH_QUAD_CMD; + break; + + default: + return -EINVAL; + } + + *ifr = (*ifr & ~QSPI_IFR_WIDTH) | ifr_width; + return 0; +} + +static int atmel_qspi_send_command(struct atmel_qspi_priv *aq, + const struct atmel_qspi_command *cmd) +{ + unsigned int iar, icr, ifr; + unsigned int offset; + unsigned int imr, sr; + unsigned long memaddr; + int err; + + iar = 0; + icr = 0; + ifr = cmd->ifr_tfrtype; + + err = atmel_qpsi_set_ifr_width(cmd->protocol, &ifr); + if (err) + return err; + + /* Compute instruction parameters */ + if (cmd->enable.bits.instruction) { + icr |= QSPI_ICR_INST_(cmd->instruction); + ifr |= QSPI_IFR_INSTEN; + } + + /* Compute address parameters. */ + switch (cmd->enable.bits.address) { + case 4: + ifr |= QSPI_IFR_ADDRL_32_BIT; + //break; /* fall through the 24bit (3 byte) address case */ + case 3: + iar = (cmd->enable.bits.data) ? 0 : cmd->address; + ifr |= QSPI_IFR_ADDREN; + offset = cmd->address; + break; + case 0: + offset = 0; + break; + default: + return -EINVAL; + } + + /* Compute option parameters. */ + if (cmd->enable.bits.mode && cmd->num_mode_cycles) { + unsigned int mode_cycle_bits, mode_bits; + + icr |= QSPI_ICR_OPT_(cmd->mode); + ifr |= QSPI_IFR_OPTEN; + + switch (ifr & QSPI_IFR_WIDTH) { + case QSPI_IFR_WIDTH_SINGLE_BIT_SPI: + case QSPI_IFR_WIDTH_DUAL_OUTPUT: + case QSPI_IFR_WIDTH_QUAD_OUTPUT: + mode_cycle_bits = 1; + break; + case QSPI_IFR_WIDTH_DUAL_IO: + case QSPI_IFR_WIDTH_DUAL_CMD: + mode_cycle_bits = 2; + break; + case QSPI_IFR_WIDTH_QUAD_IO: + case QSPI_IFR_WIDTH_QUAD_CMD: + mode_cycle_bits = 4; + break; + default: + return -EINVAL; + } + + mode_bits = cmd->num_mode_cycles * mode_cycle_bits; + switch (mode_bits) { + case 1: + ifr |= QSPI_IFR_OPTL_1BIT; + break; + + case 2: + ifr |= QSPI_IFR_OPTL_2BIT; + break; + + case 4: + ifr |= QSPI_IFR_OPTL_4BIT; + break; + + case 8: + ifr |= QSPI_IFR_OPTL_8BIT; + break; + + default: + return -EINVAL; + } + } + + /* Set the number of dummy cycles. */ + if (cmd->enable.bits.dummy) + ifr |= QSPI_IFR_NBDUM_(cmd->num_dummy_cycles); + + /* Set data enable. */ + if (cmd->enable.bits.data) { + ifr |= QSPI_IFR_DATAEN; + + /* Special case for Continuous Read Mode. */ + if (!cmd->tx_buf && !cmd->rx_buf) + ifr |= QSPI_IFR_CRM; + } + + /* Clear pending interrupts. */ + (void)qspi_readl(aq, QSPI_SR); + + /* Set QSPI Instruction Frame registers. */ + qspi_writel(aq, QSPI_IAR, iar); + qspi_writel(aq, QSPI_ICR, icr); + qspi_writel(aq, QSPI_IFR, ifr); + + /* Skip to the final steps if there is no data. */ + if (!cmd->enable.bits.data) + goto no_data; + + /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses. */ + (void)qspi_readl(aq, QSPI_IFR); + + /* Stop here for Continuous Read. */ + memaddr = (unsigned long)(aq->membase + offset); + if (cmd->tx_buf) + /* Write data. */ + atmel_qspi_memcpy_toio(memaddr, cmd->tx_buf, cmd->buf_len); + else if (cmd->rx_buf) + /* Read data. */ + atmel_qspi_memcpy_fromio(cmd->rx_buf, memaddr, cmd->buf_len); + else + /* Stop here for continuous read */ + return 0; + + /* Release the chip-select. */ + qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); + +no_data: + /* Poll INSTruction End and Chip Select Rise flags. */ + imr = (QSPI_SR_INSTRE | QSPI_SR_CSR); + sr = 0; + while (sr != (QSPI_SR_INSTRE | QSPI_SR_CSR)) + sr |= qspi_readl(aq, QSPI_SR) & imr; + + return 0; +} + +static int atmel_qspi_read_reg(struct udevice *dev, u8 opcode, + size_t len, void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + struct atmel_qspi_priv *aq = dev_get_priv(dev->parent); + struct atmel_qspi_command cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.enable.bits.instruction = 1; + cmd.enable.bits.data = 1; + cmd.instruction = opcode; + cmd.rx_buf = buf; + cmd.buf_len = len; + cmd.protocol = flash->reg_proto; + cmd.ifr_tfrtype = QSPI_IFR_TFRTYPE_READ; + return atmel_qspi_send_command(aq, &cmd); +} + +static int atmel_qspi_write_reg(struct udevice *dev, u8 opcode, + size_t len, const void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + struct atmel_qspi_priv *aq = dev_get_priv(dev->parent); + struct atmel_qspi_command cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.enable.bits.instruction = 1; + cmd.enable.bits.data = (buf && len); + cmd.instruction = opcode; + cmd.tx_buf = buf; + cmd.buf_len = len; + cmd.protocol = flash->reg_proto; + cmd.ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE; + return atmel_qspi_send_command(aq, &cmd); +} + +static int atmel_qspi_read_impl(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + struct atmel_qspi_priv *aq = dev_get_priv(flash->dev->parent); + struct atmel_qspi_command cmd; + u8 lshift; + + switch (SPI_FLASH_PROTO_ADR_FROM_PROTO(flash->read_proto)) { + case 1: + lshift = 3; + break; + + case 2: + lshift = 2; + break; + + case 4: + lshift = 1; + break; + + default: + return -EINVAL; + } + + memset(&cmd, 0, sizeof(cmd)); + cmd.enable.bits.instruction = 1; + cmd.enable.bits.address = flash->addr_width; + cmd.enable.bits.mode = 0; + cmd.enable.bits.dummy = (flash->dummy_byte > 0); + cmd.enable.bits.data = 1; + cmd.instruction = flash->read_cmd; + cmd.address = offset; + cmd.num_dummy_cycles = flash->dummy_byte << lshift; + cmd.rx_buf = buf; + cmd.buf_len = len; + cmd.protocol = flash->read_proto; + cmd.ifr_tfrtype = QSPI_IFR_TFRTYPE_READ_MEMORY; + return atmel_qspi_send_command(aq, &cmd); +} + +static int atmel_qspi_read(struct udevice *dev, u32 offset, + size_t len, void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_read_alg(flash, offset, len, buf, + atmel_qspi_read_impl); +} + +static int atmel_qspi_write_impl(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + struct atmel_qspi_priv *aq = dev_get_priv(flash->dev->parent); + struct atmel_qspi_command cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.enable.bits.instruction = 1; + cmd.enable.bits.address = flash->addr_width; + cmd.enable.bits.data = 1; + cmd.instruction = flash->write_cmd; + cmd.address = offset; + cmd.tx_buf = buf; + cmd.buf_len = len; + cmd.protocol = flash->write_proto; + cmd.ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE_MEMORY; + return atmel_qspi_send_command(aq, &cmd); +} + +static int atmel_qspi_write(struct udevice *dev, u32 offset, + size_t len, const void *buf) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_write_alg(flash, offset, len, buf, + atmel_qspi_write_impl); +} + +static int atmel_qspi_erase_impl(struct spi_flash *flash, u32 offset) +{ + struct atmel_qspi_priv *aq = dev_get_priv(flash->dev->parent); + struct atmel_qspi_command cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.enable.bits.instruction = 1; + cmd.enable.bits.address = flash->addr_width; + cmd.instruction = flash->erase_cmd; + cmd.address = offset; + cmd.protocol = flash->erase_proto; + cmd.ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE; + return atmel_qspi_send_command(aq, &cmd); +} + +static int atmel_qspi_erase(struct udevice *dev, u32 offset, size_t len) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_erase_alg(flash, offset, len, + atmel_qspi_erase_impl); +} + +static const struct dm_spi_flash_ops atmel_qspi_flash_ops = { + .read_reg = atmel_qspi_read_reg, + .write_reg = atmel_qspi_write_reg, + .read = atmel_qspi_read, + .write = atmel_qspi_write, + .erase = atmel_qspi_erase, +}; + +static int atmel_qspi_flash_probe(struct udevice *dev) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + int ret; + + flash->dev = dev; + flash->spi = slave; + + /* Claim spi bus */ + ret = spi_claim_bus(slave); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + return ret; + } + + /* The Quad SPI controller supports all Dual & Quad I/O protocols */ + slave->mode |= (SPI_TX_QUAD | SPI_TX_DUAL); + ret = spi_flash_scan(flash, RD_FCMD); + if (ret) { + ret = -EINVAL; + goto release; + } + +#ifdef CONFIG_SPI_FLASH_MTD + ret = spi_flash_mtd_register(flash); +#endif + +release: + spi_release_bus(slave); + return ret; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id atmel_qspi_flash_ids[] = { + { .compatible = "atmel,sama5d2-qspi-flash" }, + { } +}; +#endif + +U_BOOT_DRIVER(atmel_qspi_flash) = { + .name = "atmel_qspi_flash", + .id = UCLASS_SPI_FLASH, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = atmel_qspi_flash_ids, +#endif + .probe = atmel_qspi_flash_probe, + .ops = &atmel_qspi_flash_ops, +}; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f0258f84afeb..d478c5d953c6 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,15 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera.

+config ATMEL_QSPI + bool "Atmel QSPI driver" + depends on ARCH_AT91 + select SPI_FLASH + select DM_SPI_FLASH + help + Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be + used to access SPI NOR flashes. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca7456d6a6..eb3bd95f5ee7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o +obj-$(CONFIG_ATMEL_QSPI) += atmel_qspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o diff --git a/drivers/spi/atmel_qspi.c b/drivers/spi/atmel_qspi.c new file mode 100644 index 000000000000..b8e280553d99 --- /dev/null +++ b/drivers/spi/atmel_qspi.c @@ -0,0 +1,150 @@ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <spi.h> +#include <asm/io.h> +#include <mach/clk.h> + +#include "atmel_qspi.h" + +DECLARE_GLOBAL_DATA_PTR; + + +static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + /* This controller can only be used with SPI NOR flashes. */ + return -EINVAL; +} + +static int atmel_qspi_set_speed(struct udevice *bus, uint hz) +{ + struct atmel_qspi_priv *aq = dev_get_priv(bus); + unsigned long src_rate; + u32 scr, scbr, mask, new_value; + + /* Compute the QSPI baudrate */ + src_rate = get_qspi_clk_rate(aq->dev_id); + scbr = DIV_ROUND_UP(src_rate, hz); + if (scbr > 0) + scbr--; + + new_value = QSPI_SCR_SCBR_(scbr); + mask = QSPI_SCR_SCBR; + + scr = qspi_readl(aq, QSPI_SCR); + if ((scr & mask) == new_value) + return 0; + + scr = (scr & ~mask) | new_value; + qspi_writel(aq, QSPI_SCR, scr); + + return 0; +} + +static int atmel_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct atmel_qspi_priv *aq = dev_get_priv(bus); + u32 scr, mask, new_value; + + new_value = (QSPI_SCR_CPOL_((mode & SPI_CPOL) != 0) | + QSPI_SCR_CPHA_((mode & SPI_CPHA) != 0)); + mask = (QSPI_SCR_CPOL | QSPI_SCR_CPHA); + + scr = qspi_readl(aq, QSPI_SCR); + if ((scr & mask) == new_value) + return 0; + + scr = (scr & ~mask) | new_value; + qspi_writel(aq, QSPI_SCR, scr); + + return 0; +} + +static const struct dm_spi_ops atmel_qspi_ops = { + .xfer = atmel_qspi_xfer, + .set_speed = atmel_qspi_set_speed, + .set_mode = atmel_qspi_set_mode, +}; + +static int atmel_qspi_probe(struct udevice *dev) +{ + const struct atmel_qspi_platdata *plat = dev_get_platdata(dev); + struct atmel_qspi_priv *aq = dev_get_priv(dev); + u32 mr; + + aq->regbase = plat->regbase; + aq->membase = plat->membase; + aq->dev_id = plat->dev_id; + + /* Reset the QSPI controler */ + qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); + + /* Set the QSPI controller in Serial Memory Mode */ + mr = (QSPI_MR_NBBITS_8_BIT | + QSPI_MR_SMM_MEMORY | + QSPI_MR_CSMODE_LASTXFER); + qspi_writel(aq, QSPI_MR, mr); + + /* Enable the QSPI controller */ + qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); + + return 0; +} + +static int atmel_qspi_remove(struct udevice *dev) +{ + struct atmel_qspi_priv *aq = dev_get_priv(dev); + + /* Disable the QSPI controller */ + qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS); + + return 0; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int atmel_qspi_ofdata_to_platdata(struct udevice *dev) +{ + struct atmel_qspi_platdata *plat = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + u32 data[4]; + int ret, seq; + + ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); + if (ret) { + printf("Error: Can't get base addresses (ret=%d)!\n", ret); + return -ENODEV; + } + plat->regbase = (void *)data[0]; + plat->membase = (void *)data[2]; + + ret = fdtdec_get_alias_seq(blob, "spi", node, &seq); + if (ret) { + printf("Error: Can't get device ID (ret=%d)!\n", ret); + return -ENODEV; + } + plat->dev_id = (unsigned int)seq; + + return 0; +} + +static const struct udevice_id atmel_qspi_ids[] = { + { .compatible = "atmel,sama5d2-qspi" }, + { } +}; +#endif + +U_BOOT_DRIVER(atmel_qspi) = { + .name = "atmel_qspi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = atmel_qspi_ids, + .ofdata_to_platdata = atmel_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atmel_qspi_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct atmel_qspi_priv), + .ops = &atmel_qspi_ops, + .probe = atmel_qspi_probe, + .remove = atmel_qspi_remove, +}; diff --git a/drivers/spi/atmel_qspi.h b/drivers/spi/atmel_qspi.h new file mode 100644 index 000000000000..2b221dd44335 --- /dev/null +++ b/drivers/spi/atmel_qspi.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_QSPI_H__ +#define __ATMEL_QSPI_H__ + +/* + * Register Definitions + */ +#define QSPI_CR 0x00 /* Control Register */ +#define QSPI_MR 0x04 /* Mode Register */ +#define QSPI_RDR 0x08 /* Receive Data Register */ +#define QSPI_TDR 0x0c /* Transmit Data Register */ +#define QSPI_SR 0x10 /* Status Register */ +#define QSPI_IER 0x14 /* Interrupt Enable Register */ +#define QSPI_IDR 0x18 /* Interrupt Disable Register */ +#define QSPI_IMR 0x1c /* Interrupt Mask Register */ +#define QSPI_SCR 0x20 /* Serial Clock Register */ +#define QSPI_IAR 0x30 /* Instruction Address Register */ +#define QSPI_ICR 0x34 /* Instruction Code Register */ +#define QSPI_IFR 0x38 /* Instruction Frame Register */ +/* 0x3c Reserved */ +#define QSPI_SMR 0x40 /* Scrambling Mode Register */ +#define QSPI_SKR 0x44 /* Scrambling Key Register */ +/* 0x48 ~ 0xe0 */ +#define QSPI_WPMR 0xe4 /* Write Protection Mode Register */ +#define QSPI_WPSR 0xe8 /* Write Protection Status Register */ +/* 0xec ~ 0xf8 Reserved */ +/* 0xfc Reserved */ + +/* + * Register Field Definitions + */ +/* QSPI_CR */ +#define QSPI_CR_QSPIEN (0x1 << 0) /* QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1 << 1) /* QSPI Disable */ +#define QSPI_CR_SWRST (0x1 << 7) /* QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1 << 24) /* Last Transfer */ + +/* QSPI_MR */ +#define QSPI_MR_SMM (0x1 << 0) /* Serial Memort Mode */ +#define QSPI_MR_SMM_SPI (0x0 << 0) +#define QSPI_MR_SMM_MEMORY (0x1 << 0) +#define QSPI_MR_LLB (0x1 << 1) /* Local Localback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0 << 1) +#define QSPI_MR_LLB_ENABLED (0x1 << 1) +#define QSPI_MR_WDRBT (0x1 << 2) /* Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0 << 2) +#define QSPI_MR_WDRBT_ENABLED (0x1 << 2) +#define QSPI_MR_SMRM (0x1 << 3) /* Serial Memory Register Mode */ +#define QSPI_MR_SMRM_AHB (0x0 << 3) +#define QSPI_MR_SMRM_APB (0x1 << 3) +#define QSPI_MR_CSMODE (0x3 << 4) /* Chip Select Mode */ +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0 << 4) +#define QSPI_MR_CSMODE_LASTXFER (0x1 << 4) +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2 << 4) +#define QSPI_MR_NBBITS (0xf << 8) /* Number of Bits Per Transfer */ +#define QSPI_MR_NBBITS_8_BIT (0x0 << 8) +#define QSPI_MR_NBBITS_16_BIT (0x8 << 8) +#define QSPI_MR_DLYBCT (0xff << 16) /* Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYCS (0xff << 24) /* Minimum Inactive QCS Delay */ + +/* QSPI_SR */ +#define QSPI_SR_RDRF (0x1 << 0) /* Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1 << 1) /* Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1 << 2) /* Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1 << 3) /* Overrun Error Status */ +#define QSPI_SR_CSR (0x1 << 8) /* Chip Select Rise */ +#define QSPI_SR_CSS (0x1 << 9) /* Chip Select Status */ +#define QSPI_SR_INSTRE (0x1 << 10) /* Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1 << 24) /* QSPI Enable Status */ + +/* QSPI_SCR */ +#define QSPI_SCR_CPOL (0x1 << 0) /* Clock Polarity */ +#define QSPI_SCR_CPOL_(x) ((x) << 0) +#define QSPI_SCR_CPHA (0x1 << 1) /* Clock Phase */ +#define QSPI_SCR_CPHA_(x) ((x) << 1) +#define QSPI_SCR_SCBR (0xff << 8) /* Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR_(x) ((x) << 8) +#define QSPI_SCR_DLYBS_(x) ((x) << 16) /* Delay Before QSCK */ + +/* QSPI_ICR */ +#define QSPI_ICR_INST_(x) ((x) << 0) /* Instruction Code */ +#define QSPI_ICR_OPT_(x) ((x) << 16) /* Option Code */ + +/* QSPI_IFR */ +#define QSPI_IFR_WIDTH (0x7 << 0) /* Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0 << 0) +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1 << 0) +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2 << 0) +#define QSPI_IFR_WIDTH_DUAL_IO (0x3 << 0) +#define QSPI_IFR_WIDTH_QUAD_IO (0x4 << 0) +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5 << 0) +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6 << 0) +#define QSPI_IFR_WIDTH_(x) (((x) << 0) & QSPI_IFR_WIDTH) +#define QSPI_IFR_INSTEN (0x1 << 4) /* Instruction Enable*/ +#define QSPI_IFR_ADDREN (0x1 << 5) /* Address Enable*/ +#define QSPI_IFR_OPTEN (0x1 << 6) /* Option Enable*/ +#define QSPI_IFR_DATAEN (0x1 << 7) /* Data Enable*/ +#define QSPI_IFR_OPTL (0x3 << 8) /* Option Code Length */ +#define QSPI_IFR_OPTL_1BIT (0x0 << 8) +#define QSPI_IFR_OPTL_2BIT (0x1 << 8) +#define QSPI_IFR_OPTL_4BIT (0x2 << 8) +#define QSPI_IFR_OPTL_8BIT (0x3 << 8) +#define QSPI_IFR_ADDRL (0x1 << 10) /* Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0 << 10) +#define QSPI_IFR_ADDRL_32_BIT (0x1 << 10) +#define QSPI_IFR_TFRTYPE (0x3 << 12) /* Data Transfer Type */ +#define QSPI_IFR_TFRTYPE_READ (0x0 << 12) +#define QSPI_IFR_TFRTYPE_READ_MEMORY (0x1 << 12) +#define QSPI_IFR_TFRTYPE_WRITE (0x2 << 12) +#define QSPI_IFR_TFRTYPE_WRITE_MEMORY (0x3 << 12) +#define QSPI_IFR_TFRTYPE_(x) (((x) << 12) & QSPI_IFR_TFRTYPE) +#define QSPI_IFR_CRM (0x1 << 14) /* Continuous Read Mode */ +#define QSPI_IFR_NBDUM_(x) ((x) << 16) /* Number Of Dummy Cycles */ + + +struct atmel_qspi_platdata { + unsigned int dev_id; + void *regbase; + void *membase; +}; + +struct atmel_qspi_priv { + unsigned int dev_id; + void *regbase; + void *membase; +}; + +#include <asm/io.h> + +static inline u32 qspi_readl(struct atmel_qspi_priv *aq, u32 reg) +{ + return readl(aq->regbase + reg); +} + +static inline void qspi_writel(struct atmel_qspi_priv *aq, u32 reg, u32 value) +{ + writel(value, aq->regbase + reg); +} + +#endif /* __ATMEL_QSPI_H__ */