[U-Boot] [PATCH v1 00/12] Bring up rk3036 uboot
This series patch bring up rk3036 uboot, since rk3036 only 8K size SRAM, not enough space to add ddr driver, so you should use rockchip bootmerge script to merge ddr.bin and u-boot-dtb.bin.
Lin Huang (12): rockchip: define SUPPORT_SPL and SPL config in RK3288 config rockchip: implement rockchip timer init function rockchip: serial driver support rk3036 rockchip: Bring in RK3036 device tree file includes and bindings rockchip: rk3036: Add clock driver rockchip: rk3036: Add header files for GRF rockchip: rk3036: Add Soc reset driver rockchip: rk3036: Add a simple syscon driver rockchip: rk3036: Add pinctrl driver rockchip: Add an rk3036 MMC driver rockchip: rk3036: Add core Soc start-up code rockchip: Add basic support for evb-rk3036 board
arch/arm/Kconfig | 2 - arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 +++ arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 53 +++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 491 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 2 +- arch/arm/include/asm/arch-rockchip/timer.h | 18 + arch/arm/mach-rockchip/Kconfig | 12 +- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board.c | 19 +- arch/arm/mach-rockchip/common.c | 11 + arch/arm/mach-rockchip/rk3036/Kconfig | 11 + arch/arm/mach-rockchip/rk3036/Makefile | 8 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 7 + configs/evb-rk3036_defconfig | 41 ++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 522 ++++++++++++++++++++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_3036_dw_mmc.c | 479 ++++++++++++++++++++++ drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 +++++++++++++ drivers/serial/serial_rockchip.c | 2 +- include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 116 ++++++ include/configs/rk3288_common.h | 3 +- include/dt-bindings/clock/rk3036-cru.h | 186 +++++++++ 34 files changed, 2858 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/mmc/rockchip_3036_dw_mmc.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h
it may not use SPL in other rockchip SOC, so move SUPPORT_SPL and SPL config to rk3288 configuration.
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None
arch/arm/Kconfig | 2 -- arch/arm/mach-rockchip/Kconfig | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 194fb7b..40fa741 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -831,8 +831,6 @@ config TARGET_STM32F429_DISCOVERY
config ARCH_ROCKCHIP bool "Support Rockchip SoCs" - select SUPPORT_SPL - select SPL select OF_CONTROL select CPU_V7 select DM diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ab50f4e..15cd380 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -2,6 +2,8 @@ if ARCH_ROCKCHIP
config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" + select SUPPORT_SPL + select SPL help The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
now the timer init function implement in board-spl.c, but it may not use SPL in other board or other rockchip SOC, so implement timer init in common.c, we can call it if we need.
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None
arch/arm/include/asm/arch-rockchip/hardware.h | 2 +- arch/arm/include/asm/arch-rockchip/timer.h | 18 ++++++++++++++++++ arch/arm/mach-rockchip/board.c | 8 +++++++- arch/arm/mach-rockchip/common.c | 11 +++++++++++ include/configs/rk3288_common.h | 3 ++- 5 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h
diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index d5af5b8..44bd67a 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -11,7 +11,7 @@ #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
-#define TIMER7_BASE 0xff810020 +#define TIMER_BASE CONFIG_SYS_TIMER_BASE
#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr) #define rk_clrreg(addr, clr) writel((clr) << 16, addr) diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h new file mode 100644 index 0000000..57269e9 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -0,0 +1,18 @@ +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { + unsigned int timer_load_count0; + unsigned int timer_load_count1; + unsigned int timer_curr_value0; + unsigned int timer_curr_value1; + unsigned int timer_ctrl_reg; + unsigned int timer_int_status; +}; + +/** + * timer_init() - rockchip timer init + */ +void rockchip_timer_init(void); + +#endif diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 688bc0f..789a801 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - +#include <asm/arch/timer.h> #include <common.h> #include <dm.h> #include <ram.h> @@ -12,6 +12,12 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void) { +#ifdef CONFIG_SPL_BUILD + + /* have been init in spl board */ +#else + rockchip_timer_init(); +#endif return 0; }
diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c index fc7ac72..eaf8bc1 100644 --- a/arch/arm/mach-rockchip/common.c +++ b/arch/arm/mach-rockchip/common.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <asm/io.h> +#include <asm/arch/timer.h> #include <common.h> #include <dm.h> #include <errno.h> @@ -26,3 +28,12 @@ void *rockchip_get_cru(void)
return (void *)addr; } + +void rockchip_timer_init(void) +{ + struct rk_timer * const timer_ptr = (void *)TIMER_BASE; + + writel(0xffffffff, &timer_ptr->timer_load_count0); + writel(0xffffffff, &timer_ptr->timer_load_count1); + writel(1, &timer_ptr->timer_ctrl_reg); +} diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index e8aec28..b4d040e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -24,7 +24,8 @@ #define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) +#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LIBCOMMON_SUPPORT
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None
drivers/serial/serial_rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 0e7bbfc..1b64ea0 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -12,7 +12,7 @@
static const struct udevice_id rockchip_serial_ids[] = { { .compatible = "rockchip,rk3288-uart" }, - { } + { .compatible = "rockchip,rk3036-uart" }, };
static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3036-cru.h | 186 ++++++++++++++ 2 files changed, 613 insertions(+) create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 include/dt-bindings/clock/rk3036-cru.h
diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi new file mode 100644 index 0000000..e2f3ba9 --- /dev/null +++ b/arch/arm/dts/rk3036.dtsi @@ -0,0 +1,427 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3036-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3036"; + + interrupt-parent = <&gic>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + i2c1 = &i2c1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; + }; + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + sram: sram@10080000 { + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; + reg = <0x10080000 0x2000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3036-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1021c000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>; + /* + <1 28 RK_FUNC_2 &pcfg_pull_up>, + <1 29 RK_FUNC_2 &pcfg_pull_up>, + <1 30 RK_FUNC_2 &pcfg_pull_up>, + <1 31 RK_FUNC_2 &pcfg_pull_up>; + */ + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; +}; diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 0000000..87acf4a --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif
Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 53 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 522 ++++++++++++++++++++++++ 3 files changed, 576 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 drivers/clk/clk_rk3036.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file mode 100644 index 0000000..565491b --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define CPU_ACLK_HZ 150000000 +#define CPU_HCLK_HZ 300000000 +#define CPU_PCLK_HZ 300000000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3036_cru { + struct rk3036_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[11]; + u32 reserved; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved1[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved2[2]; + u32 cru_glb_cnt_th; + u32 cru_sdmmc_con[2]; + u32 cru_sdio_con[2]; + u32 cru_emmc_con[2]; + u32 reserved3; + u32 cru_rst_st; + u32 reserved4[0x23]; + u32 cru_pll_mask_con; +}; +check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); + +#endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 008ec10..4a6a4a8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -6,5 +6,6 @@ #
obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c new file mode 100644 index 0000000..6c64070 --- /dev/null +++ b/drivers/clk/clk_rk3036.c @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_clk_plat { + enum rk_clk_id clk_id; +}; + +struct rk3036_clk_priv { + struct rk3036_cru *cru; + ulong rate; +}; + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_MASK = 7, + PLL_POSTDIV1_SHIFT = 12, + PLL_FBDIV_MASK = 0xfff, + PLL_FBDIV_SHIFT = 0, + + /* PLLCON1 */ + PLL_DSMPD_MASK = 1, + PLL_DSMPD_SHIFT = 12, + PLL_LOCK_STATUS_MASK = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_POSTDIV2_MASK = 7, + PLL_POSTDIV2_SHIFT = 6, + PLL_REFDIV_MASK = 0x3f, + PLL_REFDIV_SHIFT = 0, + PLL_RST_SHIFT = 14, + + /* CRU_MODE */ + GPLL_MODE_MASK = 3, + GPLL_MODE_SHIFT = 12, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + DPLL_MODE_MASK = 1, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_MASK = 1, + APLL_MODE_SHIFT = 0, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + CPU_CLK_PLL_SEL_MASK = 3, + CPU_CLK_PLL_SEL_SHIFT = 14, + CPU_CLK_PLL_SEL_APLL = 0, + CPU_CLK_PLL_SEL_DPLL, + CPU_CLK_PLL_SEL_GPLL, + ACLK_CPU_DIV_MASK = 0x1f, + ACLK_CPU_DIV_SHIFT = 8, + CORE_CLK_PLL_SEL_MASK = 1, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_MASK = 0x1f, + CORE_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL1_CON */ + CPU_PCLK_DIV_MASK = 7, + CPU_PCLK_DIV_SHIFT = 12, + CPU_HCLK_DIV_MASK = 3, + CPU_HCLK_DIV_SHIFT = 8, + CORE_ACLK_DIV_MASK = 7, + CORE_ACLK_DIV_SHIFT = 4, + CORE_PERI_DIV_MASK = 0xf, + CORE_PERI_DIV_SHIFT = 0, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_MASK = 3, + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_SHIFT = 12, + PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_SHIFT = 8, + PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_SHIFT = 0, + + /* CRU_CLKSEL11_CON */ + SDIO_DIV_MASK = 0x7f, + SDIO_DIV_SHIFT = 8, + MMC0_DIV_MASK = 0x7f, + MMC0_DIV_SHIFT = 0, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_MASK = 3, + EMMC_PLL_SHIFT = 12, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_MASK = 3, + SDIO_PLL_SHIFT = 10, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_MASK = 3, + MMC0_PLL_SHIFT = 8, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + EMMC_DIV_MASK = 0x7f, + EMMC_DIV_SHIFT = 0, +}; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static inline unsigned int log2(unsigned int value) +{ + return fls(value) - 1; +} + +static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ + vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use interger mode */ + rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | + PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static void rkclk_init(struct rk3036_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as core clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | + CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | + CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select apll as cpu clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; + assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + + pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; + assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + + hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; + assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | + ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, + CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | + aclk_div << ACLK_CPU_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * select gpll as peri clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT); +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, + GPLL_MODE_SHIFT, 0xff + }; + static u8 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con >> shift) & mask) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; + fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + con = readl(&pll->con1); + postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; + refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + case GPLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case PERIPH_ID_EMMC: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case PERIPH_ID_SDCARD: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock auto divide 2 in internal */ + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + + if (src_clk_div > 0x7f) { + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_PLL_MASK << EMMC_PLL_SHIFT | + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + mux << EMMC_PLL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK << MMC0_PLL_SHIFT | + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static ulong rk3036_clk_get_rate(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + debug("%s\n", dev->name); + return rkclk_pll_get_rate(priv->cru, plat->clk_id); +} + +static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate) +{ + debug("%s\n", dev->name); + + return 0; +} + +ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{ + struct rk3036_clk_priv *priv = dev_get_priv(dev); + ulong new_rate; + + switch (periph) { + case PERIPH_ID_EMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev), + periph, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3036_clk_ops = { + .get_rate = rk3036_clk_get_rate, + .set_rate = rk3036_clk_set_rate, + .set_periph_rate = rk3036_set_periph_rate, +}; + +static int rk3036_clk_probe(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + if (plat->clk_id != CLK_OSC) { + struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent); + + priv->cru = parent_priv->cru; + return 0; + } + priv->cru = (struct rk3036_cru *)dev_get_addr(dev); + rkclk_init(priv->cru); + + return 0; +} + +static const char *const clk_name[] = { + "osc", + "apll", + "dpll", + "cpll", + "gpll", + "mpll", +}; + +static int rk3036_clk_bind(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + int pll, ret; + + /* We only need to set up the root clock */ + if (dev->of_offset == -1) { + plat->clk_id = CLK_OSC; + return 0; + } + + /* Create devices for P main clocks */ + for (pll = 1; pll < CLK_COUNT; pll++) { + struct udevice *child; + struct rk3036_clk_plat *cplat; + + debug("%s %s\n", __func__, clk_name[pll]); + ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll], + &child); + if (ret) + return ret; + + cplat = dev_get_platdata(child); + cplat->clk_id = pll; + } + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev); + if (ret) + debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3036_clk_ids[] = { + { .compatible = "rockchip,rk3036-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rk3036) = { + .name = "clk_rk3036", + .id = UCLASS_CLK, + .of_match = rk3036_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat), + .ops = &rk3036_clk_ops, + .bind = rk3036_clk_bind, + .probe = rk3036_clk_probe, +};
GRF is the gereral register file. Add header files with register definitions.
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 491 ++++++++++++++++++++++++ 1 file changed, 491 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file mode 100644 index 0000000..c25345e --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -0,0 +1,491 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +struct rk3036_grf { + u32 reserved[0x2a]; + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 reserved2[0x0a]; + u32 gpiods; + u32 reserved3[0x05]; + u32 gpio0l_pull; + u32 gpio0h_pull; + u32 gpio1l_pull; + u32 gpio1h_pull; + u32 gpio2l_pull; + u32 gpio2h_pull; + u32 reserved4[4]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_status0; + u32 reserved5; + u32 soc_con3; + u32 reserved6; + u32 dmac_con0; + u32 dmac_con1; + u32 dmac_con2; + u32 reserved7[5]; + u32 uoc0_con5; + u32 reserved8[4]; + u32 uoc1_con4; + u32 uoc1_con5; + u32 reserved9; + u32 ddrc_stat; + u32 uoc_con6; + u32 soc_status1; + u32 cpu_con0; + u32 cpu_con1; + u32 cpu_con2; + u32 cpu_con3; + u32 reserved10; + u32 reserved11; + u32 cpu_status0; + u32 cpu_status1; + u32 os_reg[8]; + u32 reserved12[6]; + u32 dll_con[4]; + u32 dll_status[4]; + u32 dfi_wrnum; + u32 dfi_rdnum; + u32 dfi_actnum; + u32 dfi_timerval; + u32 nfi_fifo[4]; + u32 reserved13[0x10]; + u32 usbphy0_con[8]; + u32 usbphy1_con[8]; + u32 reserved14[0x10]; + u32 chip_tag; + u32 sdmmc_det_cnt; +}; +check_member(rk3036_grf, sdmmc_det_cnt, 0x304); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + GPIO0A1_PWM2, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, + GPIO0A0_PWM1, + +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3, + GPIO0B6_GPIO = 0, + GPIO0B6_MMC1_D3, + GPIO0B6_I2S1_SCLK, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3, + GPIO0B5_GPIO = 0, + GPIO0B5_MMC1_D2, + GPIO0B5_I2S1_SDI, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 3, + GPIO0B4_GPIO = 0, + GPIO0B4_MMC1_D1, + GPIO0B4_I2S1_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3, + GPIO0B3_GPIO = 0, + GPIO0B3_MMC1_D0, + GPIO0B3_I2S1_LRCKRX, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_MMC1_CLKOUT, + GPIO0B1_I2S1_MCLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_MMC1_CMD, + GPIO0B0_I2S1_SDO, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 1, + GPIO0C4_GPIO = 0, + GPIO0C4_DRIVE_VBUS, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 1, + GPIO0C3_GPIO = 0, + GPIO0C3_UART0_CTSN, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 1, + GPIO0C2_GPIO = 0, + GPIO0C2_UART0_RTSN, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 1, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_SIN, + + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 1, + GPIO0C0_GPIO = 0, + GPIO0C0_UART0_SOUT, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPDIF, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM3, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 1, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 1, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 6, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_I2S_PWM1_0, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 1, + GPIO1B3_GPIO = 0, + GPIO1B3_HDMI_HPD, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 1, + GPIO1B2_GPIO = 0, + GPIO1B2_HDMI_SCL, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1, + GPIO1B1_GPIO = 0, + GPIO1B1_HDMI_SDA, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1, + GPIO1B0_GPIO = 0, + GPIO1B0_HDMI_CEC, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 1, + GPIO2A7_GPIO = 0, + GPIO2A7_TESTCLK_OUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 1, + GPIO2B7_GPIO = 0, + GPIO2B7_MAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3, + GPIO2B6_GPIO = 0, + GPIO2B6_MAC_CLKOUT, + GPIO2B6_MAC_CLKIN, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1, + GPIO2B5_GPIO = 0, + GPIO2B5_MAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 1, + GPIO2B4_GPIO = 0, + GPIO2B4_MAC_MDIO, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1, + GPIO2B2_GPIO = 0, + GPIO2B2_MAC_CRS, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3, + GPIO2C7_GPIO = 0, + GPIO2C7_UART1_SOUT, + GPIO2C7_TESTCLK_OUT1, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 1, + GPIO2C6_GPIO = 0, + GPIO2C6_UART1_SIN, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 1, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 1, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 1, + GPIO2C3_GPIO = 0, + GPIO2C3_MAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 1, + GPIO2C2_GPIO = 0, + GPIO2C2_MAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1, + GPIO2C1_GPIO = 0, + GPIO2C1_MAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1, + GPIO2C0_GPIO = 0, + GPIO2C0_MAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1, + GPIO2D6_GPIO = 0, + GPIO2D6_I2S_SDO1, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1, + GPIO2D5_GPIO = 0, + GPIO2D5_I2S_SDO2, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1, + GPIO2D4_GPIO = 0, + GPIO2D4_I2S_SDO3, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 1, + GPIO2D1_GPIO = 0, + GPIO2D1_MAC_MDC, +}; +#endif
We can reset the Soc using some CRU (clock/reset unit) register. Add support for this.
Signed-off-by: Lin Huang hl@rock-chips.com --- Chnages in v1: - clean copyright announcement
arch/arm/mach-rockchip/rk3036/Makefile | 8 +++++ arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile new file mode 100644 index 0000000..643c8d1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset_rk3036.o + diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c new file mode 100644 index 0000000..fefb568 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3036_reset_request(struct udevice *dev, enum reset_t type) +{ + struct rk3036_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case RESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case RESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct reset_ops rk3036_reset = { + .request = rk3036_reset_request, +}; + +U_BOOT_DRIVER(reset_rk3036) = { + .name = "rk3036_reset", + .id = UCLASS_RESET, + .ops = &rk3036_reset, +};
Add a driver that provides access to system controllers
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: -clean copyright announcement
arch/arm/mach-rockchip/rk3036/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 643c8d1..5071551 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -5,4 +5,4 @@ #
obj-y += reset_rk3036.o - +obj-y += syscon_rk3036.o diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c new file mode 100644 index 0000000..965afde --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3036_syscon_ids[] = { + { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3036) = { + .name = "rk3036_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3036_syscon_ids, +};
Add a driver which support pin multiplexing setup for rk3036
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
drivers/pinctrl/Kconfig | 18 ++ drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b8146df..8e414cd 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -114,6 +114,24 @@ config ROCKCHIP_PINCTRL definitions and pin control functions for each available multiplex function.
+config ROCKCHIP_3036_PINCTRL + bool "Rockchip rk3036 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + +config ROCKCHIP_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 251bace..6fa7d00 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,3 +6,4 @@ #
obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c new file mode 100644 index 0000000..25aba1f --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -0,0 +1,276 @@ +/* + * Pinctrl driver for Rockchip 3036 SoCs + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_pinctrl_priv { + struct rk3036_grf *grf; +}; + +static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT, + GPIO0D2_PWM0 << GPIO0D2_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A0_PWM1 << GPIO0A0_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT, + GPIO0A1_PWM2 << GPIO0A1_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT, + GPIO0D3_PWM3 << GPIO0D3_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK << GPIO0A1_SHIFT | + GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK << GPIO0A3_SHIFT | + GPIO0A2_MASK << GPIO0A2_SHIFT, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK << GPIO2C5_SHIFT | + GPIO2C4_MASK << GPIO2C4_SHIFT, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + + break; + } +} + +static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) +{ + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT, + GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); + break; + } + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | + GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); + + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_MASK << GPIO2A0_SHIFT, + GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); +} + +static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C3_MASK << GPIO0C3_SHIFT | + GPIO0C2_MASK << GPIO0C2_SHIFT | + GPIO0C1_MASK << GPIO0C1_SHIFT | + GPIO0C0_MASK << GPIO0C0_SHIFT, + GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | + GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | + GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | + GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C7_MASK << GPIO2C7_SHIFT | + GPIO2C6_MASK << GPIO2C6_SHIFT, + GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | + GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + break; + } +} + +static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A4_MASK << GPIO2A4_SHIFT | + GPIO2A1_MASK << GPIO2A1_SHIFT, + GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | + GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1c_iomux, 0xffff, + GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | + GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | + GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | + GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | + GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | + GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3036_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + pinctrl_rk3036_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk3036_spi_config(priv->grf, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rk3036_uart_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3036_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3036_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 14: + return PERIPH_ID_SDCARD; + case 16: + return PERIPH_ID_EMMC; + case 20: + return PERIPH_ID_UART0; + case 21: + return PERIPH_ID_UART1; + case 22: + return PERIPH_ID_UART2; + case 23: + return PERIPH_ID_SPI0; + case 24: + return PERIPH_ID_I2C0; + case 25: + return PERIPH_ID_I2C1; + case 26: + return PERIPH_ID_I2C2; + case 30: + return PERIPH_ID_PWM0; + } + return -ENOENT; +} + +static int rk3036_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3036_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3036_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3036_pinctrl_ops = { + .set_state_simple = rk3036_pinctrl_set_state_simple, + .request = rk3036_pinctrl_request, + .get_periph_id = rk3036_pinctrl_get_periph_id, +}; + +static int rk3036_pinctrl_probe(struct udevice *dev) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk3036_pinctrl_ids[] = { + { .compatible = "rockchip,rk3036-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3036) = { + .name = "pinctrl_rk3036", + .id = UCLASS_PINCTRL, + .of_match = rk3036_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), + .ops = &rk3036_pinctrl_ops, + .probe = rk3036_pinctrl_probe, +};
rk3036 mmc driver is similar to dw_mmc, but use external dma, this patch implment fifo mode, need to do dma mode in future.
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_3036_dw_mmc.c | 479 +++++++++++++++++++++++++++++++++++++ 3 files changed, 489 insertions(+) create mode 100644 drivers/mmc/rockchip_3036_dw_mmc.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6277f92..38bfb9c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -19,6 +19,15 @@ config ROCKCHIP_DWMMC SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as removeable SD and micro-SD cards.
+config ROCKCHIP_3036_DWMMC + bool "Rockchip 3036 SD/MMC controller support" + depends on DM_MMC && OF_CONTROL + help + This enables support for the Rockchip 3036 SD/MMM controller, which is + based on Designware IP. The device is compatible with at least + SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well + as removeable SD and micro-SD cards. + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on RMOBILE diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 99d0295..ff3920a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_X86) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_ROCKCHIP_DWMMC) += rockchip_dw_mmc.o +obj-$(CONFIG_ROCKCHIP_3036_DWMMC) += rockchip_3036_dw_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o diff --git a/drivers/mmc/rockchip_3036_dw_mmc.c b/drivers/mmc/rockchip_3036_dw_mmc.c new file mode 100644 index 0000000..2a2df52 --- /dev/null +++ b/drivers/mmc/rockchip_3036_dw_mmc.c @@ -0,0 +1,479 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dwmmc.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <linux/err.h> +#include <bouncebuf.h> +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <memalign.h> +#include <mmc.h> +#include <dwmmc.h> +#include <asm-generic/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define PAGE_SIZE 4096 +#define MMC_GET_FCNT(x) (((x)>>17) & 0x1FF) + +struct rockchip_dwmmc_priv { + struct udevice *clk; + struct dwmci_host host; +}; + +static int dwmci_wait_reset(struct dwmci_host *host, u32 value) +{ + unsigned long timeout = 1000; + u32 ctrl; + + dwmci_writel(host, DWMCI_CTRL, value); + + while (timeout--) { + ctrl = dwmci_readl(host, DWMCI_CTRL); + if (!(ctrl & DWMCI_RESET_ALL)) + return 1; + } + return 0; +} + +static int dwmci_set_transfer_mode(struct dwmci_host *host, + struct mmc_data *data) +{ + unsigned long mode; + + mode = DWMCI_CMD_DATA_EXP; + if (data->flags & MMC_DATA_WRITE) + mode |= DWMCI_CMD_RW; + + return mode; +} + +static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct dwmci_host *host = mmc->priv; + int ret = 0, flags = 0, i; + unsigned int timeout = 100000; + u32 retry = 10000; + u32 mask; + ulong start = get_timer(0); + int size; + unsigned int fifo_len; + unsigned int *buf = 0; + + while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { + if (get_timer(start) > timeout) { + debug("%s: Timeout on data busy\n", __func__); + return TIMEOUT; + } + } + + dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); + + if (data) { + /* + * TODO: rk3036 use external DMA, + * need to support DMA mode in future + */ + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src; + dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); + dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); + } + + dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); + + if (data) + flags = dwmci_set_transfer_mode(host, data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= DWMCI_CMD_ABORT_STOP; + else + flags |= DWMCI_CMD_PRV_DAT_WAIT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + flags |= DWMCI_CMD_RESP_EXP; + if (cmd->resp_type & MMC_RSP_136) + flags |= DWMCI_CMD_RESP_LENGTH; + } + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= DWMCI_CMD_CHECK_CRC; + + flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); + + debug("Sending CMD%d\n", cmd->cmdidx); + + dwmci_writel(host, DWMCI_CMD, flags); + + for (i = 0; i < retry; i++) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + if (mask & DWMCI_INTMSK_CDONE) { + if (!data) + dwmci_writel(host, DWMCI_RINTSTS, mask); + break; + } + } + + if (i == retry) { + debug("%s: Timeout.\n", __func__); + return TIMEOUT; + } + + if (mask & DWMCI_INTMSK_RTO) { + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + debug("%s: Response Timeout.\n", __func__); + return TIMEOUT; + } else if (mask & DWMCI_INTMSK_RE) { + debug("%s: Response Error.\n", __func__); + return -EIO; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); + cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); + cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); + cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); + } else { + cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); + } + } + + if (data) { + size = data->blocksize * data->blocks / 4; + start = get_timer(0); + timeout = 1000; + for (;;) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + /* Error during data transfer. */ + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + debug("%s: DATA ERROR!\n", __func__); + ret = -EINVAL; + break; + } + + /* + * TODO: rk3036 use external DMA, + * need to support DMA mode in future + */ + if (data->flags == MMC_DATA_READ) { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_RXDR) && size) { + fifo_len = dwmci_readl(host, + DWMCI_STATUS); + fifo_len = MMC_GET_FCNT(fifo_len); + for (i = 0; i < fifo_len; i++) + *buf++ = dwmci_readl(host, + DWMCI_DATA); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_RXDR); + size = size > fifo_len ? + (size - fifo_len) : 0; + } + } else { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_TXDR) && size) { + fifo_len = dwmci_readl(host, + DWMCI_STATUS); + fifo_len = MMC_GET_FCNT(fifo_len); + for (i = 0; i < fifo_len; i++) + dwmci_writel(host, DWMCI_DATA, + *buf++); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_TXDR); + size = size > fifo_len ? + (size - fifo_len) : 0; + } + } + + /* Data arrived correctly. */ + if (mask & DWMCI_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + debug("%s: Timeout waiting for data!\n", + __func__); + ret = TIMEOUT; + break; + } + } + dwmci_writel(host, DWMCI_RINTSTS, mask); + } + + udelay(100); + + return ret; +} + +static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +{ + u32 div, status; + int timeout = 10000; + unsigned long sclk; + + if ((freq == host->clock) || (freq == 0)) + return 0; + /* + * If host->get_mmc_clk isn't defined, + * then assume that host->bus_hz is source clock value. + * host->bus_hz should be set by user. + */ + if (host->get_mmc_clk) + sclk = host->get_mmc_clk(host, freq); + else if (host->bus_hz) + sclk = host->bus_hz; + else { + debug("%s: Didn't get source clock value.\n", __func__); + return -EINVAL; + } + + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); + + dwmci_writel(host, DWMCI_CLKENA, 0); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + dwmci_writel(host, DWMCI_CLKDIV, div); + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | + DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + + do { + status = dwmci_readl(host, DWMCI_CMD); + if (timeout-- < 0) { + debug("%s: Timeout!\n", __func__); + return -ETIMEDOUT; + } + } while (status & DWMCI_CMD_START); + + dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | + DWMCI_CLKEN_LOW_PWR); + + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | + DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + + timeout = 10000; + do { + status = dwmci_readl(host, DWMCI_CMD); + if (timeout-- < 0) { + debug("%s: Timeout!\n", __func__); + return -ETIMEDOUT; + } + } while (status & DWMCI_CMD_START); + + host->clock = freq; + + return 0; +} + +static void dwmci_set_ios(struct mmc *mmc) +{ + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + u32 ctype, regs; + + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); + + dwmci_setup_bus(host, mmc->clock); + switch (mmc->bus_width) { + case 8: + ctype = DWMCI_CTYPE_8BIT; + break; + case 4: + ctype = DWMCI_CTYPE_4BIT; + break; + default: + ctype = DWMCI_CTYPE_1BIT; + break; + } + + dwmci_writel(host, DWMCI_CTYPE, ctype); + + regs = dwmci_readl(host, DWMCI_UHS_REG); + if (mmc->ddr_mode) + regs |= DWMCI_DDR_MODE; + else + regs &= ~DWMCI_DDR_MODE; + + dwmci_writel(host, DWMCI_UHS_REG, regs); + + if (host->clksel) + host->clksel(host); +} + +static int dwmci_init(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + if (host->board_init) + host->board_init(host); + + dwmci_writel(host, DWMCI_PWREN, 1); + + if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { + debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); + return -EIO; + } + + /* Enumerate at 400KHz */ + dwmci_setup_bus(host, mmc->cfg->f_min); + + dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_INTMASK, 0); + + dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); + + dwmci_writel(host, DWMCI_IDINTEN, 0); + dwmci_writel(host, DWMCI_BMOD, 1); + + if (!host->fifoth_val) { + uint32_t fifo_size; + fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | + TX_WMARK(fifo_size / 2); + } + dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); + + dwmci_writel(host, DWMCI_CLKENA, 0); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + return 0; +} + +static const struct mmc_ops dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, + .init = dwmci_init, +}; + +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +{ + host->cfg.name = host->name; + host->cfg.ops = &dwmci_ops; + host->cfg.f_min = min_clk; + host->cfg.f_max = max_clk; + + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + + host->cfg.host_caps = host->caps; + + if (host->buswidth == 8) { + host->cfg.host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps &= ~MMC_MODE_4BIT; + } else { + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps &= ~MMC_MODE_8BIT; + } + host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) + return -1; + + return 0; +} + +static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) +{ + struct udevice *dev = host->priv; + struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_set_periph_rate(priv->clk, PERIPH_ID_SDMMC0 + host->dev_index, + freq); + if (ret < 0) { + debug("%s: err=%d\n", __func__, ret); + return ret; + } + + return freq; +} + +static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; + host->priv = dev; + + /* use non-removeable as sdcard and emmc as judgement */ + if (fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "non-removable") + == -FDT_ERR_NOTFOUND) + host->dev_index = (ulong)host->ioaddr == 1; + + return 0; +} + +static int rockchip_dwmmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + u32 minmax[2]; + int ret; + + ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk); + if (ret) + return ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", minmax, 2); + if (!ret) + ret = add_dwmci(host, minmax[1], minmax[0]); + if (ret) + return ret; + + upriv->mmc = host->mmc; + + return 0; +} + +static const struct udevice_id rockchip_dwmmc_ids[] = { + { .compatible = "rockchip,rk3288-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_dwmmc_drv) = { + .name = "rockchip_3036_dwmmc", + .id = UCLASS_MMC, + .of_match = rockchip_dwmmc_ids, + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, + .probe = rockchip_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), +};
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
arch/arm/mach-rockchip/Kconfig | 10 ++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board.c | 13 +++- arch/arm/mach-rockchip/rk3036/Kconfig | 11 ++++ include/configs/rk3036_common.h | 116 ++++++++++++++++++++++++++++++++++ 5 files changed, 149 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 include/configs/rk3036_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 15cd380..72d61d1 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,14 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config SYS_MALLOC_F default y
@@ -39,5 +47,5 @@ config ROCKCHIP_SERIAL default y
source "arch/arm/mach-rockchip/rk3288/Kconfig" - +source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5a4e383..1cdbc34 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,3 +11,4 @@ obj-y += board.o endif obj-y += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 789a801..d1d8856 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -3,6 +3,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + +#include <asm/io.h> #include <asm/arch/timer.h> #include <common.h> #include <dm.h> @@ -23,6 +25,7 @@ int board_init(void)
int dram_init(void) { +#ifdef CONFIG_SPL_BUILD struct ram_info ram; struct udevice *dev; int ret; @@ -37,8 +40,16 @@ int dram_init(void) debug("Cannot get DRAM size: %d\n", ret); return ret; } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); gd->ram_size = ram.size; +#else + int i; + unsigned int addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } +#endif
return 0; } diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig new file mode 100644 index 0000000..6198ad6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -0,0 +1,11 @@ +if ROCKCHIP_RK3036 + +config TARGET_EVB_RK3036 + bool "EVB_RK3036" + +config SYS_SOC + default "rockchip" + +source "board/evb_rk3036/evb_rk3036/Kconfig" + +endif diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h new file mode 100644 index 0000000..1d7d20c --- /dev/null +++ b/include/configs/rk3036_common.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_OF_LIBFDT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_ROCKCHIP_3036_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_PINCTRL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_RAM_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (512UL << 20UL) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so + * limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x1fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif
This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: - clean copyright announcement
arch/arm/dts/Makefile | 3 ++- arch/arm/dts/rk3036-sdk.dts | 46 ++++++++++++++++++++++++++++++++ board/evb_rk3036/evb_rk3036/Kconfig | 15 +++++++++++ board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 +++++ board/evb_rk3036/evb_rk3036/evb_rk3036.c | 7 +++++ configs/evb-rk3036_defconfig | 41 ++++++++++++++++++++++++++++ include/configs/evb_rk3036.h | 12 +++++++++ 8 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 include/configs/evb_rk3036.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3babe65..d007199 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -17,7 +17,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ - rk3288-jerry.dtb + rk3288-jerry.dtb \ + rk3036-sdk.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts new file mode 100644 index 0000000..a83badb --- /dev/null +++ b/arch/arm/dts/rk3036-sdk.dts @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "SDK-RK3036"; + compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; + + chosen { + stdout-path = &uart2; + }; + + usb_control { + compatible = "rockchip,rk3036-usb-control"; + host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>; + otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + + dr_mode = "host"; +}; diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/evb_rk3036/evb_rk3036/Kconfig new file mode 100644 index 0000000..ae2a9eb --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3036 + +config SYS_BOARD + default "evb_rk3036" + +config SYS_VENDOR + default "evb_rk3036" + +config SYS_CONFIG_NAME + default "evb_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS new file mode 100644 index 0000000..e69de29 diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/evb_rk3036/evb_rk3036/Makefile new file mode 100644 index 0000000..0403836 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3036.o diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c new file mode 100644 index 0000000..19850ff --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/evb_rk3036.c @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig new file mode 100644 index 0000000..53aa98b --- /dev/null +++ b/configs/evb-rk3036_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3036=y +CONFIG_TARGET_EVB_RK3036=y +CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_RESET=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x20068000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_ACT8846=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h new file mode 100644 index 0000000..aa07889 --- /dev/null +++ b/include/configs/evb_rk3036.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif
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Lin Huang