[U-Boot] [PATCH RESEND 01/14] imx: i.MX7ULP: add get_boot_device
Add get_boot_device for i.MX7ULP
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 13 +++++++++++++ arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 + arch/arm/mach-imx/mx7ulp/soc.c | 27 +++++++++++++++++++++++++++ 3 files changed, 41 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 63b02de087..d58ed43199 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -10,6 +10,8 @@
#define ARCH_MXC
+#define ROM_SW_INFO_ADDR 0x000001E8 + #define CAAM_SEC_SRAM_BASE (0x26000000) #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) @@ -1112,6 +1114,17 @@ struct usbphy_regs { u32 usb1_pfda_ctrl1_tog; /* 0x14c */ };
+struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 rom_tick_freq; + u32 reserved_3[3]; +};
#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h index 6ecde7db93..0e4c8ad15d 100644 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -17,4 +17,5 @@ enum bt_mode { SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ };
+enum boot_device get_boot_device(void); #endif diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index c72f0ed3fc..6015c11869 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -6,6 +6,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/hab.h>
static char *get_reset_cause(char *); @@ -244,3 +245,29 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } #endif + +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_USB: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +}
Since the SD3.0 kernel driver needs M4 image support, this causes problem for usb boot booting into kernel. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0. So the kernel won't depend on M4 image.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/mx7ulp_evk.c | 47 +++++++++++++++++++++++++++++++++ configs/mx7ulp_evk_defconfig | 1 + 2 files changed, 48 insertions(+)
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 3a12fe1551..7527263577 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -4,10 +4,12 @@ */
#include <common.h> +#include <fdt_support.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mx7ulp-pins.h> #include <asm/arch/iomux.h> +#include <asm/mach-imx/boot_mode.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,3 +47,48 @@ int board_init(void)
return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + const char *path; + int rc, nodeoff; + + if (get_boot_device() == USB_BOOT) { + path = fdt_get_alias(blob, "mmc0"); + if (!path) { + puts("Not found mmc0\n"); + return 0; + } + + nodeoff = fdt_path_offset(blob, path); + if (nodeoff < 0) + return 0; + + printf("Found usdhc0 node\n"); + if (fdt_get_property(blob, nodeoff, "vqmmc-supply", + NULL) != NULL) { + rc = fdt_delprop(blob, nodeoff, "vqmmc-supply"); + if (!rc) { + puts("Removed vqmmc-supply property\n"); +add: + rc = fdt_setprop(blob, nodeoff, + "no-1-8-v", NULL, 0); + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 32); + if (!rc) + goto add; + } else if (rc) { + printf("Failed to add no-1-8-v property, %d\n", rc); + } else { + puts("Added no-1-8-v property\n"); + } + } else { + printf("Failed to remove vqmmc-supply property, %d\n", rc); + } + } + } + + return 0; +} +#endif diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index d4eba65ac0..b5ad025ab4 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_TARGET_MX7ULP_EVK=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y
From: Bai Ping ping.bai@nxp.com
The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access it. So check the CPU rev and not apply the settings for B0.
Signed-off-by: Bai Ping ping.bai@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 7 +++++++ arch/arm/mach-imx/mx7ulp/soc.c | 4 ++++ 2 files changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index d58ed43199..3c82e9921e 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -58,6 +58,7 @@ #define USDHC1_AIPS2_SLOT (56) #define RGPIO2P0_AIPS0_SLOT (15) #define RGPIO2P1_AIPS2_SLOT (15) +#define SNVS_AIPS2_SLOT (35) #define IOMUXC0_AIPS0_SLOT (61) #define OCOTP_CTRL_AIPS1_SLOT (38) #define OCOTP_CTRL_PCC1_SLOT (38) @@ -177,6 +178,9 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
+#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) +#define SNVS_LP_LPCR (SNVS_BASE + 0x38) + #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
@@ -939,6 +943,9 @@ #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
+#define SNVS_LPCR_DPEN (0x20) +#define SNVS_LPCR_SRTC_ENV (0x1) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h> diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 6015c11869..7119ee4a07 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -106,6 +106,10 @@ void s_init(void) /* clock configuration. */ clock_init();
+ if (soc_rev() < CHIP_REV_2_0) { + /* enable dumb pmic */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); + } return; }
From: Bai Ping ping.bai@nxp.com
On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index.
Signed-off-by: Bai Ping ping.bai@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/scg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index b4f2ea875a..85d726fe30 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate();
From: Ye Li ye.li@nxp.com
The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7ulp/pcc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 67a0936150..dee3cfcdc0 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -289,10 +289,10 @@ enum pcc3_entry { #define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) #define PCC_PCS_OFFSET 24 #define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 4 +#define PCC_FRAC_OFFSET 3 #define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) #define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type {
From: Ye Li ye.li@nxp.com
Since many drivers need this CONFIG_MX7ULP to distiguish the settings for i.MX7ULP only. Add this entry to cpu's kconfig.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index d4b0299dbd..ed5f0aeb2d 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -3,12 +3,16 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp"
+config MX7ULP + bool + choice prompt "MX7ULP board select" optional
config TARGET_MX7ULP_EVK - bool "Support mx7ulp EVK board" + bool "Support mx7ulp EVK board" + select MX7ULP select SYS_ARCH_TIMER
endchoice
From: Ye Li ye.li@nxp.com
Wrong I2c driver configuration name is used in codes, so I2c driver is not built. Correct it.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7ulp/clock.h | 2 +- arch/arm/mach-imx/mx7ulp/clock.c | 2 +- configs/mx7ulp_evk_defconfig | 1 + configs/mx7ulp_evk_plugin_defconfig | 1 + 4 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index bf69785831..eb02a20fdc 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -26,7 +26,7 @@ enum mxc_clock {
u32 mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num); u32 imx_get_i2cclk(unsigned i2c_num); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index dc317fe810..e333c7815b 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -72,7 +72,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); }
-#ifdef CONFIG_SYS_LPI2C_IMX +#ifdef CONFIG_SYS_I2C_IMX_LPI2C int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { /* Set parent to FIRC DIV2 clock */ diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index b5ad025ab4..3c5d75de0b 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_GPIO=y CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC_IMX=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index ae8d4b4d39..28b75cca5f 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -20,6 +20,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PINCTRL=y
Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/misc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index cb8b5c04db..9968cc4f1f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -200,7 +200,7 @@ config JZ4780_EFUSE
config MXC_OCOTP bool "Enable MXC OCOTP Driver" - depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610 + depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 default y help If you say Y here, you will get support for the One Time
Enable fuse command
Signed-off-by: Peng Fan peng.fan@nxp.com --- configs/mx7ulp_evk_defconfig | 1 + configs/mx7ulp_evk_plugin_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 3c5d75de0b..0f39d878e7 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -9,6 +9,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 28b75cca5f..88c75c4763 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" CONFIG_BOUNCE_BUFFER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y
From: Ye Li ye.li@nxp.com
The num/denom is a float value, but in the calculation it is convert to integer 0, and cause the result wrong.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/scg.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 85d726fe30..a28a2bc81b 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -503,7 +503,10 @@ u32 decode_pll(enum pll_clocks pll)
infreq = infreq / pre_div;
- return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult;
case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -532,7 +535,10 @@ u32 decode_pll(enum pll_clocks pll)
infreq = infreq / pre_div;
- return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult;
case PLL_USB: reg = readl(&scg1_regs->upllcsr);
From: Ye Li ye.li@nxp.com
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index e333c7815b..7012157078 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -300,9 +300,9 @@ void clock_init(void)
scg_a7_soscdiv_init();
- /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); - scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
init_clk_lpuart();
Since there is no register for CPU revision, we use ROM version to check the A0 or B0 chip.
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/soc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 7119ee4a07..6c53aa106e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -18,10 +18,13 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { }; #endif
+#define ROM_VERSION_ADDR 0x80 u32 get_cpu_rev(void) { - /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ - return (MXC_CPU_MX7ULP << 12) | (1 << 4); + /* Check the ROM version for cpu revision */ + u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR); + + return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF); }
#ifdef CONFIG_REVISION_TAG
From: Ye Li ye.li@nxp.com
The normal target frequency for ULP A7 core is 500Mhz, but now ROM set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7ulp/scg.h | 1 + arch/arm/mach-imx/mx7ulp/clock.c | 2 ++ arch/arm/mach-imx/mx7ulp/scg.c | 41 ++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index f1fae010da..531d8f3a95 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -337,5 +337,6 @@ void scg_a7_nicclk_init(void); void scg_a7_sys_clk_sel(enum scg_sys_src clk); void scg_a7_info(void); void scg_a7_soscdiv_init(void); +void scg_a7_init_core_clk(void);
#endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 7012157078..7bf83170eb 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -300,6 +300,8 @@ void clock_init(void)
scg_a7_soscdiv_init();
+ scg_a7_init_core_clk(); + /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index a28a2bc81b..0d31352c77 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -1091,3 +1091,44 @@ void scg_a7_info(void) debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); } + +void scg_a7_init_core_clk(void) +{ + u32 val = 0; + + /* + * The normal target frequency for ULP B0 is 500Mhz, + * but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC + */ + if (soc_rev() >= CHIP_REV_2_0) { + /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */ + if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) { + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + + /* Switch the PLLS to SPLL clk */ + val = readl(&scg1_regs->spllcfg); + val &= ~SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* + * Re-configure PFD0 to 19, + * A7 SPLL(528MHz) * 18 / 19 = 500MHz + */ + scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19); + + /* Switch the PLLS to SPLL PFD0 */ + val = readl(&scg1_regs->spllcfg); + val |= SCG_PLL_CFG_PLLSEL_MASK; + writel(val, &scg1_regs->spllcfg); + + /* Set RCCR SCG to SPLL clk out */ + val = readl(&scg1_regs->rccr); + val &= (~SCG_CCR_SCS_MASK); + val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT); + writel(val, &scg1_regs->rccr); + } + } +}
From: Ye Li ye.li@nxp.com
On i.MX7ULP B0, there is change in NIC clock dividers architecture. On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but on B0 they are parallel with NIC1 DIV. So now the dividers are independent. This patch modifies the scg_nic_get_rate function according to this change.
Signed-off-by: Ye Li ye.li@nxp.com Acked-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/mx7ulp/scg.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 0d31352c77..819c90af6c 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -352,7 +352,7 @@ static u32 scg_ddr_get_rate(void)
static u32 scg_nic_get_rate(enum scg_clk clk) { - u32 reg, val, rate; + u32 reg, val, rate, nic0_rate; u32 shift, mask;
reg = readl(&scg1_regs->niccsr); @@ -370,6 +370,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk) val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
rate = rate / (val + 1); + nic0_rate = rate;
clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
@@ -411,6 +412,13 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return 0; }
+ /* + * On RevB, the nic_bus and nic_ext dividers are parallel + * not chained with nic div + */ + if (soc_rev() >= CHIP_REV_2_0) + rate = nic0_rate; + val = (reg & mask) >> shift; rate = rate / (val + 1);
On Sun, Jul 21, 2019 at 10:24 PM Peng Fan peng.fan@nxp.com wrote:
Add get_boot_device for i.MX7ULP
Signed-off-by: Peng Fan peng.fan@nxp.com
For the entire series:
Tested-by: Fabio Estevam festevam@gmail.com
Without this series I cannot boot Linux on imx7ulp-evk. With this series applied I can.
Thanks
Hi Stefano,
On Sun, Jul 21, 2019 at 10:43 PM Fabio Estevam festevam@gmail.com wrote:
On Sun, Jul 21, 2019 at 10:24 PM Peng Fan peng.fan@nxp.com wrote:
Add get_boot_device for i.MX7ULP
Signed-off-by: Peng Fan peng.fan@nxp.com
For the entire series:
Tested-by: Fabio Estevam festevam@gmail.com
Without this series I cannot boot Linux on imx7ulp-evk. With this series applied I can.
Any comments about this series, please?
I need to upstream one i.MX7ULP based board, which depends on this series.
Thanks
On 02/08/19 19:46, Fabio Estevam wrote:
Hi Stefano,
On Sun, Jul 21, 2019 at 10:43 PM Fabio Estevam festevam@gmail.com wrote:
On Sun, Jul 21, 2019 at 10:24 PM Peng Fan peng.fan@nxp.com wrote:
Add get_boot_device for i.MX7ULP
Signed-off-by: Peng Fan peng.fan@nxp.com
For the entire series:
Tested-by: Fabio Estevam festevam@gmail.com
Without this series I cannot boot Linux on imx7ulp-evk. With this series applied I can.
Any comments about this series, please?
I need to upstream one i.MX7ULP based board, which depends on this series.
I merge it into -master today.
Thanks, Stefano
participants (3)
-
Fabio Estevam -
Peng Fan -
Stefano Babic