On 3/9/24 03:11, Marek Vasut wrote:

...

Use FIELD_PREP to configure content of ETH_SEL bitfield in SYSCFG_PMCSETR register. No functional change.

Signed-off-by: Marek Vasut marex@denx.de

Cc: Christophe Roullier christophe.roullier@st.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Patrice Chotard patrice.chotard@foss.st.com Cc: Patrick Delaunay patrick.delaunay@foss.st.com Cc: Ramon Fried rfried.dev@gmail.com Cc: u-boot@dh-electronics.com Cc: uboot-stm32@st-md-mailman.stormreply.com

---

drivers/net/dwc_eth_qos_stm32.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index d7ec0c9be36..7545026b158 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -26,6 +26,7 @@ #include <reset.h> #include <syscon.h> #include <wait_bit.h> +#include <linux/bitfield.h> #include <linux/delay.h>

#include "dwc_eth_qos.h" @@ -40,9 +41,9 @@ #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)

#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0 +#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1 +#define SYSCFG_PMCSETR_ETH_SEL_RMII 0x4

static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { @@ -142,35 +143,33 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev,

   switch (interface_type) {
   case PHY_INTERFACE_MODE_MII:

•         value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  

•                 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  

•         value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  

•                            SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
  

•         value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
           log_debug("PHY_INTERFACE_MODE_MII\n");
           break;
   case PHY_INTERFACE_MODE_GMII:
  

•         value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  

•                            SYSCFG_PMCSETR_ETH_SEL_GMII_MII);
           if (eth_clk_sel_reg)
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  

•                         SYSCFG_PMCSETR_ETH_CLK_SEL;
  

•         else
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  

•                 value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
           log_debug("PHY_INTERFACE_MODE_GMII\n");
           break;
   case PHY_INTERFACE_MODE_RMII:
  

•         value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  

•                            SYSCFG_PMCSETR_ETH_SEL_RMII);
           if (eth_ref_clk_sel_reg)
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  

•                         SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  

•         else
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  

•                 value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
           log_debug("PHY_INTERFACE_MODE_RMII\n");
           break;
   case PHY_INTERFACE_MODE_RGMII:
   case PHY_INTERFACE_MODE_RGMII_ID:
   case PHY_INTERFACE_MODE_RGMII_RXID:
   case PHY_INTERFACE_MODE_RGMII_TXID:
  

•         value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK,
  

•                            SYSCFG_PMCSETR_ETH_SEL_RGMII);
           if (eth_clk_sel_reg)
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  

•                         SYSCFG_PMCSETR_ETH_CLK_SEL;
  

•         else
  

•                 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  

•                 value |= SYSCFG_PMCSETR_ETH_CLK_SEL;
           log_debug("PHY_INTERFACE_MODE_RGMII\n");
           break;
   default:
  

Reviewed-by: Christophe ROULLIER christophe.roullier@foss.st.com