Hi Tom,

The following changes since commit 7b2d4ecd7f6593771dd3118c8bab525d727a91e0:

Merge branch 'master-spi-fixes' of https://source.denx.de/u-boot/custodians/u-boot-sh (2024-09-09 13:54:10 -0600)

are available in the Git repository at:

https://source.denx.de/u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 1806fed0ce6b56365ecf6b84ce6d17aafd3af979:

cmd: add rdcycle test to RISC-V exception command (2024-09-10 10:10:43 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292 ---------------------------------------------------------------- - Add rdcycle to RISC-V exception command - Some fixes and refactoring ---------------------------------------------------------------- Heinrich Schuchardt (7): clk: sifive: append missing \n to messages clk: sifive: avoid declaring static variables in includes board: fix compatible property Milk-V Mars CM riscv: CONFIG_SPL_FRAMEPOINTER must depend on CONFIG_SPL riscv: allow to enable SHOW_REGS in main U-Boot only riscv: show registers in crash dumps by default cmd: add rdcycle test to RISC-V exception command

Maxim Kochetkov (1): riscv: define find_{first,next}_zero_bit in asm/bitops.h

arch/riscv/Kconfig | 14 ++++++++++++ arch/riscv/include/asm/bitops.h | 40 +++++++++++++++++++++++++++++++++ arch/riscv/lib/interrupts.c | 7 +++--- board/starfive/visionfive2/spl.c | 15 ++++++++++--- cmd/riscv/exception.c | 15 +++++++++++-- drivers/clk/analogbits/wrpll-cln28hpc.c | 6 ++--- drivers/clk/sifive/fu540-prci.c | 7 +++++- drivers/clk/sifive/fu540-prci.h | 22 ------------------ drivers/clk/sifive/fu740-prci.c | 7 +++++- drivers/clk/sifive/fu740-prci.h | 22 ------------------ drivers/clk/sifive/sifive-prci.c | 3 +-- drivers/clk/sifive/sifive-prci.h | 4 ++++ 12 files changed, 102 insertions(+), 60 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.h delete mode 100644 drivers/clk/sifive/fu740-prci.h

Best regards, Leo