Hello Stefano,

Am 11.07.2014 13:10, schrieb Stefano Babic:

Hi Heiko,

On 28/05/2014 12:16, Heiko Schocher wrote:

...

add mxc_iomux_set_gpr_register fucntion

Signed-off-by: Heiko Schocherhs@denx.de Cc: Stefano Babicsbabic@denx.de

---

arch/arm/imx-common/iomux-v3.c | 15 +++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 2 files changed, 17 insertions(+)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 6e46ea8..8739b4c 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -63,3 +63,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, for (i = 0; i< count; i++) imx_iomux_v3_setup_pad(*p++); }

+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,

• 		int value)
  

+{

• int i = 0;
• u32 reg;
• reg = __raw_readl(base + group * 4);
• while (num_bits) {

• reg&= ~(1<<(start_bit + i));
  

• i++;
  

• num_bits--;
  

• }
• reg |= (value<< start_bit);
• __raw_writel(reg, base + group * 4);

+}

It is not clear to me why we need to add this or better, I want to avoid having twice quite the same code doing the same ;-).

We have already a field for gpr: struct iomuxc { u32 gpr[14]; u32 omux[5]; /* mux and pad registers */ };

Ah!

• reg = __raw_readl(base + group * 4);

this could not work when Freescale introduce a new variant with a slight different layout. Thanks to Fabio, we know this is already reality:

http://patchwork.ozlabs.org/patch/368336/

Your code *does* not work with the solox.

Generally, we access register and we use setbits_ and clrsetbits_ to modify single bits. What is the advantage here ?

None, patch not longer needed. I remove it from the next patchserie.

Thanks!

bye, Heiko

On Wed, May 28, 2014 at 3:46 PM, Heiko Schocher hs@denx.de wrote:

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher hs@denx.de Cc: Dirk Behme dirk.behme@gmail.com Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com

---

drivers/spi/mxc_spi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3f029d..3cd93cf 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -212,6 +212,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, int nbytes = DIV_ROUND_UP(bitlen, 8); u32 data, cnt, i; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

•   int timeout;
  
    debug("%s: bitlen %d dout 0x%x din 0x%x\n",
            __func__, bitlen, (u32)dout, (u32)din);
  

@@ -272,9 +273,12 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

•   timeout = 10000;
    /* Wait until the TC (Transfer completed) bit is set */
  

•   while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
  

•           ;
  

•   while (timeout && ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)) {
  

•           timeout--;
  

•           udelay(10);
  

•   }
  

Advice: Not to use fixed time timeouts, instead go for timer api's to poll till TC bit is set.

Sample: from zynq_spi.c /* Check TX FIFO completion */ ts = get_timer(0); status = readl(&zslave->base->isr); while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { printf("spi_xfer: Timeout! TX FIFO not full\n"); return -1; } status = readl(&zslave->base->isr); }

May be you can try similarly like above if possible - comments.

    /* Transfer completed, clear any pending request */
    reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

-- 1.8.3.1

thanks!

Hi Heiko,

On 28/05/2014 12:16, Heiko Schocher wrote:

add enable_spi_clk(), so board code can enable spi clocks.

Signed-off-by: Heiko Schocher hs@denx.de Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Stefano Babic sbabic@denx.de

---

arch/arm/cpu/armv7/mx6/clock.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 1 + 2 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index bd65a08..4735368 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -71,6 +71,23 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) } #endif

+int enable_spi_clk(unsigned char enable, unsigned spi_num)

Add a comment here to understand that spi_num starts from 0.

+{

• u32 reg;
• u32 mask;
• if (spi_num > 3)

• return -EINVAL;
  

The maximum number should be a #define in imx-regs.h, in case we will reuse the code with a new variation of the SOC.

• mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);

• reg = __raw_readl(&imx_ccm->CCGR1);
• if (enable)

• reg |= mask;
  

• else

• reg &= ~mask;
  

• __raw_writel(reg, &imx_ccm->CCGR1);
• return 0;

+} static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 1b4ded7..339c789 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); #endif /* __ASM_ARCH_CLOCK_H */

Best regards, Stefano Babic

Hi Fabio,

On 11/07/2014 15:22, Fabio Estevam wrote:

Hi Heiko,

On Wed, May 28, 2014 at 7:16 AM, Heiko Schocher hs@denx.de wrote:

...

--- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq);

Apart from comments that Stefano pointed out, the patch looks good.

However, this approach doesn't scale very well. In the future, we should be looking into adding Common Clock Framework into U-boot, so that we can better control the clocks like we do in the kernel.

I fully agree.

Not sure if there is anyone interested or willing to work on this topic though.

Anyway, it is good to see this issue because it shows the right way to follow, even if there is not (yet) anybody ready to implement it.

Regards, Stefano

Hi Heiko,

On 28/05/2014 12:16, Heiko Schocher wrote:

CPU: Freescale i.MX6DL rev1.1 at 792 MHz Board: aristaitenos I2C: ready DRAM: 1 GiB NAND: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

This is a good idea - we get at first blick what the board support.

• UART5 is console
• MMC 0 and 1
• USB 0 and 1
• boot from mmc0 and spi nor flash

Signed-off-by: Heiko Schocher hs@denx.de Cc: Stefano Babic sbabic@denx.de

---

board/aristainetos/Makefile | 9 + board/aristainetos/aristainetos.c | 527 ++++++++++++++++++++++++++++++++++++ board/aristainetos/aristainetos.cfg | 33 +++ board/aristainetos/clocks.cfg | 24 ++ board/aristainetos/ddr-setup.cfg | 61 +++++ board/aristainetos/mt41j128M.cfg | 70 +++++ boards.cfg | 1 + include/configs/aristainetos.h | 310 +++++++++++++++++++++ 8 files changed, 1035 insertions(+) create mode 100644 board/aristainetos/Makefile create mode 100644 board/aristainetos/aristainetos.c create mode 100644 board/aristainetos/aristainetos.cfg create mode 100644 board/aristainetos/clocks.cfg create mode 100644 board/aristainetos/ddr-setup.cfg create mode 100644 board/aristainetos/mt41j128M.cfg create mode 100644 include/configs/aristainetos.h

diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile new file mode 100644 index 0000000..5de48bc --- /dev/null +++ b/board/aristainetos/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := aristainetos.o diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c new file mode 100644 index 0000000..56232e2 --- /dev/null +++ b/board/aristainetos/aristainetos.c @@ -0,0 +1,527 @@ +/*

• • (C) Copyright 2014
• • Heiko Schocher, DENX Software Engineering, hs@denx.de.
• • Based on:
• • Copyright (C) 2012 Freescale Semiconductor, Inc.
• • Author: Fabio Estevam fabio.estevam@freescale.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +DECLARE_GLOBAL_DATA_PTR;

+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
• PAD_CTL_SRE_FAST | PAD_CTL_HYS)

+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

• PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
• PAD_CTL_SRE_FAST | PAD_CTL_HYS)

+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

•       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  

+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
• PAD_CTL_ODE | PAD_CTL_SRE_FAST)

+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

+struct i2c_pads_info i2c_pad_info1 = {

• .scl = {

• .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  

• .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  

• .gp = IMX_GPIO_NR(5, 27)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  

• .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  

• .gp = IMX_GPIO_NR(5, 26)
  

• }

+};

+struct i2c_pads_info i2c_pad_info2 = {

• .scl = {

• .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  

• .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  

• .gp = IMX_GPIO_NR(4, 12)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  

• .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  

• .gp = IMX_GPIO_NR(4, 13)
  

• }

+};

+struct i2c_pads_info i2c_pad_info3 = {

• .scl = {

• .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  

• .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  

• .gp = IMX_GPIO_NR(3, 17)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  

• .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  

• .gp = IMX_GPIO_NR(3, 18)
  

• }

+};

+int dram_init(void) +{

• gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
• return 0;

+}

+iomux_v3_cfg_t const uart1_pads[] = {

• MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

+};

+iomux_v3_cfg_t const uart5_pads[] = {

• MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

+};

+iomux_v3_cfg_t const gpio_pads[] = {

• /* LED enable */
• MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* spi flash WP protect */
• MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* backlight enable */
• MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* LED yellow */
• MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* LED red */
• MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* LED green */
• MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* LED blue */
• MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* i2c4 scl */
• MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* i2c4 sda */
• MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static iomux_v3_cfg_t const misc_pads[] = {

• MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* OTG Power enable */
• MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+iomux_v3_cfg_t const enet_pads[] = {

• MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),

+};

+static void setup_iomux_enet(void) +{

• imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
• /* set GPIO_16 as ENET_REF_CLK_OUT */
• mxc_iomux_set_gpr_register(1, 21, 1, 1);

+}

+iomux_v3_cfg_t const usdhc1_pads[] = {

• MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

+};

+iomux_v3_cfg_t const usdhc2_pads[] = {

• MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

+};

+iomux_v3_cfg_t const ecspi4_pads[] = {

• MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static void setup_spi(void) +{

• imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
• enable_spi_clk(1, 0);
• enable_spi_clk(1, 1);
• enable_spi_clk(1, 2);
• enable_spi_clk(1, 3);

It is better to have a for loop here and use true and false for the boolean parameter.

+}

+static void setup_iomux_gpio(void) +{

• imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));

+}

+static void setup_iomux_uart(void) +{

• if (CONFIG_MXC_UART_BASE == UART1_BASE)

• imx_iomux_v3_setup_multiple_pads(uart1_pads,
  

• 				 ARRAY_SIZE(uart1_pads));
  

• else

• imx_iomux_v3_setup_multiple_pads(uart5_pads,
  

• 				 ARRAY_SIZE(uart5_pads));
  

+}

+#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = {

• {USDHC1_BASE_ADDR},
• {USDHC2_BASE_ADDR},

+};

+int board_mmc_getcd(struct mmc *mmc) +{

• struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
• int ret = 0;
• switch (cfg->esdhc_base) {
• case USDHC1_BASE_ADDR:

• ret = 1;
  

• break;
  

• case USDHC2_BASE_ADDR:

• ret = 1;
  

• break;
  

• }

I admit I have not understood the switch case. I understand that getcd() is not used at all. In mmc_init() you have already checked that you can instantiate only two controllers and it is not required to check it again. The function can be simply :

int board_mmc_getcd(struct mmc *mmc) { return 1; }

+int board_mmc_init(bd_t *bis) +{

• s32 status = 0;
• int i;
• /*

• * According to the board_mmc_init() the following map is done:
  

• * (U-boot device node)    (Physical Port)
  

• * mmc0                    SD1
  

• * mmc1                    SD2
  

• */
  

• for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

• switch (i) {
  

• case 0:
  

• 	imx_iomux_v3_setup_multiple_pads(
  

• 		usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  

• 	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  

• 	break;
  

• case 1:
  

• 	imx_iomux_v3_setup_multiple_pads(
  

• 		usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  

• 	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  

• 	break;
  

• default:
  

• 	printf("Warning: you configured more USDHC controllers"
  

• 	       "(%d) then supported by the board (%d)\n",
  

• 	       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  

• 	return status;
  

• }
  

• status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  

• }
• return status;

+}

I think this function can be easier written as for cgtqmx6eval board, without the loop and or-ing the return status.

+#endif

+int board_phy_config(struct phy_device *phydev) +{

• return 0;

+}

It looks weird. It seems that phydev->drv->config is firstly set, and then you overload board_phy_config to avoid using it. If yes, it is should enough to not set drv->config, because this is the default behavior of board_phy_config()

+/*

• • Do not overwrite the console
• • Use always serial for U-Boot console
• */

+int overwrite_console(void) +{

• return 1;

+}

+int board_eth_init(bd_t *bis) +{

• setup_iomux_enet();
• return cpu_eth_init(bis);

+}

+int board_early_init_f(void) +{

• setup_iomux_uart();
• setup_iomux_gpio();
• return 0;

+}

+static int setup_fec(void) +{

• struct iomuxc_base_regs *iomuxc_regs =

• 		(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
  

• int ret;
• /* clear gpr1[14], gpr1[18:17] to select anatop clock */
• clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
• ret = enable_fec_anatop_clock(ENET_50MHz);
• if (ret)

• return ret;
  

• return 0;

+}

+iomux_v3_cfg_t nfc_pads[] = {

• MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static void setup_gpmi_nand(void) +{

• struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
• /* config gpmi nand iomux */
• imx_iomux_v3_setup_multiple_pads(nfc_pads,

• 			 ARRAY_SIZE(nfc_pads));
  

• /* config gpmi and bch clock to 100 MHz */
• clrsetbits_le32(&mxc_ccm->cs2cdr,

• 	MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  

• 	MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  

• 	MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  

• 	MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  

• 	MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  

• 	MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  

• /* enable gpmi and bch clock gating */
• setbits_le32(&mxc_ccm->CCGR4,

•      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  

•      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  

•      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  

•      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  

•      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  

• /* enable apbh clock gating */
• setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);

+}

+#include <spi.h> +static void spi_read(struct spi_slave *spi) +{

• int ret;
• unsigned long flags = SPI_XFER_BEGIN;
• int cmd_len;
• u8 cmd[2];
• u8 val;
• if (!spi)

• return;
  

• cmd[0] = 0x05;
• cmd_len = 1;
• ret = spi_xfer(spi, cmd_len * 8, cmd, &val, flags);
• if (ret) {

• debug("Failed to send command (%zu bytes): %d\n",
  

•       cmd_len, ret);
  

• return;
  

• }
• flags |= SPI_XFER_END;
• val = 0;
• cmd_len = 1;
• ret = spi_xfer(spi, cmd_len * 8, NULL, &val, flags);
• if (ret) {

• debug("Failed to read (%zu bytes): %d\n",
  

•       cmd_len, ret);
  

• return;
  

• }

+}

+static void spi_write(struct spi_slave *spi, u8 reg, u8 val, int len) +{

• int ret;
• unsigned long flags = SPI_XFER_BEGIN;
• int cmd_len;
• u8 cmd[2];
• if (!spi)

• return;
  

• flags |= SPI_XFER_END;
• cmd[0] = reg;
• cmd[1] = val;
• cmd_len = len;
• ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
• if (ret) {

• debug("Failed to send command (%zu bytes): %d\n",
  

•       cmd_len, ret);
  

• }

+}

+static void spi_enable_wp(void) +{

• struct spi_slave *spi;
• int ret;
• spi = spi_setup_slave(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,

• 	      CONFIG_SF_DEFAULT_SPEED,
  

• 	      CONFIG_SF_DEFAULT_MODE);
  

• if (!spi) {

• printf("Failed to set up slave\n");
  

• return;
  

• }
• ret = spi_claim_bus(spi);
• if (ret) {

• debug("Failed to claim SPI bus: %d\n", ret);
  

• goto err_claim_bus;
  

• }
• spi_read(spi);
• spi_write(spi, 0x06, 0x80, 1);
• spi_write(spi, 0x01, 0x80, 2);
• spi_read(spi);
• spi_read(spi);
• spi_write(spi, 0x04, 0x80, 1);
• spi_read(spi);
• spi_release_bus(spi);

+err_claim_bus:

• spi_free_slave(spi);

+}

+int board_init(void) +{

• /* address of boot parameters */
• gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
• setup_fec();

Why is setup_fec() called here instead of board_eth_init() ?

setup_fec() returns an int, but then you ignore it.

• setup_spi();
• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
• setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
• setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

Can we use defines for I2C addresses ?

• /* i2c4 not used, set it to gpio input */
• gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
• gpio_direction_input(IMX_GPIO_NR(1, 7));
• gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
• gpio_direction_input(IMX_GPIO_NR(1, 8));
• /* SPI NOR Flash read only */
• gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
• gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
• gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
• /* enable LED */
• gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
• gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
• gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
• gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
• gpio_request(IMX_GPIO_NR(1, 4), "LED red");
• gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
• gpio_request(IMX_GPIO_NR(1, 5), "LED green");
• gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
• gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
• gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
• setup_gpmi_nand();
• mxc_iomux_set_gpr_register(1, 13, 1, 1);
• imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
• return 0;

+}

+int board_late_init(void) +{

• spi_enable_wp();

Why do we need this in late_init() ?

• return 0;

+}

+int checkboard(void) +{

• puts("Board: aristaitenos\n");
• return 0;

+}

+#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{

• int ret;
• ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
• if (!ret)

• gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
  

• ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
• if (!ret)

• gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
  

• udelay(100000);

Wow ! What for a delay ! Something wrong here ?

• return 0;

+}

+int board_ehci_power(int port, int on) +{

• if (port)

• gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
  

• else

• gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
  

• return 0;

+} +#endif diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg new file mode 100644 index 0000000..2290180 --- /dev/null +++ b/board/aristainetos/aristainetos.cfg @@ -0,0 +1,33 @@ +/*

• • (C) Copyright 2014
• • Heiko Schocher, DENX Software Engineering, hs@denx.de.
• • Based on:
• • Copyright (C) 2013 Boundary Devices
• • SPDX-License-Identifier: GPL-2.0+
• • Refer doc/README.imximage for more details about how-to configure
• • and create imximage boot image
• • The syntax is taken as close as possible with the kwbimage
• */

+/* image version */ +IMAGE_VERSION 2

+/*

• • Boot Device : one of
• • spi, sd
• */

+BOOT_FROM spi

+#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h"

+#include "ddr-setup.cfg" +#include "mt41j128M.cfg" +#include "clocks.cfg" diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg new file mode 100644 index 0000000..651449e --- /dev/null +++ b/board/aristainetos/clocks.cfg @@ -0,0 +1,24 @@ +/*

• • Copyright (C) 2013 Boundary Devices
• • SPDX-License-Identifier: GPL-2.0+
• • Device Configuration Data (DCD)
• • Each entry must have the format:
• • Addr-type Address Value
• • where:

• •  Addr-type register length (1,2 or 4 bytes)
    

• •  Address   absolute address of the register
    

• •  value     value to be stored in the register
    

• */

+/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00c03f3f +DATA 4, CCM_CCGR1, 0x0030fcff +DATA 4, CCM_CCGR2, 0x0fffcfc0 +DATA 4, CCM_CCGR3, 0x3ff0300f +DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0f0000c3 +DATA 4, CCM_CCGR6, 0x000003ff diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg new file mode 100644 index 0000000..c72a3ef --- /dev/null +++ b/board/aristainetos/ddr-setup.cfg @@ -0,0 +1,61 @@ +/*

• • Copyright (C) 2013 Boundary Devices
• • SPDX-License-Identifier: GPL-2.0+
• • Device Configuration Data (DCD)
• • Each entry must have the format:
• • Addr-type Address Value
• • where:

• •  Addr-type register length (1,2 or 4 bytes)
    

• •  Address   absolute address of the register
    

• •  value     value to be stored in the register
    

• */

+/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* Data Strobe */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg new file mode 100644 index 0000000..3561655 --- /dev/null +++ b/board/aristainetos/mt41j128M.cfg @@ -0,0 +1,70 @@ +/*

• • Copyright (C) 2013 Boundary Devices
• • SPDX-License-Identifier: GPL-2.0+
• */

+/* ZQ Calibration */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/*

• • DQS gating, read delay, write delay calibration values
• • based on calibration compare of 0x00ffff00
• */

+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +/* MR2 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a +/* MR3 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +/* MR1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +/* MR0 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +/* final ddr setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d +DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/boards.cfg b/boards.cfg index 81e28ba..973776c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -308,6 +308,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic sbabic@denx.de +Active arm armv7 mx6 - aristainetos aristainetos aristainetos:IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL Heiko Schocher hs@denx.de Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam fabio.estevam@freescale.com diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h new file mode 100644 index 0000000..52fb173 --- /dev/null +++ b/include/configs/aristainetos.h @@ -0,0 +1,310 @@ +/*

• • (C) Copyright 2014
• • Heiko Schocher, DENX Software Engineering, hs@denx.de.
• • Based on:
• • Copyright (C) 2012 Freescale Semiconductor, Inc.
• • Configuration settings for the Freescale i.MX6Q SabreSD board.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __ARISTAINETOS_CONFIG_H +#define __ARISTAINETOS_CONFIG_H

+#define CONFIG_MX6

+#include "mx6_common.h" +#include <linux/sizes.h>

+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO

+#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h>

+#define CONFIG_MACH_TYPE 4501 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_DEFAULT_FDT_FILE "aristainetos.dtb" +#define CONFIG_HOSTNAME aristainetos +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)

+#define CONFIG_SYS_GENERIC_BOARD

+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)

+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO

+#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART5_BASE +#define CONFIG_CONSOLE_DEV "ttymxc4"

+#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif

+/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0

+#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION

+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0

+#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL

+#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 3 +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8)) +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif

+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200

+/* Command definition */ +#include <config_cmd_default.h>

+#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS

+#define CONFIG_BOOTDELAY 3

+#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000

+#define CONFIG_EXTRA_ENV_SETTINGS \

• "uimage=uImage\0" \
• "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
• "fdt_addr_r=0x11000000\0" \
• "kernel_addr_r=0x12000000\0" \
• "kernel_file=uImage\0" \
• "boot_fdt=try\0" \
• "ip_dyn=yes\0" \
• "console=" CONFIG_CONSOLE_DEV "\0" \
• "fdt_high=0xffffffff\0" \
• "initrd_high=0xffffffff\0" \
• "mmcpart=1\0" \
• "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
• "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
• "mmcargs=setenv bootargs console=${console},${baudrate} " \

• "root=${mmcroot}\0" \
  

• "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} " \

• "${uimage}\0" \
  

• "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} " \

• "${fdt_file}\0" \
  

• "mmcboot=echo Booting from mmc ...; " \

• "run mmcargs;run loadimage loadfdt fdt_setup;" \
  

• "bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \
  

• "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-sato-sdk\0" \
• "nfsopts=nfsvers=3 nolock rw\0" \
• "netdev=eth0\0" \
• "fdt_setup=fdt addr ${fdt_addr_r};fdt resize;fdt chosen;fdt board\0"\
• "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
• "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
• "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
• "get_env=mw ${loadaddr} 0x00000000 0x20000;" \

• "tftp ${loadaddr} /tftpboot/aristainetos/env.txt;" \
  

• "env import -t ${loadaddr}\0" \
  

• "addmisc=setenv bootargs ${bootargs} maxcpus=1 loglevel=8\0" \
• "bootargs_defaults=setenv bootargs ${console} ${mtdoops} " \

• "${optargs}\0" \
  

• "net_args=run bootargs_defaults;setenv bootargs ${bootargs} " \

• "root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} " \
  

• "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
  

• "${hostname}:${netdev}:off\0" \
  

• "net_nfs=run load_kernel load_fdt;run net_args addmtd addmisc;" \

• "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  

• "uboot=/tftpboot/aristainetos/u-boot.imx\0" \
• "load_uboot=tftp ${loadaddr} ${uboot}\0" \
• "uboot_sz=c0000\0" \
• "upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \

• "mw.b 10200000 0x00 ${uboot_sz};" \
  

• "run load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
  

• "sf write ${loadaddr} 400 ${filesize};" \
  

• "sf read 10200000 400 ${uboot_sz};" \
  

• "cmp.b ${loadaddr} 10200000 bc000\0" \
  

• "ubi_prep=ubi part ubi 2048;ubifsmount ubi:kernel\0" \
• "load_kernel_ubi=ubifsload ${kernel_addr_r} uImage\0" \
• "load_fdt_ubi=ubifsload ${fdt_addr_r} aristainetos.dtb\0" \
• "ubi_nfs=run ubiprep load_kernel_ubi load_fdt_ubi;" \

• "run net_args addmtd addmisc;run fdt_setup;" \
  

• "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  

• "rootfsname=rootfs\0" \
• "ubi_args=run bootargs_defaults;setenv bootargs ${bootargs} " \

• "ubi.mtd=0,2048 root=ubi0:${rootfsname} rootfstype=ubifs " \
  

• "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
  

• "${hostname}:${netdev}:off\0" \
  

• "ubi_ubi=run ubi_prep load_kernel_ubi load_fdt_ubi;" \

• "run bootargs_defaults ubi_args addmtd addmisc;" \
  

• "run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  

• "ubirootfs_file=/tftpboot/aristainetos/rootfs-minimal.ubifs\0" \
• "upd_ubirootfs=run ubi_prep;tftp ${loadaddr} ${ubirootfs_file};" \

• "ubi write ${loadaddr} rootfs ${filesize}\0" \
  

• "ksz=800000\0" \
• "rootsz=2000000\0" \
• "usersz=8000000\0" \
• "ubi_make=run ubi_prep;ubi create kernel ${ksz};" \

• "ubi create rootfs ${rootsz};ubi create userfs ${usersz}\0"
  

+#define CONFIG_BOOTCOMMAND \

• "mmc dev ${mmcdev};" \
• "if mmc rescan; then " \

• "run mmcboot;" \
  

• "else run ubi_ubi; fi"

+#define CONFIG_ARP_TIMEOUT 200UL

+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256

+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000

+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

+#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024)

+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

+#define CONFIG_SYS_INIT_SP_OFFSET \

• (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_ADDR \

• (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

+/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH

+#define CONFIG_ENV_SIZE (12 * 1024) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SECT_SIZE (0x010000) +#define CONFIG_ENV_OFFSET (0x0c0000) +#define CONFIG_ENV_OFFSET_REDUND (0x0d0000) +#endif

+#define CONFIG_OF_LIBFDT

+#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif

+#define CONFIG_SYS_FSL_USDHC_NUM 2

+#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }

+#define CONFIG_CMD_GPIO +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)

+/* NAND stuff */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION

+/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8

+/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_RTC_M41T11 +#define CONFIG_CMD_DATE

+/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0

+#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) +#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31)

+/* UBI support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS

+#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(ubi)"

+#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1

+#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG

+#ifndef CONFIG_SPL_BUILD

?? I do not see you use SPL.

+#define CONFIG_FIT +#endif +#endif /* __ARISTAINETOS_CONFIG_H */

Best regards, Stefano Babic