[U-Boot] [PATCH 1/6 v4] i2c: designware_i2c: Add ic_enable_status to ic_regs struct
Add the ic_enable_status register to the i2c_regs struct. Additionally the register offsets are added, to better check, if the offset matches the register description in the datasheet.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Rebased on latest mainline
v2: - Fix typo in commit text - Added Reviewed-by from Bin
drivers/i2c/designware_i2c.h | 68 +++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index 19b09df..270c29c 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -9,39 +9,41 @@ #define __DW_I2C_H_
struct i2c_regs { - u32 ic_con; - u32 ic_tar; - u32 ic_sar; - u32 ic_hs_maddr; - u32 ic_cmd_data; - u32 ic_ss_scl_hcnt; - u32 ic_ss_scl_lcnt; - u32 ic_fs_scl_hcnt; - u32 ic_fs_scl_lcnt; - u32 ic_hs_scl_hcnt; - u32 ic_hs_scl_lcnt; - u32 ic_intr_stat; - u32 ic_intr_mask; - u32 ic_raw_intr_stat; - u32 ic_rx_tl; - u32 ic_tx_tl; - u32 ic_clr_intr; - u32 ic_clr_rx_under; - u32 ic_clr_rx_over; - u32 ic_clr_tx_over; - u32 ic_clr_rd_req; - u32 ic_clr_tx_abrt; - u32 ic_clr_rx_done; - u32 ic_clr_activity; - u32 ic_clr_stop_det; - u32 ic_clr_start_det; - u32 ic_clr_gen_call; - u32 ic_enable; - u32 ic_status; - u32 ic_txflr; - u32 ix_rxflr; - u32 reserved_1; - u32 ic_tx_abrt_source; + u32 ic_con; /* 0x00 */ + u32 ic_tar; /* 0x04 */ + u32 ic_sar; /* 0x08 */ + u32 ic_hs_maddr; /* 0x0c */ + u32 ic_cmd_data; /* 0x10 */ + u32 ic_ss_scl_hcnt; /* 0x14 */ + u32 ic_ss_scl_lcnt; /* 0x18 */ + u32 ic_fs_scl_hcnt; /* 0x1c */ + u32 ic_fs_scl_lcnt; /* 0x20 */ + u32 ic_hs_scl_hcnt; /* 0x24 */ + u32 ic_hs_scl_lcnt; /* 0x28 */ + u32 ic_intr_stat; /* 0x2c */ + u32 ic_intr_mask; /* 0x30 */ + u32 ic_raw_intr_stat; /* 0x34 */ + u32 ic_rx_tl; /* 0x38 */ + u32 ic_tx_tl; /* 0x3c */ + u32 ic_clr_intr; /* 0x40 */ + u32 ic_clr_rx_under; /* 0x44 */ + u32 ic_clr_rx_over; /* 0x48 */ + u32 ic_clr_tx_over; /* 0x4c */ + u32 ic_clr_rd_req; /* 0x50 */ + u32 ic_clr_tx_abrt; /* 0x54 */ + u32 ic_clr_rx_done; /* 0x58 */ + u32 ic_clr_activity; /* 0x5c */ + u32 ic_clr_stop_det; /* 0x60 */ + u32 ic_clr_start_det; /* 0x64 */ + u32 ic_clr_gen_call; /* 0x68 */ + u32 ic_enable; /* 0x6c */ + u32 ic_status; /* 0x70 */ + u32 ic_txflr; /* 0x74 */ + u32 ic_rxflr; /* 0x78 */ + u32 ic_sda_hold; /* 0x7c */ + u32 ic_tx_abrt_source; /* 0x80 */ + u8 res1[0x18]; /* 0x84 */ + u32 ic_enable_status; /* 0x9c */ };
#if !defined(IC_CLK)
dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes sense to add such a function, as the controller is dis-/en-abled multiple times in the code. Additionally, this function now checks, if the controller is really dis-/en-abled. This code is copied from the Linux I2C driver version.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Rebased on latest mainline
v3: - Rework dw_i2c_enable() as suggested by Marek
v2: - Use true / false for binary values as suggested by Bin
drivers/i2c/designware_i2c.c | 47 +++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e768cde..d5b3e29 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -34,6 +34,27 @@ static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) return NULL; }
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) +{ + u32 ena = enable ? IC_ENABLE_0B : 0; + int timeout = 100; + + do { + writel(ena, &i2c_base->ic_enable); + if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) + return; + + /* + * Wait 10 times the signaling period of the highest I2C + * transfer supported by the driver (for 400KHz this is + * 25us) as described in the DesignWare I2C databook. + */ + udelay(25); + } while (timeout--); + + printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); +} + /* * set_speed - Set the i2c speed mode (standard, high, fast) * @i2c_spd: required i2c speed mode @@ -45,12 +66,9 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd) struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; - unsigned int enbl;
/* to set speed cltr must be disabled */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false);
cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
@@ -84,8 +102,7 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd) writel(cntl, &i2c_base->ic_con);
/* Enable back i2c now speed set */ - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); }
/* @@ -123,12 +140,9 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { struct i2c_regs *i2c_base = i2c_get_base(adap); - unsigned int enbl;
/* Disable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false);
writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); writel(IC_RX_TL, &i2c_base->ic_rx_tl); @@ -138,9 +152,7 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, writel(slaveaddr, &i2c_base->ic_sar);
/* Enable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); }
/* @@ -152,19 +164,14 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) { struct i2c_regs *i2c_base = i2c_get_base(adap); - unsigned int enbl;
/* Disable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false);
writel(i2c_addr, &i2c_base->ic_tar);
/* Enable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); }
/*
On Thu, Apr 21, 2016 at 2:19 PM, Stefan Roese sr@denx.de wrote:
dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes sense to add such a function, as the controller is dis-/en-abled multiple times in the code. Additionally, this function now checks, if the controller is really dis-/en-abled. This code is copied from the Linux I2C driver version.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de
v4:
- Rebased on latest mainline
v3:
- Rework dw_i2c_enable() as suggested by Marek
v2:
- Use true / false for binary values as suggested by Bin
drivers/i2c/designware_i2c.c | 47 +++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 20 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Integrating set_speed() into dw_i2c_set_bus_speed() will make the conversion to DM easier for this driver.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Rebased on latest mainline
drivers/i2c/designware_i2c.c | 37 +++++++++++++------------------------ 1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index d5b3e29..035bf23 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -56,16 +56,25 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) }
/* - * set_speed - Set the i2c speed mode (standard, high, fast) - * @i2c_spd: required i2c speed mode + * i2c_set_bus_speed - Set the i2c speed + * @speed: required i2c speed * - * Set the i2c speed mode (standard, high, fast) + * Set the i2c speed. */ -static void set_speed(struct i2c_adapter *adap, int i2c_spd) +static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; + int i2c_spd; + + if (speed >= I2C_MAX_SPEED) + i2c_spd = IC_SPEED_MODE_MAX; + else if (speed >= I2C_FAST_SPEED) + i2c_spd = IC_SPEED_MODE_FAST; + else + i2c_spd = IC_SPEED_MODE_STANDARD;
/* to set speed cltr must be disabled */ dw_i2c_enable(i2c_base, false); @@ -103,27 +112,7 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd)
/* Enable back i2c now speed set */ dw_i2c_enable(i2c_base, true); -} - -/* - * i2c_set_bus_speed - Set the i2c speed - * @speed: required i2c speed - * - * Set the i2c speed. - */ -static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - int i2c_spd; - - if (speed >= I2C_MAX_SPEED) - i2c_spd = IC_SPEED_MODE_MAX; - else if (speed >= I2C_FAST_SPEED) - i2c_spd = IC_SPEED_MODE_FAST; - else - i2c_spd = IC_SPEED_MODE_STANDARD;
- set_speed(adap, i2c_spd); adap->speed = speed;
return 0;
This patch prepares the designware I2C driver for the DM conversion. This is mainly done by removing struct i2c_adapter from the functions that shall be used by the DM driver version as well.
Signed-off-by: Stefan Roese sr@denx.de Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Rebased on latest mainline
drivers/i2c/designware_i2c.c | 173 ++++++++++++++++++++++--------------------- 1 file changed, 90 insertions(+), 83 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 035bf23..2adc36e 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -10,30 +10,6 @@ #include <asm/io.h> #include "designware_i2c.h"
-static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) -{ - switch (adap->hwadapnr) { -#if CONFIG_SYS_I2C_BUS_MAX >= 4 - case 3: - return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; -#endif -#if CONFIG_SYS_I2C_BUS_MAX >= 3 - case 2: - return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; -#endif -#if CONFIG_SYS_I2C_BUS_MAX >= 2 - case 1: - return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; -#endif - case 0: - return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; - default: - printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); - } - - return NULL; -} - static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) { u32 ena = enable ? IC_ENABLE_0B : 0; @@ -61,10 +37,9 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) * * Set the i2c speed. */ -static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) +static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, + unsigned int speed) { - struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; int i2c_spd; @@ -113,47 +88,17 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, /* Enable back i2c now speed set */ dw_i2c_enable(i2c_base, true);
- adap->speed = speed; - return 0; }
/* - * i2c_init - Init function - * @speed: required i2c speed - * @slaveaddr: slave address for the device - * - * Initialization function. - */ -static void dw_i2c_init(struct i2c_adapter *adap, int speed, - int slaveaddr) -{ - struct i2c_regs *i2c_base = i2c_get_base(adap); - - /* Disable i2c */ - dw_i2c_enable(i2c_base, false); - - writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); - writel(IC_RX_TL, &i2c_base->ic_rx_tl); - writel(IC_TX_TL, &i2c_base->ic_tx_tl); - dw_i2c_set_bus_speed(adap, speed); - writel(IC_STOP_DET, &i2c_base->ic_intr_mask); - writel(slaveaddr, &i2c_base->ic_sar); - - /* Enable i2c */ - dw_i2c_enable(i2c_base, true); -} - -/* * i2c_setaddress - Sets the target slave address * @i2c_addr: target i2c address * * Sets the target slave address. */ -static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) +static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr) { - struct i2c_regs *i2c_base = i2c_get_base(adap); - /* Disable i2c */ dw_i2c_enable(i2c_base, false);
@@ -168,10 +113,8 @@ static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) * * Flushes the i2c RX FIFO */ -static void i2c_flush_rxfifo(struct i2c_adapter *adap) +static void i2c_flush_rxfifo(struct i2c_regs *i2c_base) { - struct i2c_regs *i2c_base = i2c_get_base(adap); - while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) readl(&i2c_base->ic_cmd_data); } @@ -181,9 +124,8 @@ static void i2c_flush_rxfifo(struct i2c_adapter *adap) * * Waits for bus busy */ -static int i2c_wait_for_bb(struct i2c_adapter *adap) +static int i2c_wait_for_bb(struct i2c_regs *i2c_base) { - struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_bb = get_timer(0);
while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || @@ -197,15 +139,13 @@ static int i2c_wait_for_bb(struct i2c_adapter *adap) return 0; }
-static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr, +static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr, int alen) { - struct i2c_regs *i2c_base = i2c_get_base(adap); - - if (i2c_wait_for_bb(adap)) + if (i2c_wait_for_bb(i2c_base)) return 1;
- i2c_setaddress(adap, chip); + i2c_setaddress(i2c_base, chip); while (alen) { alen--; /* high byte address going out first */ @@ -215,9 +155,8 @@ static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr, return 0; }
-static int i2c_xfer_finish(struct i2c_adapter *adap) +static int i2c_xfer_finish(struct i2c_regs *i2c_base) { - struct i2c_regs *i2c_base = i2c_get_base(adap); ulong start_stop_det = get_timer(0);
while (1) { @@ -229,12 +168,12 @@ static int i2c_xfer_finish(struct i2c_adapter *adap) } }
- if (i2c_wait_for_bb(adap)) { + if (i2c_wait_for_bb(i2c_base)) { printf("Timed out waiting for bus\n"); return 1; }
- i2c_flush_rxfifo(adap); + i2c_flush_rxfifo(i2c_base);
return 0; } @@ -249,10 +188,9 @@ static int i2c_xfer_finish(struct i2c_adapter *adap) * * Read from i2c memory. */ -static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *buffer, int len) +static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, + int alen, u8 *buffer, int len) { - struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned long start_time_rx;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW @@ -274,7 +212,7 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, addr); #endif
- if (i2c_xfer_init(adap, dev, addr, alen)) + if (i2c_xfer_init(i2c_base, dev, addr, alen)) return 1;
start_time_rx = get_timer(0); @@ -294,7 +232,7 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, } }
- return i2c_xfer_finish(adap); + return i2c_xfer_finish(i2c_base); }
/* @@ -307,10 +245,9 @@ static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, * * Write to i2c memory. */ -static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *buffer, int len) +static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, + int alen, u8 *buffer, int len) { - struct i2c_regs *i2c_base = i2c_get_base(adap); int nb = len; unsigned long start_time_tx;
@@ -333,7 +270,7 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, addr); #endif
- if (i2c_xfer_init(adap, dev, addr, alen)) + if (i2c_xfer_init(i2c_base, dev, addr, alen)) return 1;
start_time_tx = get_timer(0); @@ -354,7 +291,76 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, } }
- return i2c_xfer_finish(adap); + return i2c_xfer_finish(i2c_base); +} + +static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if CONFIG_SYS_I2C_BUS_MAX >= 4 + case 3: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; +#endif +#if CONFIG_SYS_I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; +#endif +#if CONFIG_SYS_I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; +#endif + case 0: + return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; + default: + printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); + } + + return NULL; +} + +static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + adap->speed = speed; + return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed); +} + +/* + * i2c_init - Init function + * @speed: required i2c speed + * @slaveaddr: slave address for the device + * + * Initialization function. + */ +static void dw_i2c_init(struct i2c_adapter *adap, int speed, + int slaveaddr) +{ + struct i2c_regs *i2c_base = i2c_get_base(adap); + + /* Disable i2c */ + dw_i2c_enable(i2c_base, false); + + writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); + writel(IC_RX_TL, &i2c_base->ic_rx_tl); + writel(IC_TX_TL, &i2c_base->ic_tx_tl); + dw_i2c_set_bus_speed(adap, speed); + writel(IC_STOP_DET, &i2c_base->ic_intr_mask); + writel(slaveaddr, &i2c_base->ic_sar); + + /* Enable i2c */ + dw_i2c_enable(i2c_base, true); +} + +static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) +{ + return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len); +} + +static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *buffer, int len) +{ + return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len); }
/* @@ -362,13 +368,14 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, */ static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) { + struct i2c_regs *i2c_base = i2c_get_base(adap); u32 tmp; int ret;
/* * Try to read the first location of the chip. */ - ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1); + ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1); if (ret) dw_i2c_init(adap, adap->speed, adap->slaveaddr);
This patch adds DM support to the designware I2C driver. It currently supports DM and the legacy I2C support. The legacy support should be removed, once all platforms using it have DM enabled.
Signed-off-by: Stefan Roese sr@denx.de Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Rebased on latest mainline
drivers/i2c/designware_i2c.c | 149 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 123 insertions(+), 26 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 2adc36e..d653eff 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -6,10 +6,15 @@ */
#include <common.h> +#include <dm.h> #include <i2c.h> #include <asm/io.h> #include "designware_i2c.h"
+struct dw_i2c { + struct i2c_regs *regs; +}; + static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) { u32 ena = enable ? IC_ENABLE_0B : 0; @@ -294,6 +299,36 @@ static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, return i2c_xfer_finish(i2c_base); }
+/* + * __dw_i2c_init - Init function + * @speed: required i2c speed + * @slaveaddr: slave address for the device + * + * Initialization function. + */ +static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) +{ + /* Disable i2c */ + dw_i2c_enable(i2c_base, false); + + writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); + writel(IC_RX_TL, &i2c_base->ic_rx_tl); + writel(IC_TX_TL, &i2c_base->ic_tx_tl); + writel(IC_STOP_DET, &i2c_base->ic_intr_mask); +#ifndef CONFIG_DM_I2C + __dw_i2c_set_bus_speed(i2c_base, speed); + writel(slaveaddr, &i2c_base->ic_sar); +#endif + + /* Enable i2c */ + dw_i2c_enable(i2c_base, true); +} + +#ifndef CONFIG_DM_I2C +/* + * The legacy I2C functions. These need to get removed once + * all users of this driver are converted to DM. + */ static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { @@ -325,30 +360,9 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed); }
-/* - * i2c_init - Init function - * @speed: required i2c speed - * @slaveaddr: slave address for the device - * - * Initialization function. - */ -static void dw_i2c_init(struct i2c_adapter *adap, int speed, - int slaveaddr) +static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { - struct i2c_regs *i2c_base = i2c_get_base(adap); - - /* Disable i2c */ - dw_i2c_enable(i2c_base, false); - - writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); - writel(IC_RX_TL, &i2c_base->ic_rx_tl); - writel(IC_TX_TL, &i2c_base->ic_tx_tl); - dw_i2c_set_bus_speed(adap, speed); - writel(IC_STOP_DET, &i2c_base->ic_intr_mask); - writel(slaveaddr, &i2c_base->ic_sar); - - /* Enable i2c */ - dw_i2c_enable(i2c_base, true); + __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr); }
static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, @@ -363,9 +377,7 @@ static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len); }
-/* - * i2c_probe - Probe the i2c chip - */ +/* dw_i2c_probe - Probe the i2c chip */ static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) { struct i2c_regs *i2c_base = i2c_get_base(adap); @@ -403,3 +415,88 @@ U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, dw_i2c_write, dw_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) #endif + +#else /* CONFIG_DM_I2C */ +/* The DM I2C functions */ + +static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct dw_i2c *i2c = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0, + msg->buf, msg->len); + } else { + ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0, + msg->buf, msg->len); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct dw_i2c *i2c = dev_get_priv(bus); + + return __dw_i2c_set_bus_speed(i2c->regs, speed); +} + +static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct dw_i2c *i2c = dev_get_priv(bus); + struct i2c_regs *i2c_base = i2c->regs; + u32 tmp; + int ret; + + /* Try to read the first location of the chip */ + ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1); + if (ret) + __dw_i2c_init(i2c_base, 0, 0); + + return ret; +} + +static int designware_i2c_probe(struct udevice *bus) +{ + struct dw_i2c *priv = dev_get_priv(bus); + + /* Save base address from device-tree */ + priv->regs = (struct i2c_regs *)dev_get_addr(bus); + + __dw_i2c_init(priv->regs, 0, 0); + + return 0; +} + +static const struct dm_i2c_ops designware_i2c_ops = { + .xfer = designware_i2c_xfer, + .probe_chip = designware_i2c_probe_chip, + .set_bus_speed = designware_i2c_set_bus_speed, +}; + +static const struct udevice_id designware_i2c_ids[] = { + { .compatible = "snps,designware-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_designware) = { + .name = "i2c_designware", + .id = UCLASS_I2C, + .of_match = designware_i2c_ids, + .probe = designware_i2c_probe, + .priv_auto_alloc_size = sizeof(struct dw_i2c), + .ops = &designware_i2c_ops, +}; + +#endif /* CONFIG_DM_I2C */
This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices.
This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de --- v4: - Used new function dev_get_addr_ptr() in probe function to avoid cast. For this to work, this patch need to be applied: http://patchwork.ozlabs.org/patch/612948/ - Rebased on latest mainline
drivers/i2c/designware_i2c.c | 118 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 106 insertions(+), 12 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index d653eff..0c7cd0b 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -8,11 +8,32 @@ #include <common.h> #include <dm.h> #include <i2c.h> +#include <pci.h> #include <asm/io.h> #include "designware_i2c.h"
+struct dw_scl_sda_cfg { + u32 ss_hcnt; + u32 fs_hcnt; + u32 ss_lcnt; + u32 fs_lcnt; + u32 sda_hold; +}; + +#ifdef CONFIG_X86 +/* BayTrail HCNT/LCNT/SDA hold time */ +static struct dw_scl_sda_cfg byt_config = { + .ss_hcnt = 0x200, + .fs_hcnt = 0x55, + .ss_lcnt = 0x200, + .fs_lcnt = 0x99, + .sda_hold = 0x6, +}; +#endif + struct dw_i2c { struct i2c_regs *regs; + struct dw_scl_sda_cfg *scl_sda_cfg; };
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) @@ -43,6 +64,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) * Set the i2c speed. */ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, + struct dw_scl_sda_cfg *scl_sda_cfg, unsigned int speed) { unsigned int cntl; @@ -62,34 +84,55 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
switch (i2c_spd) { +#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */ case IC_SPEED_MODE_MAX: - cntl |= IC_CON_SPD_HS; - hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; + cntl |= IC_CON_SPD_SS; + if (scl_sda_cfg) { + hcnt = scl_sda_cfg->fs_hcnt; + lcnt = scl_sda_cfg->fs_lcnt; + } else { + hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; + } writel(hcnt, &i2c_base->ic_hs_scl_hcnt); - lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; writel(lcnt, &i2c_base->ic_hs_scl_lcnt); break; +#endif
case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS; - hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; + if (scl_sda_cfg) { + hcnt = scl_sda_cfg->ss_hcnt; + lcnt = scl_sda_cfg->ss_lcnt; + } else { + hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; + } writel(hcnt, &i2c_base->ic_ss_scl_hcnt); - lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; writel(lcnt, &i2c_base->ic_ss_scl_lcnt); break;
case IC_SPEED_MODE_FAST: default: cntl |= IC_CON_SPD_FS; - hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; + if (scl_sda_cfg) { + hcnt = scl_sda_cfg->fs_hcnt; + lcnt = scl_sda_cfg->fs_lcnt; + } else { + hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; + lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; + } writel(hcnt, &i2c_base->ic_fs_scl_hcnt); - lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; writel(lcnt, &i2c_base->ic_fs_scl_lcnt); break; }
writel(cntl, &i2c_base->ic_con);
+ /* Configure SDA Hold Time if required */ + if (scl_sda_cfg) + writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold); + /* Enable back i2c now speed set */ dw_i2c_enable(i2c_base, true);
@@ -316,7 +359,7 @@ static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) writel(IC_TX_TL, &i2c_base->ic_tx_tl); writel(IC_STOP_DET, &i2c_base->ic_intr_mask); #ifndef CONFIG_DM_I2C - __dw_i2c_set_bus_speed(i2c_base, speed); + __dw_i2c_set_bus_speed(i2c_base, NULL, speed); writel(slaveaddr, &i2c_base->ic_sar); #endif
@@ -357,7 +400,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { adap->speed = speed; - return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed); + return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed); }
static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) @@ -448,7 +491,7 @@ static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct dw_i2c *i2c = dev_get_priv(bus);
- return __dw_i2c_set_bus_speed(i2c->regs, speed); + return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed); }
static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, @@ -471,14 +514,48 @@ static int designware_i2c_probe(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus);
- /* Save base address from device-tree */ - priv->regs = (struct i2c_regs *)dev_get_addr(bus); + if (device_is_on_pci_bus(bus)) { +#ifdef CONFIG_DM_PCI + /* Save base address from PCI BAR */ + priv->regs = (struct i2c_regs *) + dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); +#ifdef CONFIG_X86 + /* Use BayTrail specific timing values */ + priv->scl_sda_cfg = &byt_config; +#endif +#endif + } else { + priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus); + }
__dw_i2c_init(priv->regs, 0, 0);
return 0; }
+static int designware_i2c_bind(struct udevice *dev) +{ + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + /* + * ToDo: + * Setting req_seq in the driver is probably not recommended. + * But without a DT alias the number is not configured. And + * using this driver is impossible for PCIe I2C devices. + * This can be removed, once a better (correct) way for this + * is found and implemented. + */ + dev->req_seq = num_cards; + sprintf(name, "i2c_designware#%u", num_cards++); + device_set_name(dev, name); + } + + return 0; +} + static const struct dm_i2c_ops designware_i2c_ops = { .xfer = designware_i2c_xfer, .probe_chip = designware_i2c_probe_chip, @@ -494,9 +571,26 @@ U_BOOT_DRIVER(i2c_designware) = { .name = "i2c_designware", .id = UCLASS_I2C, .of_match = designware_i2c_ids, + .bind = designware_i2c_bind, .probe = designware_i2c_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .ops = &designware_i2c_ops, };
+#ifdef CONFIG_X86 +static struct pci_device_id designware_pci_supported[] = { + /* Intel BayTrail has 7 I2C controller located on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x0f41) }, + { PCI_VDEVICE(INTEL, 0x0f42) }, + { PCI_VDEVICE(INTEL, 0x0f43) }, + { PCI_VDEVICE(INTEL, 0x0f44) }, + { PCI_VDEVICE(INTEL, 0x0f45) }, + { PCI_VDEVICE(INTEL, 0x0f46) }, + { PCI_VDEVICE(INTEL, 0x0f47) }, + {}, +}; + +U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported); +#endif + #endif /* CONFIG_DM_I2C */
Hello Simon,
Am 21.04.2016 um 08:19 schrieb Stefan Roese:
This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices.
This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de
v4:
- Used new function dev_get_addr_ptr() in probe function to avoid cast. For this to work, this patch need to be applied: http://patchwork.ozlabs.org/patch/612948/
Is it Ok for you, if I apply this patch through the i2c tree? Or do you want to pick up this patchserie?
bye, Heiko
Rebased on latest mainline
drivers/i2c/designware_i2c.c | 118 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 106 insertions(+), 12 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index d653eff..0c7cd0b 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -8,11 +8,32 @@ #include <common.h> #include <dm.h> #include <i2c.h> +#include <pci.h> #include <asm/io.h> #include "designware_i2c.h"
+struct dw_scl_sda_cfg {
- u32 ss_hcnt;
- u32 fs_hcnt;
- u32 ss_lcnt;
- u32 fs_lcnt;
- u32 sda_hold;
+};
+#ifdef CONFIG_X86 +/* BayTrail HCNT/LCNT/SDA hold time */ +static struct dw_scl_sda_cfg byt_config = {
- .ss_hcnt = 0x200,
- .fs_hcnt = 0x55,
- .ss_lcnt = 0x200,
- .fs_lcnt = 0x99,
- .sda_hold = 0x6,
+}; +#endif
struct dw_i2c { struct i2c_regs *regs;
struct dw_scl_sda_cfg *scl_sda_cfg; };
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
@@ -43,6 +64,7 @@ static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
- Set the i2c speed.
*/ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
struct dw_scl_sda_cfg *scl_sda_cfg, unsigned int speed)@@ -62,34 +84,55 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
switch (i2c_spd) { +#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */ case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_HS;hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
cntl |= IC_CON_SPD_SS;if (scl_sda_cfg) {hcnt = scl_sda_cfg->fs_hcnt;lcnt = scl_sda_cfg->fs_lcnt;} else {hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;}
lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;+#endif
case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS;
hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
if (scl_sda_cfg) {hcnt = scl_sda_cfg->ss_hcnt;lcnt = scl_sda_cfg->ss_lcnt;} else {hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;}
lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;writel(lcnt, &i2c_base->ic_ss_scl_lcnt); break;
case IC_SPEED_MODE_FAST: default: cntl |= IC_CON_SPD_FS;
hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
if (scl_sda_cfg) {hcnt = scl_sda_cfg->fs_hcnt;lcnt = scl_sda_cfg->fs_lcnt;} else {hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;}
lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;writel(lcnt, &i2c_base->ic_fs_scl_lcnt); break; }
writel(cntl, &i2c_base->ic_con);
- /* Configure SDA Hold Time if required */
- if (scl_sda_cfg)
writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);- /* Enable back i2c now speed set */ dw_i2c_enable(i2c_base, true);
@@ -316,7 +359,7 @@ static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) writel(IC_TX_TL, &i2c_base->ic_tx_tl); writel(IC_STOP_DET, &i2c_base->ic_intr_mask); #ifndef CONFIG_DM_I2C
- __dw_i2c_set_bus_speed(i2c_base, speed);
- __dw_i2c_set_bus_speed(i2c_base, NULL, speed); writel(slaveaddr, &i2c_base->ic_sar); #endif
@@ -357,7 +400,7 @@ static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { adap->speed = speed;
- return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed);
return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed); }
static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
@@ -448,7 +491,7 @@ static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct dw_i2c *i2c = dev_get_priv(bus);
- return __dw_i2c_set_bus_speed(i2c->regs, speed);
return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed); }
static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
@@ -471,14 +514,48 @@ static int designware_i2c_probe(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus);
- /* Save base address from device-tree */
- priv->regs = (struct i2c_regs *)dev_get_addr(bus);
- if (device_is_on_pci_bus(bus)) {
+#ifdef CONFIG_DM_PCI
/* Save base address from PCI BAR */priv->regs = (struct i2c_regs *)dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);+#ifdef CONFIG_X86
/* Use BayTrail specific timing values */priv->scl_sda_cfg = &byt_config;+#endif +#endif
} else {
priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);}
__dw_i2c_init(priv->regs, 0, 0);
return 0; }
+static int designware_i2c_bind(struct udevice *dev) +{
- static int num_cards;
- char name[20];
- /* Create a unique device name for PCI type devices */
- if (device_is_on_pci_bus(dev)) {
/** ToDo:* Setting req_seq in the driver is probably not recommended.* But without a DT alias the number is not configured. And* using this driver is impossible for PCIe I2C devices.* This can be removed, once a better (correct) way for this* is found and implemented.*/dev->req_seq = num_cards;sprintf(name, "i2c_designware#%u", num_cards++);device_set_name(dev, name);- }
- return 0;
+}
- static const struct dm_i2c_ops designware_i2c_ops = { .xfer = designware_i2c_xfer, .probe_chip = designware_i2c_probe_chip,
@@ -494,9 +571,26 @@ U_BOOT_DRIVER(i2c_designware) = { .name = "i2c_designware", .id = UCLASS_I2C, .of_match = designware_i2c_ids,
- .bind = designware_i2c_bind, .probe = designware_i2c_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .ops = &designware_i2c_ops, };
+#ifdef CONFIG_X86 +static struct pci_device_id designware_pci_supported[] = {
- /* Intel BayTrail has 7 I2C controller located on the PCI bus */
- { PCI_VDEVICE(INTEL, 0x0f41) },
- { PCI_VDEVICE(INTEL, 0x0f42) },
- { PCI_VDEVICE(INTEL, 0x0f43) },
- { PCI_VDEVICE(INTEL, 0x0f44) },
- { PCI_VDEVICE(INTEL, 0x0f45) },
- { PCI_VDEVICE(INTEL, 0x0f46) },
- { PCI_VDEVICE(INTEL, 0x0f47) },
- {},
+};
+U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported); +#endif
- #endif /* CONFIG_DM_I2C */
On Thu, Apr 21, 2016 at 3:31 PM, Heiko Schocher hs@denx.de wrote:
Hello Simon,
Am 21.04.2016 um 08:19 schrieb Stefan Roese:
This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices.
This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de
v4:
- Used new function dev_get_addr_ptr() in probe function to avoid cast. For this to work, this patch need to be applied: http://patchwork.ozlabs.org/patch/612948/
Is it Ok for you, if I apply this patch through the i2c tree? Or do you want to pick up this patchserie?
Heiko, please go ahead to pick up this series via i2c tree.
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On 21 April 2016 at 02:14, Bin Meng bmeng.cn@gmail.com wrote:
On Thu, Apr 21, 2016 at 3:31 PM, Heiko Schocher hs@denx.de wrote:
Hello Simon,
Am 21.04.2016 um 08:19 schrieb Stefan Roese:
This patch adds support for the PCI(e) based I2C cores. Which can be found for example on the Intel Bay Trail SoC. It has 7 I2C controllers implemented as PCI devices.
This patch also adds the fixed values for the timing registers for BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Marek Vasut marex@denx.de Cc: Heiko Schocher hs@denx.de
v4:
- Used new function dev_get_addr_ptr() in probe function to avoid cast. For this to work, this patch need to be applied: http://patchwork.ozlabs.org/patch/612948/
Is it Ok for you, if I apply this patch through the i2c tree? Or do you want to pick up this patchserie?
Heiko, please go ahead to pick up this series via i2c tree.
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Reviewed-by: Simon Glass sjg@chromium.org
participants (4)
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Bin Meng -
Heiko Schocher -
Simon Glass -
Stefan Roese