From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com

There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source.

Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

drivers/fpga/zynqpl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 2ff716c25228..db9bd12992f9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h>

#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Setting PCFG_PROG_B signal to high */ control = readl(&devcfg_base->ctrl); writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Setting PCFG_PROG_B signal to low */ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);

+ /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {