[U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- Patchset history
V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses getm_ram_size().
cpu/arm926ejs/orion5x/Makefile | 51 ++++++ cpu/arm926ejs/orion5x/cpu.c | 258 ++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 62 +++++++ cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++++++++ include/asm-arm/arch-orion5x/cpu.h | 187 +++++++++++++++++++++ include/asm-arm/arch-orion5x/mv88f5182.h | 40 +++++ include/asm-arm/arch-orion5x/orion5x.h | 67 ++++++++ 7 files changed, 846 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 0000000..0ed5a75 --- /dev/null +++ b/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o +COBJS-y += dram.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 0000000..deebf24 --- /dev/null +++ b/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,258 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/cache.h> +#include <u-boot/md5.h> +#include <asm/arch/orion5x.h> +#include <hush.h> + +#define BUFLEN 16 + +void reset_cpu(unsigned long ignored) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) + ; +} + +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val > 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return 0x0000ffff & j; +} + +/* + * orion5x_config_adr_windows - Configure address Windows + * + * There are 8 address windows supported by Orion5x Soc to addess different + * devices. Each window can be configured for size, BAR and remap addr + * Below configuration is standard for most of the cases + * + * If remap function not used, remap_lo must be set as base + * + * Reference Documentation: + * Mbus-L to Mbus Bridge Registers Configuration. + * (Sec 25.1 and 25.3 of Datasheet) + */ +int orion5x_config_adr_windows(void) +{ + struct orion5x_win_registers *winregs = + (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; + + /* Window 0: PCIE MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, + ORION5X_WIN_ENABLE), &winregs[0].ctrl); + writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + + /* Window 1: PCIE IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, + ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + + /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, + ORION5X_WIN_ENABLE), &winregs[2].ctrl); + writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + + /* Window 3: PCI IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, + ORION5X_WIN_ENABLE), &winregs[3].ctrl); + writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + + /* Window 4: DEV_CS0 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, + ORION5X_WIN_ENABLE), &winregs[4].ctrl); + writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + + /* Window 5: DEV_CS1 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, + ORION5X_WIN_ENABLE), &winregs[5].ctrl); + writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + + /* Window 6: DEV_CS2 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, + ORION5X_WIN_ENABLE), &winregs[6].ctrl); + writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + + /* Window 7: BOOT Memory address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, + ORION5X_WIN_ENABLE), &winregs[7].ctrl); + writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + + return 0; +} + +/* + * Orion5x identification is done through PCIE space. + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) +u32 orion5x_device_id(void) +{ + return readl(PCIE_DEV_ID_OFF) >> 16; +} + +u32 orion5x_device_rev(void) +{ + return readl(PCIE_DEV_REV_OFF) & 0xff; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) + +int print_cpuinfo(void) +{ + char dev_str[] = "0x0000"; + char rev_str[] = "0x00"; + char *dev_name = NULL; + char *rev_name = NULL; + + u32 dev = orion5x_device_id(); + u32 rev = orion5x_device_rev(); + + if (dev == MV88F5181_DEV_ID) { + dev_name = "MV88F5181"; + if (rev == MV88F5181_REV_B1) + rev_name = "B1"; + else if (rev == MV88F5181L_REV_A1) { + dev_name = "MV88F5181L"; + rev_name = "A1"; + } else if (rev == MV88F5181L_REV_A0) { + dev_name = "MV88F5181L"; + rev_name = "A0"; + } + } else if (dev == MV88F5182_DEV_ID) { + dev_name = "MV88F5182"; + if (rev == MV88F5182_REV_A2) + rev_name = "A2"; + } else if (dev == MV88F5281_DEV_ID) { + dev_name = "MV88F5281"; + if (rev == MV88F5281_REV_D2) + rev_name = "D2"; + else if (rev == MV88F5281_REV_D1) + rev_name = "D1"; + else if (rev == MV88F5281_REV_D0) + rev_name = "D0"; + } else if (dev == MV88F6183_DEV_ID) { + dev_name = "MV88F6183"; + if (rev == MV88F6183_REV_B0) + rev_name = "B0"; + } + if (dev_name == NULL) { + sprintf(dev_str, "0x%04x", dev); + dev_name = dev_str; + } + if (rev_name == NULL) { + sprintf(rev_str, "0x%02x", rev); + rev_name = rev_str; + } + + printf("SoC: Orion5x %s-%s\n", dev_name, rev_name); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + /* Enable and invalidate L2 cache in write through mode */ + invalidate_l2_cache(); + + orion5x_config_adr_windows(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + u32 temp; + + /*CPU streaming & write allocate */ + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 28); /* disable wr alloc */ + writefr_extra_feature_reg(temp); + + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 29); /* streaming disabled */ + writefr_extra_feature_reg(temp); + + /* L2Cache settings */ + temp = readfr_extra_feature_reg(); + /* Disable L2C pre fetch - Set bit 24 */ + temp |= (1 << 24); + /* enable L2C - Set bit 22 */ + temp |= (1 << 22); + writefr_extra_feature_reg(temp); + + icache_enable(); + /* Change reset vector to address 0x0 */ + temp = get_cr(); + set_cr(temp & ~CR_V); + + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c new file mode 100644 index 0000000..af4a788 --- /dev/null +++ b/cpu/arm926ejs/orion5x/dram.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/arch/orion5x.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08)) +/* + * orion5x_sdram_bar - reads SDRAM Base Address Register + */ +u32 orion5x_sdram_bar(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank)); + return result; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); + gd->bd->bi_dram[i].size = get_ram_size( + gd->bd->bi_dram[i].start, + CONFIG_MAX_RAM_BANK_SIZE); + } + return 0; +} diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c new file mode 100644 index 0000000..6cf0cb4 --- /dev/null +++ b/cpu/arm926ejs/orion5x/timer.c @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/orion5x.h> + +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ + +/* Timer reload and current value registers */ +struct orion5x_tmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct orion5x_tmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct orion5x_tmr_val tmr[2]; + u32 wdt_reload; + u32 wdt_val; +}; + +struct orion5x_tmr_registers *orion5x_tmr_regs = + (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) +#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) +#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val) + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* + * ARM Timer\Watchdog Reload Register + * CNTMR_RELOAD_REG (TRR) + */ +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* + * ARM Timer\Watchdog Register + * CNTMR_VAL_REG (TVRG) + */ +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff + +static inline ulong read_timer(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)) + / (CONFIG_SYS_TCLK / 1000); +} + +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = read_timer(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +static inline ulong uboot_cntr_val(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)); +} + +void __udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = uboot_cntr_val(); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (uboot_cntr_val() < current) + ; + while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val()) + ; + } else { + while (uboot_cntr_val() > (current - delayticks)) + ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + unsigned int cntmrctrl; + + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + cntmrctrl = readl(CNTMR_CTRL_REG); + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); + writel(cntmrctrl, CNTMR_CTRL_REG); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h new file mode 100644 index 0000000..0a33999 --- /dev/null +++ b/include/asm-arm/arch-orion5x/cpu.h @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirorion5x_ood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ORION5X_CPU_H +#define _ORION5X_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) + +#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum orion5x_cpu_winen { + ORION5X_WIN_DISABLE, + ORION5X_WIN_ENABLE +}; + +enum orion5x_cpu_target { + ORION5X_TARGET_DRAM = 0, + ORION5X_TARGET_DEVICE = 1, + ORION5X_TARGET_PCI = 3, + ORION5X_TARGET_PCIE = 4, + ORION5X_TARGET_SASRAM = 9 +}; + +enum orion5x_cpu_attrib { + ORION5X_ATTR_DRAM_CS0 = 0x0e, + ORION5X_ATTR_DRAM_CS1 = 0x0d, + ORION5X_ATTR_DRAM_CS2 = 0x0b, + ORION5X_ATTR_DRAM_CS3 = 0x07, + ORION5X_ATTR_PCI_MEM = 0x59, + ORION5X_ATTR_PCI_IO = 0x51, + ORION5X_ATTR_PCIE_MEM = 0x59, + ORION5X_ATTR_PCIE_IO = 0x51, + ORION5X_ATTR_SASRAM = 0x00, + ORION5X_ATTR_DEV_CS0 = 0x1e, + ORION5X_ATTR_DEV_CS1 = 0x1d, + ORION5X_ATTR_DEV_CS2 = 0x1b, + ORION5X_ATTR_BOOTROM = 0x0f +}; + +/* + * Default Device Address MAP BAR values + */ +#define ORION5X_DEFADR_PCIE_MEM 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCIE_IO 0xf0000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_IO (64*1024) + +#define ORION5X_DEFADR_PCI_MEM 0x98000000 +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCI_IO 0xf0100000 +#define ORION5X_DEFSZ_PCI_IO (64*1024) + +#define ORION5X_DEFADR_DEV_CS0 0xfa000000 +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) + +#define ORION5X_DEFADR_DEV_CS1 0xf8000000 +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) + +#define ORION5X_DEFADR_DEV_CS2 0xfa800000 +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) + +#define ORION5X_DEFADR_BOOTROM 0xFFF80000 +#define ORION5X_DEFSZ_BOOTROM (512*1024) + +/* + * PCIE registers are used for SoC device ID and revision + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) + +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +/* + * read feroceon core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * AHB to Mbus Bridge Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + * Note: only windows 0 and 1 have remap capability. + */ +struct orion5x_win_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + */ +struct orion5x_cpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ +}; + +/* + * functions + */ +void reset_cpu(unsigned long ignored); +u32 orion5x_device_id(void); +u32 orion5x_device_rev(void); +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +#endif /* __ASSEMBLY__ */ +#endif /* _ORION5X_CPU_H */ diff --git a/include/asm-arm/arch-orion5x/mv88f5182.h b/include/asm-arm/arch-orion5x/mv88f5182.h new file mode 100644 index 0000000..b16b23f --- /dev/null +++ b/include/asm-arm/arch-orion5x/mv88f5182.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood 88F6182 support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * Header file for Feroceon CPU core 88F5182 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_88F5182_H +#define _CONFIG_88F5182_H + +/* SOC specific definations */ +#define F88F5182_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_88F5182_H */ diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 0000000..d7b5509 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * Header file for Marvell's Orion SoC with Feroceon CPU core. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ORION5X_H +#define _ASM_ARCH_ORION5X_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined(CONFIG_FEROCEON) +#include <asm/arch/cpu.h> + +/* SOC specific definations */ +#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) + +/* Documented registers */ +#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) +#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) +#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) +#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) +#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) +#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) +#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) +#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) +#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) +#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) +#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) +#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) +#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) + +#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) + +#if defined(CONFIG_88F5182) +#include <asm/arch/mv88f5182.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_FEROCEON */ +#endif /* _ASM_ARCH_ORION5X_H */
This patch provides access to the 16550-compatible serial device of the Orion5x SoC.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- drivers/serial/serial.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dd5f332..18686a2 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -30,6 +30,9 @@ #ifdef CONFIG_KIRKWOOD #include <asm/arch/kirkwood.h> #endif +#ifdef CONFIG_ORION5X +#include <asm/arch/orion5x.h> +#endif
#if defined (CONFIG_SERIAL_MULTI) #include <serial.h>
This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses CONFIG_FLASH_CFI_LEGACY as the Macronix MX29LV400 used on ED Mini V2 is not CFI compliant (mixes 16 and 8 bit behaviors).
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 58 ++++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 88 +++++++++ board/LaCie/edminiv2/edminiv2.h | 59 ++++++ board/LaCie/edminiv2/lowlevel_init.S | 324 ++++++++++++++++++++++++++++++++++ include/configs/edminiv2.h | 147 +++++++++++++++ 9 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 board/LaCie/edminiv2/lowlevel_init.S create mode 100644 include/configs/edminiv2.h
diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d..5460c22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -514,6 +514,10 @@ Unknown / orphaned boards: # Board CPU # #########################################################################
+Albert ARIBAUD albert.aribaud@free.fr + + edminiv2 ARM926EJS (Orion5x SoC) + Rowel Atienza rowel@diwalabs.com
armadillo ARM720T diff --git a/MAKEALL b/MAKEALL index ab1bb6f..e85d585 100755 --- a/MAKEALL +++ b/MAKEALL @@ -552,6 +552,7 @@ LIST_ARM9=" \ cp946es \ cp966 \ da830evm \ + edminiv2 \ imx27lite \ lpd7a400 \ mv88f6281gtw_ge \ diff --git a/Makefile b/Makefile index ed6156f..917854f 100644 --- a/Makefile +++ b/Makefile @@ -2927,6 +2927,9 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+edminiv2_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) LaCie orion5x + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile new file mode 100644 index 0000000..41eafe0 --- /dev/null +++ b/board/LaCie/edminiv2/Makefile @@ -0,0 +1,58 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edminiv2.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS := lowlevel_init.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk new file mode 100644 index 0000000..91f2db9 --- /dev/null +++ b/board/LaCie/edminiv2/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c new file mode 100644 index 0000000..988de52 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/orion5x.h> +#include "edminiv2.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH + * which CFI does not properly detect, hence the LEGACY config. + */ +#if defined(CONFIG_FLASH_CFI_LEGACY) +#include <flash.h> +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; + int sect; + + if (base != CONFIG_SYS_FLASH_BASE) + return 0; + + info->size = 0; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { + info->start[sect] = base+info->size; + info->size += sectsz[sect]; + } + info->flash_id = 0x01000000; + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->buffer_size = 0; + info->erase_blk_tout = 1000; + info->write_tout = 10; + info->buffer_write_tout = 300; + info->vendor = CFI_CMDSET_AMD_LEGACY; + info->cmd_reset = 0xF0; + info->interface = FLASH_CFI_X8; + info->legacy_unlock = 0; + info->manufacturer_id = 0x22; + info->device_id = 0xBA; + info->device_id2 = 0; + info->ext_addr = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0000; + info->addr_unlock1 = 0x00000aaa; + info->addr_unlock2 = 0x00000555; + info->name = "MX29LV400CB"; + + return 1; +} +#endif /* CONFIG_SYS_FLASH_CFI */ + +int board_init(void) +{ + /* arch number of board */ + gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..88f4cee --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_H +#define __EDMINIV2_H + +/* + * Internal register base - Linux expects 0xf1000000 + */ + +#define EDMINIV2_INTERNAL_BASE 0xf1000000 + +/* + * MPPs: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 0 for others + */ + +#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_23 0x00000000 + +/* + * GPIOs: + * - GPIO3 is input (RTC interrupt) + * - GPIO16 is Power LED control (0 = on, 1 = off) + * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) + * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) + * - Last GPIO is 26, further bits are supposed to be 0. + * Default is LED ON + */ + +#define EDMINIV2_OE 0x03fcffff +#define EDMINIV2_OE_VAL 0x00020000 + +#endif /* __EDMINIV2_H */ diff --git a/board/LaCie/edminiv2/lowlevel_init.S b/board/LaCie/edminiv2/lowlevel_init.S new file mode 100644 index 0000000..891423f --- /dev/null +++ b/board/LaCie/edminiv2/lowlevel_init.S @@ -0,0 +1,324 @@ +/******************************************************************************* +Copyright (c) Albert ARIBAUD albert.aribaud@free.fr +Redistributed under GPLv2, pursuant to the licensing terms +if the original Marvell U-boot code which is: +Copyright (C) Marvell International Ltd. and its affiliates +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include "edminiv2.h" + +/* + * Configuration values for SDRAM access setup + */ + +#define SDRAM_CONFIG 0x3148400 +#define SDRAM_MODE 0x62 +#define SDRAM_CONTROL 0x4041000 +#define SDRAM_TIME_CTRL_LOW 0x11602220 +#define SDRAM_TIME_CTRL_HI 0x40c +#define SDRAM_OPEN_PAGE_EN 0x0 +/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */ +#define SDRAM_BANK0_SIZE 0x3ff0001 +#define SDRAM_ADDR_CTRL 0x10 + +#define SDRAM_OP_NOP 0x05 +#define SDRAM_OP_SETMODE 0x03 + +#define SDRAM_PAD_CTRL_WR_EN 0x80000000 +#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000 +#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f +#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0 + +/* + * For Guideline MEM-3 - Drive Strength value + */ + +#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000 +#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000 + +/* + * For Guideline MEM-4 - DQS Reference Delay Tuning + */ + +#define MSAR_ARMDDRCLCK_MASK 0x000000f0 +#define MSAR_ARMDDRCLCK_H_MASK 0x00000100 + +#define MSAR_ARMDDRCLCK_333_167 0x00000000 +#define MSAR_ARMDDRCLCK_500_167 0x00000030 +#define MSAR_ARMDDRCLCK_667_167 0x00000060 +#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0 +#define MSAR_ARMDDRCLCK_400_200 0x00000010 +#define MSAR_ARMDDRCLCK_600_200 0x00000050 +#define MSAR_ARMDDRCLCK_800_200 0x00000070 + +#define FTDLL_DDR1_166MHZ 0x0047F001 + +#define FTDLL_DDR1_200MHZ 0x0044D001 + +/* + * MPPs: + * - MPPs 12 to 15 are SATA LEDs (mode 5) + * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for + * MPP16 to MPP19, mode 0 for others + */ + +#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_19 0x00005555 + +/* + * GPIOs: + * All GPIOs are inputs except: + * - MPP16: Power LED control (0 = On, 1 = Off) + * - MPP17: Power LED control select (0 = CPLD, 1 = GPIO16) + * Default setting puts LED under CPLD control. + */ + +#define EDMINIV2_GPIO_OUT_ENABLE 0x03FCFFFF + +/* + * Low-level init happens right after start.S has switched to SVC32, + * flushed and disabled caches and disabled MMU. We're still running + * from the boot chip select, so the first thing we should do is set + * up RAM for us to relocate into. + */ + +.globl lowlevel_init + +lowlevel_init: + + /* Use 'r4 as the base for internal register accesses */ + ldr r4, =EDMINIV2_INTERNAL_BASE + + /* move internal registers from the default 0xD0000000 + * to their intended location of 0xf1000000 */ + ldr r3, =0xD0000000 + add r3, r3, #0x20000 + str r4, [r3, #0x80] + + /* Use R3 as the base for Device Bus registers */ + add r3, r4, #0x10000 + + /* init MPPs */ + ldr r6, =EDMINIV2_MPP0_7 + str r6, [r3, #0x000] + ldr r6, =EDMINIV2_MPP8_15 + str r6, [r3, #0x004] + ldr r6, =EDMINIV2_MPP16_23 + str r6, [r3, #0x050] + + /* init GPIOs */ + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE + str r6, [r3, #0x104] + + /* Use R3 as the base for DRAM registers */ + add r3, r4, #0x01000 + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + str r6, [r3, #0x480] + + /* Use R3 as the base for PCI registers */ + add r3, r4, #0x31000 + + /* Disable arbiter */ + ldr r6, =0x00000030 + str r6, [r3, #0xd00] + + /* Use R3 as the base for DRAM registers */ + add r3, r4, #0x01000 + + /* set all dram windows to 0 */ + mov r6, #0 + str r6, [r3, #0x504] + str r6, [r3, #0x50C] + str r6, [r3, #0x514] + str r6, [r3, #0x51C] + + /* 1) Configure SDRAM */ + ldr r6, =SDRAM_CONFIG + str r6, [r3, #0x400] + + /* 2) Set SDRAM Control reg */ + ldr r6, =SDRAM_CONTROL + str r6, [r3, #0x404] + + /* 3) Write SDRAM address control register */ + ldr r6, =SDRAM_ADDR_CTRL + str r6, [r3, #0x410] + + /* 4) Write SDRAM bank 0 size register */ + ldr r6, =SDRAM_BANK0_SIZE + str r6, [r3, #0x504] + /* keep other banks disabled */ + + /* 5) Write SDRAM open pages control register */ + ldr r6, =SDRAM_OPEN_PAGE_EN + str r6, [r3, #0x414] + + /* 6) Write SDRAM timing Low register */ + ldr r6, =SDRAM_TIME_CTRL_LOW + str r6, [r3, #0x408] + + /* 7) Write SDRAM timing High register */ + ldr r6, =SDRAM_TIME_CTRL_HI + str r6, [r3, #0x40C] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + ldr r6, =SDRAM_OP_NOP + str r6, [r3, #0x418] + + /* 8.2 poll SDRAM operation until back in 'normal' mode. */ +1: + ldr r6, [r3, #0x418] + cmp r6, #0 + bne 1b + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r6, =SDRAM_MODE + str r6, [r3, #0x41C] + + /* 8.4 Set new mode */ + ldr r6, =SDRAM_OP_SETMODE + str r6, [r3, #0x418] + + /* 8.5 poll SDRAM operation until back in 'normal' mode. */ +2: + ldr r6, [r3, #0x418] + cmp r6, #0 + bne 2b + + /* DDR SDRAM Address/Control Pads Calibration */ + ldr r6, [r3, #0x4C0] + + /* Set Bit [31] to make the register writable */ + orr r6, r6, #SDRAM_PAD_CTRL_WR_EN + str r6, [r3, #0x4C0] + + bic r6, r6, #SDRAM_PAD_CTRL_WR_EN + bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN + bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK + bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ + orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ + + /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ + orr r6, r6, r1 + str r6, [r3, #0x4C0] + + /* DDR SDRAM Data Pads Calibration */ + ldr r6, [r3, #0x4C4] + + /* Set Bit [31] to make the register writable */ + orr r6, r6, #SDRAM_PAD_CTRL_WR_EN + str r6, [r3, #0x4C4] + + bic r6, r6, #SDRAM_PAD_CTRL_WR_EN + bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN + bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK + bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 + orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ + + /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ + orr r6, r6, r1 + + str r6, [r3, #0x4C4] + + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + + ldr r1, =DDR1_PAD_STRENGTH_DEFAULT + + /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ + ldr r6, [r3, #0x4C0] + orr r6, r6, #SDRAM_PAD_CTRL_WR_EN + str r6, [r3, #0x4C0] + + /* Correct strength and disable writes again */ + bic r6, r6, #SDRAM_PAD_CTRL_WR_EN + bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK + orr r6, r6, r1 + str r6, [r3, #0x4C0] + + /* Enable writes to DDR SDRAM Data Pads Calibration register */ + ldr r6, [r3, #0x4C4] + orr r6, r6, #SDRAM_PAD_CTRL_WR_EN + str r6, [r3, #0x4C4] + + /* Correct strength and disable writes again */ + bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK + bic r6, r6, #SDRAM_PAD_CTRL_WR_EN + orr r6, r6, r1 + str r6, [r3, #0x4C4] + + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + + /* Get the "sample on reset" register for the DDR frequancy */ + ldr r3, =0x10000 + ldr r6, [r3, #0x010] + ldr r1, =MSAR_ARMDDRCLCK_MASK + and r1, r6, r1 + + ldr r6, =FTDLL_DDR1_166MHZ + cmp r1, #MSAR_ARMDDRCLCK_333_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_500_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_667_167 + beq 3f + + ldr r6, =FTDLL_DDR1_200MHZ + cmp r1, #MSAR_ARMDDRCLCK_400_200_1 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_400_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_600_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_800_200 + beq 3f + + ldr r6, =0 + +3: + /* Use R3 as the base for DRAM registers */ + add r3, r4, #0x01000 + + ldr r2, [r3, #0x484] + orr r2, r2, r6 + str r2, [r3, #0x484] + + /* Return to U-boot via saved link register */ + mov pc, lr diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..53e0046 --- /dev/null +++ b/include/configs/edminiv2.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_EDMINIV2_H +#define _CONFIG_EDMINIV2_H + +/* + * Version number information + */ + +#define CONFIG_IDENT_STRING " EDMiniV2" + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON 1 /* CPU Core subversion */ +#define CONFIG_ORION5X 1 /* SOC Family Name */ +#define CONFIG_88F5182 1 /* SOC Name */ +#define CONFIG_MACH_EDMINIV2 1 /* Machine type */ + +/* + * CLKs configurations + */ + +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +/* + * FLASH configuration + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000 +#define CONFIG_SYS_FLASH_SECTSZ \ + {16384, 8192, 8192, 32768, \ + 65536, 65536, 65536, 65536, 65536, 65536, 65536} + +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration - using default command set for now + */ +#include <config_cmd_default.h> +/* + * Disabling some default commands for staggered bring-up + */ +#undef CONFIG_CMD_BOOTD /* no bootd since no net */ +#undef CONFIG_CMD_NET /* no net since no eth */ +#undef CONFIG_CMD_NFS /* no NFS since no net */ + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_STACKSIZE 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x007fffff +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 +#define CONFIG_SYS_MAXARGS 16 + +#endif /* _CONFIG_EDMINIV2_H */
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Albert Aribaud Sent: Sunday, January 10, 2010 9:34 PM To: U-Boot@lists.denx.de Subject: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board
This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses CONFIG_FLASH_CFI_LEGACY as the Macronix MX29LV400 used on ED Mini V2 is not CFI compliant (mixes 16 and 8 bit behaviors).
Signed-off-by: Albert Aribaud albert.aribaud@free.fr
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 58 ++++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 88 +++++++++ board/LaCie/edminiv2/edminiv2.h | 59 ++++++ board/LaCie/edminiv2/lowlevel_init.S | 324 ++++++++++++++++++++++++++++++++++ include/configs/edminiv2.h | 147 +++++++++++++++ 9 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 board/LaCie/edminiv2/lowlevel_init.S create mode 100644 include/configs/edminiv2.h
....snip...
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk new file mode 100644 index 0000000..91f2db9 --- /dev/null +++ b/board/LaCie/edminiv2/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +#
+TEXT_BASE = 0x00600000
??? As reported earlier, is this okay for you? And do not want to lower it?
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c new file mode 100644 index 0000000..988de52 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.c @@ -0,0 +1,88 @@ +/*
- Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- MA 02110-1301 USA
- */
+#include <common.h> +#include <miiphy.h> +#include <asm/arch/orion5x.h> +#include "edminiv2.h"
+DECLARE_GLOBAL_DATA_PTR;
+/*
- The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
- which CFI does not properly detect, hence the LEGACY config.
- */
+#if defined(CONFIG_FLASH_CFI_LEGACY) +#include <flash.h> +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{
int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;int sect;if (base != CONFIG_SYS_FLASH_BASE)return 0;info->size = 0;info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {info->start[sect] = base+info->size;info->size += sectsz[sect];}info->flash_id = 0x01000000;info->portwidth = FLASH_CFI_8BIT;info->chipwidth = FLASH_CFI_BY8;info->buffer_size = 0;info->erase_blk_tout = 1000;info->write_tout = 10;info->buffer_write_tout = 300;info->vendor = CFI_CMDSET_AMD_LEGACY;info->cmd_reset = 0xF0;info->interface = FLASH_CFI_X8;info->legacy_unlock = 0;info->manufacturer_id = 0x22;info->device_id = 0xBA;info->device_id2 = 0;info->ext_addr = 0;info->cfi_version = 0x3133;info->cfi_offset = 0x0000;info->addr_unlock1 = 0x00000aaa;info->addr_unlock2 = 0x00000555;info->name = "MX29LV400CB";
initialization with magic numbers should be provided with some comments for better understanding.
return 1;+} +#endif /* CONFIG_SYS_FLASH_CFI */
+int board_init(void) +{
/* arch number of board */gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;/* adress of boot parameters */gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100;return 0;+} diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..88f4cee --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,59 @@ +/*
- Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- MA 02110-1301 USA
- */
+#ifndef __EDMINIV2_H +#define __EDMINIV2_H
+/*
- Internal register base - Linux expects 0xf1000000
- */
+#define EDMINIV2_INTERNAL_BASE 0xf1000000
+/*
- MPPs:
- MPPs 12 to 15 are SATA LEDs (mode 5)
- Others are GPIO/unused (mode 3 for MPP0, mode 0 for others
- */
+#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_23 0x00000000
+/*
- GPIOs:
- GPIO3 is input (RTC interrupt)
- GPIO16 is Power LED control (0 = on, 1 = off)
- GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- Last GPIO is 26, further bits are supposed to be 0.
- Default is LED ON
- */
+#define EDMINIV2_OE 0x03fcffff +#define EDMINIV2_OE_VAL 0x00020000
+#endif /* __EDMINIV2_H */ diff --git a/board/LaCie/edminiv2/lowlevel_init.S b/board/LaCie/edminiv2/lowlevel_init.S new file mode 100644 index 0000000..891423f --- /dev/null +++ b/board/LaCie/edminiv2/lowlevel_init.S
...snip...
+/*
- MPPs:
- MPPs 12 to 15 are SATA LEDs (mode 5)
- Others are GPIO/unused (mode 3 for MPP0, mode 5 for
- MPP16 to MPP19, mode 0 for others
- */
+#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_19 0x00005555
Code repeated, this is already defined in edminiv2.h (reported earlier for V3)
+/*
- GPIOs:
- All GPIOs are inputs except:
- MPP16: Power LED control (0 = On, 1 = Off)
- MPP17: Power LED control select (0 = CPLD, 1 = GPIO16)
- Default setting puts LED under CPLD control.
- */
+#define EDMINIV2_GPIO_OUT_ENABLE 0x03FCFFFF
Please defined all GPIO stuff at one place
+/*
- Low-level init happens right after start.S has switched to SVC32,
- flushed and disabled caches and disabled MMU. We're still running
- from the boot chip select, so the first thing we should do is set
- up RAM for us to relocate into.
- */
+.globl lowlevel_init
+lowlevel_init:
/* Use 'r4 as the base for internal register accesses */ldr r4, =EDMINIV2_INTERNAL_BASE/* move internal registers from the default 0xD0000000* to their intended location of 0xf1000000 */ldr r3, =0xD0000000add r3, r3, #0x20000str r4, [r3, #0x80]/* Use R3 as the base for Device Bus registers */add r3, r4, #0x10000/* init MPPs */ldr r6, =EDMINIV2_MPP0_7str r6, [r3, #0x000]ldr r6, =EDMINIV2_MPP8_15str r6, [r3, #0x004]ldr r6, =EDMINIV2_MPP16_23str r6, [r3, #0x050]/* init GPIOs */ldr r6, =EDMINIV2_GPIO_OUT_ENABLEstr r6, [r3, #0x104]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/*DDR SDRAM Initialization Control */ldr r6, =0x00000001str r6, [r3, #0x480]/* Use R3 as the base for PCI registers */add r3, r4, #0x31000/* Disable arbiter */ldr r6, =0x00000030str r6, [r3, #0xd00]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/* set all dram windows to 0 */mov r6, #0str r6, [r3, #0x504]str r6, [r3, #0x50C]str r6, [r3, #0x514]str r6, [r3, #0x51C]/* 1) Configure SDRAM */ldr r6, =SDRAM_CONFIGstr r6, [r3, #0x400]/* 2) Set SDRAM Control reg */ldr r6, =SDRAM_CONTROLstr r6, [r3, #0x404]/* 3) Write SDRAM address control register */ldr r6, =SDRAM_ADDR_CTRLstr r6, [r3, #0x410]/* 4) Write SDRAM bank 0 size register */ldr r6, =SDRAM_BANK0_SIZEstr r6, [r3, #0x504]/* keep other banks disabled *//* 5) Write SDRAM open pages control register */ldr r6, =SDRAM_OPEN_PAGE_ENstr r6, [r3, #0x414]/* 6) Write SDRAM timing Low register */ldr r6, =SDRAM_TIME_CTRL_LOWstr r6, [r3, #0x408]/* 7) Write SDRAM timing High register */ldr r6, =SDRAM_TIME_CTRL_HIstr r6, [r3, #0x40C]/* 8) Write SDRAM mode register *//* The CPU must not attempt to change the SDRAM Moderegister setting */
/* prior to DRAM controller completion of the DRAMinitialization */
/* sequence. To guarantee this restriction, it isrecommended that */
/* the CPU sets the SDRAM Operation register to NOPcommand, performs */
/* read polling until the register is back in Normaloperation value, */
/* and then sets SDRAM Mode register to its newvalue. */
/* 8.1 write 'nop' to SDRAM operation */ldr r6, =SDRAM_OP_NOPstr r6, [r3, #0x418]/* 8.2 poll SDRAM operation until back in 'normal' mode. */+1:
ldr r6, [r3, #0x418]cmp r6, #0bne 1b/* 8.3 Now its safe to write new value to SDRAM Moderegister */
ldr r6, =SDRAM_MODEstr r6, [r3, #0x41C]/* 8.4 Set new mode */ldr r6, =SDRAM_OP_SETMODEstr r6, [r3, #0x418]/* 8.5 poll SDRAM operation until back in 'normal' mode. */+2:
ldr r6, [r3, #0x418]cmp r6, #0bne 2b/* DDR SDRAM Address/Control Pads Calibration */ldr r6, [r3, #0x4C0]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26 /* r1[5:0]<DrvN> =r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C0]/* DDR SDRAM Data Pads Calibration */ldr r6, [r3, #0x4C4]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> *//* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-3) Drive StrengthValue */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ldr r1, =DDR1_PAD_STRENGTH_DEFAULT/* Enable writes to DDR SDRAM Addr/Ctrl PadsCalibration register */
ldr r6, [r3, #0x4C0]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r6, r6, r1str r6, [r3, #0x4C0]/* Enable writes to DDR SDRAM Data Pads Calibration register */ldr r6, [r3, #0x4C4]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r6, r6, #SDRAM_PAD_CTRL_WR_ENorr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-4) DQS ReferenceDelay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 *//* Get the "sample on reset" register for the DDRfrequancy */
ldr r3, =0x10000ldr r6, [r3, #0x010]ldr r1, =MSAR_ARMDDRCLCK_MASKand r1, r6, r1ldr r6, =FTDLL_DDR1_166MHZcmp r1, #MSAR_ARMDDRCLCK_333_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_500_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_667_167beq 3fldr r6, =FTDLL_DDR1_200MHZcmp r1, #MSAR_ARMDDRCLCK_400_200_1beq 3fcmp r1, #MSAR_ARMDDRCLCK_400_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_600_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_800_200beq 3f
As reported earlier comment for v3, this should only have simple DRAM initialization, which is only dependency to copy and start binary. MPP and GPIO inits should be moved to edminv2.c. Common to SoC stuff to be moved to cpu.c/h
ldr r6, =0+3:
/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000ldr r2, [r3, #0x484]orr r2, r2, r6str r2, [r3, #0x484]/* Return to U-boot via saved link register */mov pc, lrdiff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h new file mode 100644 index 0000000..53e0046 --- /dev/null +++ b/include/configs/edminiv2.h
...snip...
+/*
- FLASH configuration
- */
+#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BASE 0xfff80000
...snip...
+#define CONFIG_SYS_MEMTEST_END 0x007fffff +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
I still do not understand who will fectch u-boot binary to TEXT_BASE? (reported earlier) Is this flash XIP? Does u-boot binary below 16k? What is the size of flash? Pls refer my comments for v3
Regards.. Prafulla . .
Prafulla Wadaskar a écrit :
I still do not understand who will fectch u-boot binary to TEXT_BASE? (reported earlier) Is this flash XIP? Does u-boot binary below 16k? What is the size of flash? Pls refer my comments for v3
I thought I'd explained that already, haven't I? At power-up a ROM code at FFFF0000 (64KB of ROM taking precedence over CS0, as seen from JTAG) does a few checks then jumps to FFF90000, which is the NOR Flash. The U-boot image is mapped and flashed so that the entry point is at FFF90000. The entry point then does further inits (some under condition that SKIP_CONFIG_LOWLEVEL_INIT is not defined), initializes RAM, relocates code to TEXT_BASE (if CONFIG_SKIP_RELOCATE_UBOOT is not defined) and then jumps to it.
Amicalement,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.aribaud@free.fr] Sent: Monday, January 11, 2010 5:42 PM To: Prafulla Wadaskar Cc: U-Boot@lists.denx.de Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board
Prafulla Wadaskar a écrit :
I still do not understand who will fectch u-boot binary to
TEXT_BASE? (reported earlier)
Is this flash XIP? Does u-boot binary below 16k? What is
the size of flash?
Pls refer my comments for v3
I thought I'd explained that already, haven't I? At power-up a ROM code at FFFF0000 (64KB of ROM taking precedence over CS0, as seen from JTAG) does a few checks then jumps to FFF90000, which is the NOR Flash. The U-boot image is mapped and flashed so that the entry point is at FFF90000. The entry point then does further inits (some under condition that SKIP_CONFIG_LOWLEVEL_INIT is not defined), initializes RAM, relocates code to TEXT_BASE (if CONFIG_SKIP_RELOCATE_UBOOT is not defined) and then jumps to it.
Okay. I am referring to 5281 users manual section 17.2.1 and that does not have these details. Or is ROM sitting at 0xffff0000 already have a code that does above? Or Are you pointing to Boot ROM Support that 5281 have?
Do you have any reference for all this explanation? Or can you point any reference for me to look for?
Regards.. Prafulla . .
Amicalement,
Albert.
Hi Prafulla,
Prafulla Wadaskar a écrit :
-----Original Message----- From: Albert ARIBAUD [mailto:albert.aribaud@free.fr] Sent: Monday, January 11, 2010 5:42 PM To: Prafulla Wadaskar Cc: U-Boot@lists.denx.de Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board
Prafulla Wadaskar a écrit :
I still do not understand who will fectch u-boot binary to
TEXT_BASE? (reported earlier)
Is this flash XIP? Does u-boot binary below 16k? What is
the size of flash?
Pls refer my comments for v3
I thought I'd explained that already, haven't I? At power-up a ROM code at FFFF0000 (64KB of ROM taking precedence over CS0, as seen from JTAG) does a few checks then jumps to FFF90000, which is the NOR Flash. The U-boot image is mapped and flashed so that the entry point is at FFF90000. The entry point then does further inits (some under condition that SKIP_CONFIG_LOWLEVEL_INIT is not defined), initializes RAM, relocates code to TEXT_BASE (if CONFIG_SKIP_RELOCATE_UBOOT is not defined) and then jumps to it.
Okay. I am referring to 5281 users manual section 17.2.1 and that does not have these details.
Watch out: ED Mini is 5182-based, not 5281. However, the 5182 docs don't mention this FFF90000 business either. This was found by readint the source code made available by LaCie for this board (more below).
Or is ROM sitting at 0xffff0000 already have a code that does above? Or Are you pointing to Boot ROM Support that 5281 have?
The ED Mini only has Flash sitting on BOOTCS -- not CS0 as I mistakenly wrote: CS0 is for the 64M SDRAM.
The final mapping of the 512KB Flash is FFF80000. However, the 5182 user manual says BOOTCS at reset is at F8000000-FFFFFFFF, which means the Flash will mirror every 512Kb over this area, thus *normally* FFFF0000 should be the last 64K of the Flash. However the U-boot image does not contain reset vectors there -- they're at FFF90000, and built so as to be there -- and a JTAG reset execution path analysis shows different code at FFFF0000 than what e.g. an U-boot 'md.b ffff0000 100' will show. Following the reset code shows a machine ID check and, in the case of a 5182, a jump to FFF90000, which is both the last mirror of the Flash before BOOTCS reprogramming and and its final location afterward.
Do you have any reference for all this explanation? Or can you point any reference for me to look for?
I'm afraid there's no documented reference. My reference for building U-boot to start from NOR Flash at FFF90000 comes from the (much older) U-boot source code provided by LaCie, which did not contain explanations as to the reason for starting at this address; and the existence of ROM code was later observed through JTAG reset execution path analysis.
Regards.. Prafulla . .
Amicalement,
Prafulla Wadaskar a écrit :
diff --git a/board/LaCie/edminiv2/config.mk
+TEXT_BASE = 0x00600000
??? As reported earlier, is this okay for you? And do not want to lower it?
Fixed for good this time. :)
diff --git a/board/LaCie/edminiv2/edminiv2.c
info->flash_id = 0x01000000;info->portwidth = FLASH_CFI_8BIT;info->chipwidth = FLASH_CFI_BY8;info->buffer_size = 0;info->erase_blk_tout = 1000;info->write_tout = 10;info->buffer_write_tout = 300;info->vendor = CFI_CMDSET_AMD_LEGACY;info->cmd_reset = 0xF0;info->interface = FLASH_CFI_X8;info->legacy_unlock = 0;info->manufacturer_id = 0x22;info->device_id = 0xBA;info->device_id2 = 0;info->ext_addr = 0;info->cfi_version = 0x3133;info->cfi_offset = 0x0000;info->addr_unlock1 = 0x00000aaa;info->addr_unlock2 = 0x00000555;info->name = "MX29LV400CB";initialization with magic numbers should be provided with some comments for better understanding.
I can add some comments, although here most of the comments would simply paraphrase the code one way or the other, e.g.
info->device_id = 0xBA; /* device ID of the MX29LV400CB is 0xBA */
... won't add much to readability. For anyone interested in this part of the code, for the most part field names and assigned values are all the information needed. How about a global comment before the whole lot of assignments?
+++ b/board/LaCie/edminiv2/edminiv2.h
+#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_23 0x00000000
+++ b/board/LaCie/edminiv2/lowlevel_init.S
+#define EDMINIV2_MPP0_7 0x00000003 +#define EDMINIV2_MPP8_15 0x55550000 +#define EDMINIV2_MPP16_19 0x00005555
Code repeated, this is already defined in edminiv2.h (reported earlier for V3)
Dupe removed.
Please defined all GPIO stuff at one place
Ditto, as above.
+/*
- Low-level init happens right after start.S has switched to SVC32,
- flushed and disabled caches and disabled MMU. We're still running
- from the boot chip select, so the first thing we should do is set
- up RAM for us to relocate into.
- */
+.globl lowlevel_init
+lowlevel_init:
/* Use 'r4 as the base for internal register accesses */ldr r4, =EDMINIV2_INTERNAL_BASE/* move internal registers from the default 0xD0000000* to their intended location of 0xf1000000 */ldr r3, =0xD0000000add r3, r3, #0x20000str r4, [r3, #0x80]/* Use R3 as the base for Device Bus registers */add r3, r4, #0x10000/* init MPPs */ldr r6, =EDMINIV2_MPP0_7str r6, [r3, #0x000]ldr r6, =EDMINIV2_MPP8_15str r6, [r3, #0x004]ldr r6, =EDMINIV2_MPP16_23str r6, [r3, #0x050]/* init GPIOs */ldr r6, =EDMINIV2_GPIO_OUT_ENABLEstr r6, [r3, #0x104]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/*DDR SDRAM Initialization Control */ldr r6, =0x00000001str r6, [r3, #0x480]/* Use R3 as the base for PCI registers */add r3, r4, #0x31000/* Disable arbiter */ldr r6, =0x00000030str r6, [r3, #0xd00]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/* set all dram windows to 0 */mov r6, #0str r6, [r3, #0x504]str r6, [r3, #0x50C]str r6, [r3, #0x514]str r6, [r3, #0x51C]/* 1) Configure SDRAM */ldr r6, =SDRAM_CONFIGstr r6, [r3, #0x400]/* 2) Set SDRAM Control reg */ldr r6, =SDRAM_CONTROLstr r6, [r3, #0x404]/* 3) Write SDRAM address control register */ldr r6, =SDRAM_ADDR_CTRLstr r6, [r3, #0x410]/* 4) Write SDRAM bank 0 size register */ldr r6, =SDRAM_BANK0_SIZEstr r6, [r3, #0x504]/* keep other banks disabled *//* 5) Write SDRAM open pages control register */ldr r6, =SDRAM_OPEN_PAGE_ENstr r6, [r3, #0x414]/* 6) Write SDRAM timing Low register */ldr r6, =SDRAM_TIME_CTRL_LOWstr r6, [r3, #0x408]/* 7) Write SDRAM timing High register */ldr r6, =SDRAM_TIME_CTRL_HIstr r6, [r3, #0x40C]/* 8) Write SDRAM mode register *//* The CPU must not attempt to change the SDRAM Moderegister setting */
/* prior to DRAM controller completion of the DRAMinitialization */
/* sequence. To guarantee this restriction, it isrecommended that */
/* the CPU sets the SDRAM Operation register to NOPcommand, performs */
/* read polling until the register is back in Normaloperation value, */
/* and then sets SDRAM Mode register to its newvalue. */
/* 8.1 write 'nop' to SDRAM operation */ldr r6, =SDRAM_OP_NOPstr r6, [r3, #0x418]/* 8.2 poll SDRAM operation until back in 'normal' mode. */+1:
ldr r6, [r3, #0x418]cmp r6, #0bne 1b/* 8.3 Now its safe to write new value to SDRAM Moderegister */
ldr r6, =SDRAM_MODEstr r6, [r3, #0x41C]/* 8.4 Set new mode */ldr r6, =SDRAM_OP_SETMODEstr r6, [r3, #0x418]/* 8.5 poll SDRAM operation until back in 'normal' mode. */+2:
ldr r6, [r3, #0x418]cmp r6, #0bne 2b/* DDR SDRAM Address/Control Pads Calibration */ldr r6, [r3, #0x4C0]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26 /* r1[5:0]<DrvN> =r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C0]/* DDR SDRAM Data Pads Calibration */ldr r6, [r3, #0x4C4]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> *//* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-3) Drive StrengthValue */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ldr r1, =DDR1_PAD_STRENGTH_DEFAULT/* Enable writes to DDR SDRAM Addr/Ctrl PadsCalibration register */
ldr r6, [r3, #0x4C0]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r6, r6, r1str r6, [r3, #0x4C0]/* Enable writes to DDR SDRAM Data Pads Calibration register */ldr r6, [r3, #0x4C4]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r6, r6, #SDRAM_PAD_CTRL_WR_ENorr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-4) DQS ReferenceDelay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 *//* Get the "sample on reset" register for the DDRfrequancy */
ldr r3, =0x10000ldr r6, [r3, #0x010]ldr r1, =MSAR_ARMDDRCLCK_MASKand r1, r6, r1ldr r6, =FTDLL_DDR1_166MHZcmp r1, #MSAR_ARMDDRCLCK_333_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_500_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_667_167beq 3fldr r6, =FTDLL_DDR1_200MHZcmp r1, #MSAR_ARMDDRCLCK_400_200_1beq 3fcmp r1, #MSAR_ARMDDRCLCK_400_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_600_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_800_200beq 3fAs reported earlier comment for v3, this should only have simple DRAM initialization, which is only dependency to copy and start binary.
Hmm... Those are fixes to allow/ensure DDRAM access, so I'd say this is a dependency to copy and start the binary.
MPP and GPIO inits should be moved to edminv2.c.
Why move them? They must be board-specific, and they are indeed in board-specific code.
Common to SoC stuff to be moved to cpu.c/h
This I can agree upon, however I don't see much that is common across SoCs here. Does that warrant creating a function at SoC level which will do practically nothing?
Regards.. Prafulla . .
Thanks Prafulla for your comments.
Amicalement,
-----Original Message----- From: Albert ARIBAUD [mailto:albert.aribaud@free.fr] Sent: Wednesday, January 13, 2010 6:08 PM To: Prafulla Wadaskar Cc: U-Boot@lists.denx.de Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board
...snip...
info->flash_id = 0x01000000;info->portwidth = FLASH_CFI_8BIT;info->chipwidth = FLASH_CFI_BY8;info->buffer_size = 0;info->erase_blk_tout = 1000;info->write_tout = 10;info->buffer_write_tout = 300;info->vendor = CFI_CMDSET_AMD_LEGACY;info->cmd_reset = 0xF0;info->interface = FLASH_CFI_X8;info->legacy_unlock = 0;info->manufacturer_id = 0x22;info->device_id = 0xBA;info->device_id2 = 0;info->ext_addr = 0;info->cfi_version = 0x3133;info->cfi_offset = 0x0000;info->addr_unlock1 = 0x00000aaa;info->addr_unlock2 = 0x00000555;info->name = "MX29LV400CB";initialization with magic numbers should be provided with
some comments for better understanding.
I can add some comments, although here most of the comments would simply paraphrase the code one way or the other, e.g.
info->device_id = 0xBA; /* device ID of theMX29LV400CB is 0xBA */
This level documentation is good rather than nothing :-)
...snip...
+lowlevel_init:
/* Use 'r4 as the base for internal register accesses */ldr r4, =EDMINIV2_INTERNAL_BASE/* move internal registers from the default 0xD0000000* to their intended location of 0xf1000000 */ldr r3, =0xD0000000add r3, r3, #0x20000str r4, [r3, #0x80]/* Use R3 as the base for Device Bus registers */add r3, r4, #0x10000/* init MPPs */ldr r6, =EDMINIV2_MPP0_7str r6, [r3, #0x000]ldr r6, =EDMINIV2_MPP8_15str r6, [r3, #0x004]ldr r6, =EDMINIV2_MPP16_23str r6, [r3, #0x050]/* init GPIOs */ldr r6, =EDMINIV2_GPIO_OUT_ENABLEstr r6, [r3, #0x104]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/*DDR SDRAM Initialization Control */ldr r6, =0x00000001str r6, [r3, #0x480]/* Use R3 as the base for PCI registers */add r3, r4, #0x31000/* Disable arbiter */ldr r6, =0x00000030str r6, [r3, #0xd00]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/* set all dram windows to 0 */mov r6, #0str r6, [r3, #0x504]str r6, [r3, #0x50C]str r6, [r3, #0x514]str r6, [r3, #0x51C]/* 1) Configure SDRAM */ldr r6, =SDRAM_CONFIGstr r6, [r3, #0x400]/* 2) Set SDRAM Control reg */ldr r6, =SDRAM_CONTROLstr r6, [r3, #0x404]/* 3) Write SDRAM address control register */ldr r6, =SDRAM_ADDR_CTRLstr r6, [r3, #0x410]/* 4) Write SDRAM bank 0 size register */ldr r6, =SDRAM_BANK0_SIZEstr r6, [r3, #0x504]/* keep other banks disabled *//* 5) Write SDRAM open pages control register */ldr r6, =SDRAM_OPEN_PAGE_ENstr r6, [r3, #0x414]/* 6) Write SDRAM timing Low register */ldr r6, =SDRAM_TIME_CTRL_LOWstr r6, [r3, #0x408]/* 7) Write SDRAM timing High register */ldr r6, =SDRAM_TIME_CTRL_HIstr r6, [r3, #0x40C]/* 8) Write SDRAM mode register *//* The CPU must not attempt to change the SDRAM Moderegister setting */
/* prior to DRAM controller completion of the DRAMinitialization */
/* sequence. To guarantee this restriction, it isrecommended that */
/* the CPU sets the SDRAM Operation register to NOPcommand, performs */
/* read polling until the register is back in Normaloperation value, */
/* and then sets SDRAM Mode register to its newvalue. */
/* 8.1 write 'nop' to SDRAM operation */ldr r6, =SDRAM_OP_NOPstr r6, [r3, #0x418]/* 8.2 poll SDRAM operation until back in'normal' mode. */
+1:
ldr r6, [r3, #0x418]cmp r6, #0bne 1b/* 8.3 Now its safe to write new value to SDRAM Moderegister */
ldr r6, =SDRAM_MODEstr r6, [r3, #0x41C]/* 8.4 Set new mode */ldr r6, =SDRAM_OP_SETMODEstr r6, [r3, #0x418]/* 8.5 poll SDRAM operation until back in'normal' mode. */
+2:
ldr r6, [r3, #0x418]cmp r6, #0bne 2b/* DDR SDRAM Address/Control Pads Calibration */ldr r6, [r3, #0x4C0]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26 /* r1[5:0]<DrvN> =r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C0]/* DDR SDRAM Data Pads Calibration */ldr r6, [r3, #0x4C4]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> *//* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-3) Drive StrengthValue */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ldr r1, =DDR1_PAD_STRENGTH_DEFAULT/* Enable writes to DDR SDRAM Addr/Ctrl PadsCalibration register */
ldr r6, [r3, #0x4C0]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r6, r6, r1str r6, [r3, #0x4C0]/* Enable writes to DDR SDRAM Data Pads Calibrationregister */
ldr r6, [r3, #0x4C4]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r6, r6, #SDRAM_PAD_CTRL_WR_ENorr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-4) DQS ReferenceDelay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 *//* Get the "sample on reset" register for the DDRfrequancy */
ldr r3, =0x10000ldr r6, [r3, #0x010]ldr r1, =MSAR_ARMDDRCLCK_MASKand r1, r6, r1ldr r6, =FTDLL_DDR1_166MHZcmp r1, #MSAR_ARMDDRCLCK_333_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_500_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_667_167beq 3fldr r6, =FTDLL_DDR1_200MHZcmp r1, #MSAR_ARMDDRCLCK_400_200_1beq 3fcmp r1, #MSAR_ARMDDRCLCK_400_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_600_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_800_200beq 3fAs reported earlier comment for v3, this should only have simple DRAM initialization, which is
only dependency to copy and start binary.
Hmm... Those are fixes to allow/ensure DDRAM access, so I'd say this is a dependency to copy and start the binary.
The code here looks very long It's purpose is to initialize certain CPU registers. For specific board there is no need of any conditional initializations.
Similar to board/Marvell/Sheevaplug/kwbimage.cfg, can you abstract a data for CPU registers and values to be initialized through some data structures and a small function to read and copy them to respective registers?
That will give better readability and easy updates for future users.
MPP and GPIO inits should be moved to edminv2.c.
Why move them? They must be board-specific, and they are indeed in board-specific code.
edminv2.c is also board specific :-), lets keep least ASM code. We cannot avoid lowlevel_init otherwise I could have preferred to omit it.
Common to SoC stuff to be moved to cpu.c/h
This I can agree upon, however I don't see much that is common across SoCs here. Does that warrant creating a function at SoC level which will do practically nothing?
For ex. Mpp_init, GPIO_init and other init can go in cpu.c, You can declare respective init macros in edminv2.h and function calls in edminv2.c Thus those will be re-usable for other orion5X boards.
Also you can do basic CPU registers initialization as suggested above and Further tuning like reading "sample on reset" and updating some specific registers can be pushed in cpu.c Because this will be a standard need to all board using this SoC
What do you think?
Regards. Prafulla . .
Prafulla Wadaskar a écrit :
I can add some comments, although here most of the comments would simply paraphrase the code one way or the other, e.g.
info->device_id = 0xBA; /* device ID of theMX29LV400CB is 0xBA */
This level documentation is good rather than nothing :-)
Ok, but I prefer to summarize it above the assignments, e.g. 'commands and unlock addresses are AMD-compliant for an 8-bit mode, 8-bit bus device' is enough to let the reader understand the assignments to portwidth, chipwidth, vendor, cmd_reset, interface, addr_unlock1 and addr_unlock2; I'll make sure all fields are covered.
...snip...
+lowlevel_init:
/* Use 'r4 as the base for internal register accesses */ldr r4, =EDMINIV2_INTERNAL_BASE/* move internal registers from the default 0xD0000000* to their intended location of 0xf1000000 */ldr r3, =0xD0000000add r3, r3, #0x20000str r4, [r3, #0x80]/* Use R3 as the base for Device Bus registers */add r3, r4, #0x10000/* init MPPs */ldr r6, =EDMINIV2_MPP0_7str r6, [r3, #0x000]ldr r6, =EDMINIV2_MPP8_15str r6, [r3, #0x004]ldr r6, =EDMINIV2_MPP16_23str r6, [r3, #0x050]/* init GPIOs */ldr r6, =EDMINIV2_GPIO_OUT_ENABLEstr r6, [r3, #0x104]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/*DDR SDRAM Initialization Control */ldr r6, =0x00000001str r6, [r3, #0x480]/* Use R3 as the base for PCI registers */add r3, r4, #0x31000/* Disable arbiter */ldr r6, =0x00000030str r6, [r3, #0xd00]/* Use R3 as the base for DRAM registers */add r3, r4, #0x01000/* set all dram windows to 0 */mov r6, #0str r6, [r3, #0x504]str r6, [r3, #0x50C]str r6, [r3, #0x514]str r6, [r3, #0x51C]/* 1) Configure SDRAM */ldr r6, =SDRAM_CONFIGstr r6, [r3, #0x400]/* 2) Set SDRAM Control reg */ldr r6, =SDRAM_CONTROLstr r6, [r3, #0x404]/* 3) Write SDRAM address control register */ldr r6, =SDRAM_ADDR_CTRLstr r6, [r3, #0x410]/* 4) Write SDRAM bank 0 size register */ldr r6, =SDRAM_BANK0_SIZEstr r6, [r3, #0x504]/* keep other banks disabled *//* 5) Write SDRAM open pages control register */ldr r6, =SDRAM_OPEN_PAGE_ENstr r6, [r3, #0x414]/* 6) Write SDRAM timing Low register */ldr r6, =SDRAM_TIME_CTRL_LOWstr r6, [r3, #0x408]/* 7) Write SDRAM timing High register */ldr r6, =SDRAM_TIME_CTRL_HIstr r6, [r3, #0x40C]/* 8) Write SDRAM mode register *//* The CPU must not attempt to change the SDRAM Moderegister setting */
/* prior to DRAM controller completion of the DRAMinitialization */
/* sequence. To guarantee this restriction, it isrecommended that */
/* the CPU sets the SDRAM Operation register to NOPcommand, performs */
/* read polling until the register is back in Normaloperation value, */
/* and then sets SDRAM Mode register to its newvalue. */
/* 8.1 write 'nop' to SDRAM operation */ldr r6, =SDRAM_OP_NOPstr r6, [r3, #0x418]/* 8.2 poll SDRAM operation until back in'normal' mode. */
+1:
ldr r6, [r3, #0x418]cmp r6, #0bne 1b/* 8.3 Now its safe to write new value to SDRAM Moderegister */
ldr r6, =SDRAM_MODEstr r6, [r3, #0x41C]/* 8.4 Set new mode */ldr r6, =SDRAM_OP_SETMODEstr r6, [r3, #0x418]/* 8.5 poll SDRAM operation until back in'normal' mode. */
+2:
ldr r6, [r3, #0x418]cmp r6, #0bne 2b/* DDR SDRAM Address/Control Pads Calibration */ldr r6, [r3, #0x4C0]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26 /* r1[5:0]<DrvN> =r3[22:17]<LockN> */
orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =r1[5:0]<DrvN> */
/* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C0]/* DDR SDRAM Data Pads Calibration */ldr r6, [r3, #0x4C4]/* Set Bit [31] to make the register writable */orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_TUNE_ENbic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASKbic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK/* Get the final N locked value of driving strength[22:17] */
mov r1, r6mov r1, r1, LSL #9mov r1, r1, LSR #26orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> *//* Write to both <DrvN> bits [5:0] and <DrvP> bits[11:6] */
orr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-3) Drive StrengthValue */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ldr r1, =DDR1_PAD_STRENGTH_DEFAULT/* Enable writes to DDR SDRAM Addr/Ctrl PadsCalibration register */
ldr r6, [r3, #0x4C0]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C0]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_WR_ENbic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKorr r6, r6, r1str r6, [r3, #0x4C0]/* Enable writes to DDR SDRAM Data Pads Calibrationregister */
ldr r6, [r3, #0x4C4]orr r6, r6, #SDRAM_PAD_CTRL_WR_ENstr r6, [r3, #0x4C4]/* Correct strength and disable writes again */bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASKbic r6, r6, #SDRAM_PAD_CTRL_WR_ENorr r6, r6, r1str r6, [r3, #0x4C4]/* Implement Guideline (GL# MEM-4) DQS ReferenceDelay Tuning */
/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 *//* Get the "sample on reset" register for the DDRfrequancy */
ldr r3, =0x10000ldr r6, [r3, #0x010]ldr r1, =MSAR_ARMDDRCLCK_MASKand r1, r6, r1ldr r6, =FTDLL_DDR1_166MHZcmp r1, #MSAR_ARMDDRCLCK_333_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_500_167beq 3fcmp r1, #MSAR_ARMDDRCLCK_667_167beq 3fldr r6, =FTDLL_DDR1_200MHZcmp r1, #MSAR_ARMDDRCLCK_400_200_1beq 3fcmp r1, #MSAR_ARMDDRCLCK_400_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_600_200beq 3fcmp r1, #MSAR_ARMDDRCLCK_800_200beq 3fAs reported earlier comment for v3, this should only have simple DRAM initialization, which is
only dependency to copy and start binary.
Hmm... Those are fixes to allow/ensure DDRAM access, so I'd say this is a dependency to copy and start the binary.
The code here looks very long It's purpose is to initialize certain CPU registers. For specific board there is no need of any conditional initializations.
Similar to board/Marvell/Sheevaplug/kwbimage.cfg, can you abstract a data for CPU registers and values to be initialized through some data structures and a small function to read and copy them to respective registers?
That will give better readability and easy updates for future users.
It's not only setting registers, there are some loops, so several register+value tables would be needed, but yes, I can give it a shot.
lets keep least ASM code.
Ok.
We cannot avoid lowlevel_init otherwise I could have preferred to omit it.
I would have too, but there's no choice there.
Common to SoC stuff to be moved to cpu.c/h
This I can agree upon, however I don't see much that is common across SoCs here. Does that warrant creating a function at SoC level which will do practically nothing?
For ex. Mpp_init, GPIO_init and other init can go in cpu.c, You can declare respective init macros in edminv2.h and function calls in edminv2.c Thus those will be re-usable for other orion5X boards.
Also you can do basic CPU registers initialization as suggested above and Further tuning like reading "sample on reset" and updating some specific registers can be pushed in cpu.c Because this will be a standard need to all board using this SoC
What do you think?
I'll give a shot at moving as much code from lowlevel_init as I can into cpu.c with constants in edminiv2.h.
Regards. Prafulla . .
Amicalement,
Albert Aribaud wrote:
This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses CONFIG_FLASH_CFI_LEGACY as the Macronix MX29LV400 used on ED Mini V2 is not CFI compliant (mixes 16 and 8 bit behaviors).
Signed-off-by: Albert Aribaud albert.aribaud@free.fr
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 58 ++++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 88 +++++++++ board/LaCie/edminiv2/edminiv2.h | 59 ++++++ board/LaCie/edminiv2/lowlevel_init.S | 324 ++++++++++++++++++++++++++++++++++ include/configs/edminiv2.h | 147 +++++++++++++++ 9 files changed, 711 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 board/LaCie/edminiv2/lowlevel_init.S create mode 100644 include/configs/edminiv2.h
Please resolve the compile warnings generated from MAKEALL for the edminiv2_config.
dram.c: In function 'dram_init': dram.c:59: warning: passing argument 1 of 'get_ram_size' makes pointer from integer without a cast edminiv2.c: In function 'board_init': edminiv2.c:85: warning: implicit declaration of function 'orion5x_sdram_bar'
Tom
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Albert Aribaud Sent: Sunday, January 10, 2010 9:34 PM To: U-Boot@lists.denx.de Subject: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr
Patchset history
V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses getm_ram_size().
cpu/arm926ejs/orion5x/Makefile | 51 ++++++ cpu/arm926ejs/orion5x/cpu.c | 258 ++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 62 +++++++ cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++++++++ include/asm-arm/arch-orion5x/cpu.h | 187 +++++++++++++++++++++ include/asm-arm/arch-orion5x/mv88f5182.h | 40 +++++ include/asm-arm/arch-orion5x/orion5x.h | 67 ++++++++ 7 files changed, 846 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
...snip...
diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c new file mode 100644 index 0000000..af4a788 --- /dev/null +++ b/cpu/arm926ejs/orion5x/dram.c @@ -0,0 +1,62 @@ +/*
- Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr
- Based on original Kirkwood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- MA 02110-1301 USA
- */
+#include <common.h> +#include <config.h> +#include <asm/arch/orion5x.h>
+DECLARE_GLOBAL_DATA_PTR;
+#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08))
As pointed by wolfgang earlier, you can use c-structures here too. -Magic numbers 1500, 1504 can be replaced by appropreate macros like- CPU_CS0_BAR, CPU_CS0_SZ -Struct pointer can be declared in cpu.h like #define ORION5X_SDRAM_ADRDEC_BASE (ORION5X_REGISTER(0x1500)) ref( table 114 in 5182 users manual)
I know it's coming from referenced code but lets make new code the best. Also I will be updating old code too.
+/*
- orion5x_sdram_bar - reads SDRAM Base Address Register
- */
+u32 orion5x_sdram_bar(enum memory_bank bank) +{
- u32 result = 0;
- u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
- if ((!enable) || (bank > BANK3))
return 0;- result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank));
- return result;
+}
...snip..
diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h new file mode 100644 index 0000000..0a33999 --- /dev/null +++ b/include/asm-arm/arch-orion5x/cpu.h @@ -0,0 +1,187 @@ +/*
- Copyright (C) 2009 Albert ARIBAUD albert.aribaud@free.fr
- Based on original Kirorion5x_ood support which is
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Written-by: Prafulla Wadaskar prafulla@marvell.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- MA 02110-1301 USA
- */
+#ifndef _ORION5X_CPU_H +#define _ORION5X_CPU_H
+#include <asm/system.h>
+#ifndef __ASSEMBLY__
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) |(orion5x_winctrl_calcsize(size) << 16))
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
((_x ? ORION5X_EGIGA0_BASE :ORION5X_EGIGA1_BASE) + 0x44c)
+enum memory_bank {
- BANK0,
- BANK1,
- BANK2,
- BANK3
+};
+enum orion5x_cpu_winen {
- ORION5X_WIN_DISABLE,
- ORION5X_WIN_ENABLE
+};
+enum orion5x_cpu_target {
- ORION5X_TARGET_DRAM = 0,
- ORION5X_TARGET_DEVICE = 1,
- ORION5X_TARGET_PCI = 3,
- ORION5X_TARGET_PCIE = 4,
- ORION5X_TARGET_SASRAM = 9
+};
+enum orion5x_cpu_attrib {
- ORION5X_ATTR_DRAM_CS0 = 0x0e,
- ORION5X_ATTR_DRAM_CS1 = 0x0d,
- ORION5X_ATTR_DRAM_CS2 = 0x0b,
- ORION5X_ATTR_DRAM_CS3 = 0x07,
- ORION5X_ATTR_PCI_MEM = 0x59,
- ORION5X_ATTR_PCI_IO = 0x51,
- ORION5X_ATTR_PCIE_MEM = 0x59,
- ORION5X_ATTR_PCIE_IO = 0x51,
- ORION5X_ATTR_SASRAM = 0x00,
- ORION5X_ATTR_DEV_CS0 = 0x1e,
- ORION5X_ATTR_DEV_CS1 = 0x1d,
- ORION5X_ATTR_DEV_CS2 = 0x1b,
- ORION5X_ATTR_BOOTROM = 0x0f
+};
+/*
- Default Device Address MAP BAR values
- */
+#define ORION5X_DEFADR_PCIE_MEM 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
+#define ORION5X_DEFADR_PCIE_IO 0xf0000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_IO (64*1024)
+#define ORION5X_DEFADR_PCI_MEM 0x98000000 +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
+#define ORION5X_DEFADR_PCI_IO 0xf0100000 +#define ORION5X_DEFSZ_PCI_IO (64*1024)
+#define ORION5X_DEFADR_DEV_CS0 0xfa000000 +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
+#define ORION5X_DEFADR_DEV_CS1 0xf8000000 +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
+#define ORION5X_DEFADR_DEV_CS2 0xfa800000 +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
+#define ORION5X_DEFADR_BOOTROM 0xFFF80000 +#define ORION5X_DEFSZ_BOOTROM (512*1024)
+/*
- PCIE registers are used for SoC device ID and revision
- */
+#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3
These are Chip specific, should be moved to mv88f5182.h and similar headers for other Supported Chips
Regards. Prafulla . .
Prafulla Wadaskar a écrit :
+#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08))
As pointed by wolfgang earlier, you can use c-structures here too. -Magic numbers 1500, 1504 can be replaced by appropreate macros like- CPU_CS0_BAR, CPU_CS0_SZ -Struct pointer can be declared in cpu.h like #define ORION5X_SDRAM_ADRDEC_BASE (ORION5X_REGISTER(0x1500)) ref( table 114 in 5182 users manual)
I know it's coming from referenced code but lets make new code the best. Also I will be updating old code too.
Agreed and fixed for V5.
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3
These are Chip specific, should be moved to mv88f5182.h and similar headers for other Supported Chips
The reason why they are defined this way is that they are for identifying the real device/revision on which you are running u-boot, as opposed to the intended device/revision for which you built it; they are only useful for parts of the code which are common to all orion5x variants (such as print_cpuinfo). Variant-specific code would not need it as it knows already which variant it is for.
Regards. Prafulla . .
Amicalement,
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Albert Aribaud Sent: Sunday, January 10, 2010 9:34 PM To: U-Boot@lists.denx.de Subject: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr
Patchset history
V1: Initial monolithic patch. V2: split in three patches : orion, serial, edmini; checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3: useless GPIO and MPP programming support removed; low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed. V4: all files licensed GPLv2-only removed; RAM bank size detection now uses getm_ram_size().
cpu/arm926ejs/orion5x/Makefile | 51 ++++++ cpu/arm926ejs/orion5x/cpu.c | 258
....snip....
+int print_cpuinfo(void) +{
- char dev_str[] = "0x0000";
- char rev_str[] = "0x00";
- char *dev_name = NULL;
- char *rev_name = NULL;
- u32 dev = orion5x_device_id();
- u32 rev = orion5x_device_rev();
- if (dev == MV88F5181_DEV_ID) {
dev_name = "MV88F5181";if (rev == MV88F5181_REV_B1)rev_name = "B1";else if (rev == MV88F5181L_REV_A1) {dev_name = "MV88F5181L";rev_name = "A1";} else if (rev == MV88F5181L_REV_A0) {dev_name = "MV88F5181L";rev_name = "A0";}- } else if (dev == MV88F5182_DEV_ID) {
dev_name = "MV88F5182";if (rev == MV88F5182_REV_A2)rev_name = "A2";- } else if (dev == MV88F5281_DEV_ID) {
dev_name = "MV88F5281";if (rev == MV88F5281_REV_D2)rev_name = "D2";else if (rev == MV88F5281_REV_D1)rev_name = "D1";else if (rev == MV88F5281_REV_D0)rev_name = "D0";- } else if (dev == MV88F6183_DEV_ID) {
dev_name = "MV88F6183";if (rev == MV88F6183_REV_B0)rev_name = "B0";- }
The above checks should be #ifdefed with CONFIG_88FXXXX (SOC type) There is no need to check for all SoC names, this will also reduce code size.
Regards.. Prafulla . .
Prafulla Wadaskar a écrit :
cpu/arm926ejs/orion5x/cpu.c | 258
....snip....
+int print_cpuinfo(void)
The above checks should be #ifdefed with CONFIG_88FXXXX (SOC type) There is no need to check for all SoC names, this will also reduce code size.
As stated in my answer re: the declaration of the dev/rev constants, I believe that this place, of all place, should not be conditionally built depending on the device, because it is there to positively identify the device/revision we're running our code on even if not built for the right variant.
Amicalement,
participants (4)
-
Albert ARIBAUD -
Albert Aribaud
-
Prafulla Wadaskar -
Tom