[U-Boot] [PATCH 00/20] updates for Keymile Marvell boards
This series adds support for 2 new Kirkwood boards at Keymile: kmnusa and kmcoge5un. All the previously supported boards that had a proper config file now are all supported by the generic km_kirkwood.h config file.
This series also adds support for the environment variables in the SPI NOR Flash, for a skippable FPGA download through the BOCO2 CPLD, and for the configuration of a managed Marvell switch that is used on kmnusa.
This series also corrects a bug caused by accessing global static tables in board_early_init_f that is called before relocation which must be avoided.
Holger Brunck (6): arm/km: add kmnusa board support arm/km: add kmcoge5un board support arm/km: convert mgcoge3un target to km_kirkwood arm/km: remove portl2.h and use km_kirkwood instead arm/km: cleanup km_kirkwood boards arm/km: remove spi toggle command
Thomas Herzmann (2): arm/km: add implementation for read_dip_switch arm/km: fix testpin detection for kmcoge5un
Valentin Longchamp (12): arm/km: enable spi claim bus arm/km: use correct kw_gpio function for NAND/SPI switching arm/kirkwood: protect the ENV_SPI #defines arm/km: correct init of 88e6352 switch in the reset_phy function arm/km: enable BOCO2 FPGA download support arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: add support for external switch configuration arm/km: enable external switch configuration for kmnusa arm/km: skip FPGA config when already configured arm/km: support the 2 PCIe fpga resets arm/km: implement weak function board_spi_clam_bus/release arm/km: remove calls to kw_gpio_* in board_early_init_f
MAINTAINERS | 2 + arch/arm/include/asm/arch-kirkwood/config.h | 12 +- board/keymile/common/common.h | 5 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++ board/keymile/km_arm/256M8-1.cfg | 296 +++++++++++++++++++++++++ board/keymile/km_arm/Makefile | 8 + board/keymile/km_arm/fpga_config.c | 256 ++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 169 +++++++++------ board/keymile/km_arm/managed_switch.c | 316 +++++++++++++++++++++++++++ board/keymile/km_arm/managed_switch.h | 106 +++++++++ boards.cfg | 10 +- include/configs/km/km_arm.h | 57 ++++- include/configs/km_kirkwood.h | 154 ++++++++++++- include/configs/mgcoge3un.h | 87 -------- include/configs/portl2.h | 85 ------- 15 files changed, 1583 insertions(+), 274 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg create mode 100644 board/keymile/km_arm/256M8-1.cfg create mode 100644 board/keymile/km_arm/fpga_config.c create mode 100644 board/keymile/km_arm/managed_switch.c create mode 100644 board/keymile/km_arm/managed_switch.h delete mode 100644 include/configs/mgcoge3un.h delete mode 100644 include/configs/portl2.h
This is required for all our keymile ARM boards. The selected MPPs are the default one for the SPI controller, thus the 0x0 definition.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- include/configs/km/km_arm.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index eb60d29..056bf53 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -227,6 +227,9 @@ int get_scl(void); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO
+/* SPI bus claim MPP configuration */ +#define CONFIG_SYS_KW_SPI_MPP 0x0 + #define FLASH_GPIO_PIN 0x00010000
#define MTDIDS_DEFAULT "nand0=orion_nand"
This used to be done with registers direct access, which is not clear and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++------------------- include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/* - * The FLASH_GPIO_PIN switches between using a + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); - + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); #if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{ + int gpio_value = !on; + + if (on) { + kwmpp_config[0] = MPP0_SPI_SCn; + kwmpp_config[1] = MPP1_SPI_MOSI; + kwmpp_config[2] = MPP2_SPI_SCK; + kwmpp_config[3] = MPP3_SPI_MISO; + } else { + kwmpp_config[0] = MPP0_NF_IO2; + kwmpp_config[1] = MPP1_NF_IO3; + kwmpp_config[2] = MPP2_NF_IO4; + kwmpp_config[3] = MPP3_NF_IO5; + } + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + kw_gpio_set_value(KM_FLASH_GPIO_PIN, gpio_value); + + return 0; +} + #if defined(CONFIG_CMD_SF) int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u32 tmp; if (argc < 2) return cmd_usage(cmdtp);
if ((strcmp(argv[1], "off") == 0)) { printf("SPI FLASH disabled, NAND enabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - - kirkwood_mpp_conf(kwmpp_config, NULL); - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); + km_hw_spi_bus_claim(0); } else if ((strcmp(argv[1], "on") == 0)) { printf("SPI FLASH enabled, NAND disabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - - kirkwood_mpp_conf(kwmpp_config, NULL); - tmp = readl(KW_GPIO0_BASE); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); + km_hw_spi_bus_claim(1); } else { return cmd_usage(cmdtp); } diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 056bf53..28b5021 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -231,6 +231,7 @@ int get_scl(void); #define CONFIG_SYS_KW_SPI_MPP 0x0
#define FLASH_GPIO_PIN 0x00010000 +#define KM_FLASH_GPIO_PIN 16
#define MTDIDS_DEFAULT "nand0=orion_nand" /* test-only: partitioning needs some tuning, this is just for tests */
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not clear and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++-----------
include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/*
* The FLASH_GPIO_PIN switches between using a
* The KM_FLASH_GPIO_PIN switches between using a*/
- NAND or a SPI FLASH. Set this pin on start
- to NAND mode.
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{
- int gpio_value = !on;
- if (on) {
kwmpp_config[0] = MPP0_SPI_SCn;kwmpp_config[1] = MPP1_SPI_MOSI;kwmpp_config[2] = MPP2_SPI_SCK;kwmpp_config[3] = MPP3_SPI_MISO;- } else {
kwmpp_config[0] = MPP0_NF_IO2;kwmpp_config[1] = MPP1_NF_IO3;kwmpp_config[2] = MPP2_NF_IO4;kwmpp_config[3] = MPP3_NF_IO5;- }
NACK...
Regards.. Prafulla . . .
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not clear and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++-----------
include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/*
* The FLASH_GPIO_PIN switches between using a
* The KM_FLASH_GPIO_PIN switches between using a*/
- NAND or a SPI FLASH. Set this pin on start
- to NAND mode.
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{
- int gpio_value = !on;
- if (on) {
kwmpp_config[0] = MPP0_SPI_SCn;kwmpp_config[1] = MPP1_SPI_MOSI;kwmpp_config[2] = MPP2_SPI_SCK;kwmpp_config[3] = MPP3_SPI_MISO;- } else {
kwmpp_config[0] = MPP0_NF_IO2;kwmpp_config[1] = MPP1_NF_IO3;kwmpp_config[2] = MPP2_NF_IO4;kwmpp_config[3] = MPP3_NF_IO5;- }
NACK...
Could you please be a bit more verbose. Why do you NACK this? This code is only related to our boards...
Regards Holger
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:08 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not
clear
and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++--------
include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/*
* The FLASH_GPIO_PIN switches between using a
* The KM_FLASH_GPIO_PIN switches between using a*/
- NAND or a SPI FLASH. Set this pin on start
- to NAND mode.
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{
- int gpio_value = !on;
- if (on) {
kwmpp_config[0] = MPP0_SPI_SCn;kwmpp_config[1] = MPP1_SPI_MOSI;kwmpp_config[2] = MPP2_SPI_SCK;kwmpp_config[3] = MPP3_SPI_MISO;- } else {
kwmpp_config[0] = MPP0_NF_IO2;kwmpp_config[1] = MPP1_NF_IO3;kwmpp_config[2] = MPP2_NF_IO4;kwmpp_config[3] = MPP3_NF_IO5;- }
NACK...
Could you please be a bit more verbose. Why do you NACK this? This code is only related to our boards...
Dear Holger We have already patches for Kirkwood-spi in place that address this. So we have to use this framework.
Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html
Regards.. Prafulla . . .
On 06/12/2012 11:32 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:08 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not
clear
and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++--------
include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/*
* The FLASH_GPIO_PIN switches between using a
* The KM_FLASH_GPIO_PIN switches between using a*/
- NAND or a SPI FLASH. Set this pin on start
- to NAND mode.
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{
- int gpio_value = !on;
- if (on) {
kwmpp_config[0] = MPP0_SPI_SCn;kwmpp_config[1] = MPP1_SPI_MOSI;kwmpp_config[2] = MPP2_SPI_SCK;kwmpp_config[3] = MPP3_SPI_MISO;- } else {
kwmpp_config[0] = MPP0_NF_IO2;kwmpp_config[1] = MPP1_NF_IO3;kwmpp_config[2] = MPP2_NF_IO4;kwmpp_config[3] = MPP3_NF_IO5;- }
NACK...
Could you please be a bit more verbose. Why do you NACK this? This code is only related to our boards...
Dear Holger We have already patches for Kirkwood-spi in place that address this. So we have to use this framework.
Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html
ok I see what you mean. We make use of it later on: [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release I'll squash this one together with 02/20 then it is more clear.
Regards Holger
On 06/12/2012 12:29 PM, Holger Brunck wrote:
On 06/12/2012 11:32 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:08 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not
clear
and optimal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 53 +++++++++++++++++++++--------
include/configs/km/km_arm.h | 1 + 2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..e4ae1fb 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -247,15 +247,12 @@ int board_early_init_f(void) kirkwood_mpp_conf(kwmpp_config, NULL);
/*
* The FLASH_GPIO_PIN switches between using a
* The KM_FLASH_GPIO_PIN switches between using a*/
- NAND or a SPI FLASH. Set this pin on start
- to NAND mode.
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C) /* init the GPIO for I2C Bitbang driver */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); @@ -284,35 +281,41 @@ int board_init(void) return 0; }
+int km_hw_spi_bus_claim(int on) +{
- int gpio_value = !on;
- if (on) {
kwmpp_config[0] = MPP0_SPI_SCn;kwmpp_config[1] = MPP1_SPI_MOSI;kwmpp_config[2] = MPP2_SPI_SCK;kwmpp_config[3] = MPP3_SPI_MISO;- } else {
kwmpp_config[0] = MPP0_NF_IO2;kwmpp_config[1] = MPP1_NF_IO3;kwmpp_config[2] = MPP2_NF_IO4;kwmpp_config[3] = MPP3_NF_IO5;- }
NACK...
Could you please be a bit more verbose. Why do you NACK this? This code is only related to our boards...
Dear Holger We have already patches for Kirkwood-spi in place that address this. So we have to use this framework.
Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html
ok I see what you mean. We make use of it later on: [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release I'll squash this one together with 02/20 then it is more clear.
ok I'll send an update of the SPI feature update soon as a standalone patch. I'll squash
[PATCH 01/20] arm/km: enable spi claim bus [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release [PATCH 19/20] arm/km: remove spi toggle command
into it and then it is much more clear what the patch does.
Updates with your inputs of the remaining patches will also follow.
Regards Holger
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- arch/arm/include/asm/arch-kirkwood/config.h | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 91164eb..a9499b7 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -82,9 +82,15 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif #endif
/*
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details: - IVM EEPROM is at adress: pca9547:70:9 - PCI is enabled - PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC) + kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)
diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg new file mode 100644 index 0000000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/128M16-1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15] + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay + +DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) + +DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e4ae1fb..ffe13cd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -133,10 +133,11 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ + defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { @@ -384,7 +385,7 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#else +#elif !defined(CONFIG_KM_PIGGY4_88E6352) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/boards.cfg b/boards.cfg index b711e0d..1a4c2ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pogo_e02 arm arm926ejs - clouden dns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 28b5021..a35ef61 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif + #include "asm/arch/config.h"
#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -211,6 +218,15 @@ int get_scl(void); /* * Environment variables configurations */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ +#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ +#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 #define CONFIG_ENV_EEPROM_IS_ON_I2C @@ -218,11 +234,11 @@ int get_scl(void); #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -245,17 +261,27 @@ int get_scl(void); "sf write ${load_addr_r} 0 ${filesize};" \ "spi off\0"
-/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " xstr(CONFIG_ENV_OFFSET) " " \ + xstr(CONFIG_ENV_TOTAL_SIZE)"\0" +#else +#define CONFIG_KM_NEW_ENV \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" +#endif + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_NEW_ENV \ "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ "" diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index f639edc..97aa617 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -6,8 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de + * (C) Copyright 2011-2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com * * See file CREDITS for list of people who contributed to this * project. @@ -36,23 +37,67 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H
-/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ #if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #undef CONFIG_KIRKWOOD_PCIE_INIT +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile NUSA" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_PIGGY4_88E6352 + +#else +#error ("Board unsupported") #endif
+/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h" + #define CONFIG_HOSTNAME km_kirkwood
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#endif + +#if defined(CONFIG_KM_PIGGY4_88E6352) +/* + * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via + * an Marvell 88E6352 simple switch. + * In this case we have to change the default settings for the etherent mac. + * There is NO ethernet phy. The ARM and Switch are conencted directly over + * RGMII in MAC-MAC mode + * In this case 1GBit full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_1000 |\ + MVGBE_SET_MII_SPEED_TO_100) + +#endif
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++
Please avoid file names starting with numbers.
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)
Again.... I would like to suggest to separate out new boards addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.
It's always faster to merger small patch series that big one.
mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg new file mode 100644 index 0000000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/128M16-1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +#
+# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7]
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15]
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23]
+# MPP Control 3-6 Register untouched (MPP24-49)
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved
+# ??? Missing register # CPU RAM Management Control2 Register
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin
+# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved
+DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required
+DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required
+DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB)
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved
+# End of Header extension
Is this configuration similar to any other board already mainlined? if there is small delta like RAM/flash sizes then you can manage it through board_init()
Just think of it.
+DATA 0x0 0x0 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e4ae1fb..ffe13cd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -133,10 +133,11 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
defined(CONFIG_KM_PIGGY4_88E6352))/*
- These two boards have always ethernet present. Its connected to
the mv
- switch.
- All boards with PIGGY4 connected via a simple switch have ethernet
always
*/
- present.
int ethernet_present(void) { @@ -384,7 +385,7 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#else +#elif !defined(CONFIG_KM_PIGGY4_88E6352) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/boards.cfg b/boards.cfg index b711e0d..1a4c2ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pogo_e02 arm arm926ejs
cloudendns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +kmnusa arm arm926ejs km_arm
Why name is not km_nusa?
keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 28b5021..a35ef61 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif
Do you still need this? Your patch 03/20 takes care of this.
#include "asm/arch/config.h"
#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -211,6 +218,15 @@ int get_scl(void); /*
- Environment variables configurations
*/ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ +#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ +#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)+#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 #define CONFIG_ENV_EEPROM_IS_ON_I2C @@ -218,11 +234,11 @@ int get_scl(void); #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0"
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -245,17 +261,27 @@ int get_scl(void); "sf write ${load_addr_r} 0 ${filesize};" \ "spi off\0"
-/*
- Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \
"newenv=sf probe 0;" \"sf erase " xstr(CONFIG_ENV_OFFSET) " " \xstr(CONFIG_ENV_TOTAL_SIZE)"\0"+#else +#define CONFIG_KM_NEW_ENV \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"+#endif
+/*
- Default environment variables
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \CONFIG_KM_NEW_ENV \ "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ ""diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index f639edc..97aa617 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -6,8 +6,9 @@
- (C) Copyright 2009
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- (C) Copyright 2011
- Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de
- (C) Copyright 2011-2012
- Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
- Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
- See file CREDITS for list of people who contributed to this
- project.
@@ -36,23 +37,67 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H
-/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h"
-/*
- Version number information
- */
#if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #undef CONFIG_KIRKWOOD_PCIE_INIT +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile NUSA" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg+#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_PIGGY4_88E6352
+#else +#error ("Board unsupported") #endif
+/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h"
#define CONFIG_HOSTNAME km_kirkwood
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#endif
+#if defined(CONFIG_KM_PIGGY4_88E6352) +/*
- Some keymile boards like mgcoge5un & nusa1 have their PIGGY4
connected via
- an Marvell 88E6352 simple switch.
- In this case we have to change the default settings for the
etherent mac.
- There is NO ethernet phy. The ARM and Switch are conencted
directly over
- RGMII in MAC-MAC mode
- In this case 1GBit full duplex and autoneg off
- */
+#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \MVGBE_ADV_NO_FLOW_CTRL | \MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \MVGBE_FORCE_BP_MODE_NO_JAM | \(1 << 9) /* Reserved bit has to be 1 */ | \MVGBE_DO_NOT_FORCE_LINK_FAIL | \MVGBE_DIS_AUTO_NEG_SPEED_GMII | \MVGBE_DTE_ADV_0 | \MVGBE_MIIPHY_MAC_MODE | \MVGBE_AUTO_NEG_NO_CHANGE | \MVGBE_MAX_RX_PACKET_1552BYTE | \MVGBE_CLR_EXT_LOOPBACK | \MVGBE_SET_FULL_DUPLEX_MODE | \MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\MVGBE_SET_GMII_SPEED_TO_1000 |\MVGBE_SET_MII_SPEED_TO_100)+#endif
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
#define KM_XLX_PROGRAM_B_PIN 39
1.7.1
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++
Please avoid file names starting with numbers.
would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance to know which organisation this RAM has.
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg new file mode 100644 index 0000000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/128M16-1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +#
+# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7]
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15]
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23]
+# MPP Control 3-6 Register untouched (MPP24-49)
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved
+# ??? Missing register # CPU RAM Management Control2 Register
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin
+# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved
+DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required
+DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required
+DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB)
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved
+# End of Header extension
Is this configuration similar to any other board already mainlined? if there is small delta like RAM/flash sizes then you can manage it through board_init()
Just think of it.
I would like to keep it as it is.
+DATA 0x0 0x0 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e4ae1fb..ffe13cd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -133,10 +133,11 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
defined(CONFIG_KM_PIGGY4_88E6352))/*
- These two boards have always ethernet present. Its connected to
the mv
- switch.
- All boards with PIGGY4 connected via a simple switch have ethernet
always
*/
- present.
int ethernet_present(void) { @@ -384,7 +385,7 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#else +#elif !defined(CONFIG_KM_PIGGY4_88E6352) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/boards.cfg b/boards.cfg index b711e0d..1a4c2ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pogo_e02 arm arm926ejs
cloudendns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +kmnusa arm arm926ejs km_arm
Why name is not km_nusa?
Could be also km_nusa. But isn't it up to us how we name our boards?
keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 28b5021..a35ef61 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif
Do you still need this? Your patch 03/20 takes care of this.
Yes we need it. Patch 03/20 makes it possible to overwrite these default values. And in this patch we use 5MHz as max frequency rather than 50MHz which is the default setting.
Regards Holger
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:04 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp;
Gerlando
Falauto; Prafulla Wadaskar Subject: [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++
Please avoid file names starting with numbers.
would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance to know which organisation this RAM has.
I think kwbimage_128M16_1.cfg should be okay, BTW: if the configuration is similar to any other already supported board, may you think to reuse the same.
Regards.. Prafulla . . .
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg new file mode 100644 index 0000000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/128M16-1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public
License
+# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to
configure
+# and create kirkwood boot image +#
+# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7]
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15]
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23]
+# MPP Control 3-6 Register untouched (MPP24-49)
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3
Register
+# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved
+# ??? Missing register # CPU RAM Management Control2 Register
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1
Register
+# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0
Register
+# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin
+# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling
Logic
+# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care
for
APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-
399MHz,
unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles
value
+1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved
+DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required
+DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required
+DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start
command
+# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write
start
command +# with the considered SDRAM internal delay
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB)
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from
DRAM
CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM
CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register
above
+# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from
DRAM
bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved
+# End of Header extension
Is this configuration similar to any other board already mainlined?
if there is small delta like RAM/flash sizes then you can manage it through board_init()
Just think of it.
I would like to keep it as it is.
+DATA 0x0 0x0 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e4ae1fb..ffe13cd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -133,10 +133,11 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
defined(CONFIG_KM_PIGGY4_88E6352))/*
- These two boards have always ethernet present. Its connected to
the mv
- switch.
- All boards with PIGGY4 connected via a simple switch have
ethernet
always
*/
- present.
int ethernet_present(void) { @@ -384,7 +385,7 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#else +#elif !defined(CONFIG_KM_PIGGY4_88E6352) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/boards.cfg b/boards.cfg index b711e0d..1a4c2ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pogo_e02 arm
arm926ejs
cloudendns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood
km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa arm arm926ejs km_arm
Why name is not km_nusa?
Could be also km_nusa. But isn't it up to us how we name our boards?
keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h
b/include/configs/km/km_arm.h
index 28b5021..a35ef61 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif
Do you still need this? Your patch 03/20 takes care of this.
Yes we need it. Patch 03/20 makes it possible to overwrite these default values. And in this patch we use 5MHz as max frequency rather than 50MHz which is the default setting.
Regards Holger
On 06/12/2012 11:40 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:04 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp;
Gerlando
Falauto; Prafulla Wadaskar Subject: [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++
Please avoid file names starting with numbers.
would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance to know which organisation this RAM has.
I think kwbimage_128M16_1.cfg should be okay, BTW: if the configuration is similar to any other already supported board, may you think to reuse the same.
yes of course, but it isn't. I'll fix the naming in a v2.
Regards Holger
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:04 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
...snip...
+# End of Header extension
Is this configuration similar to any other board already mainlined?
if there is small delta like RAM/flash sizes then you can manage it through board_init()
Just think of it.
I would like to keep it as it is.
Okay
+DATA 0x0 0x0 diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e4ae1fb..ffe13cd 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -133,10 +133,11 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
defined(CONFIG_KM_PIGGY4_88E6352))/*
- These two boards have always ethernet present. Its connected to
the mv
- switch.
- All boards with PIGGY4 connected via a simple switch have
ethernet
always
*/
- present.
int ethernet_present(void) { @@ -384,7 +385,7 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#else +#elif !defined(CONFIG_KM_PIGGY4_88E6352) /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/boards.cfg b/boards.cfg index b711e0d..1a4c2ad 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pogo_e02 arm
arm926ejs
cloudendns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood
km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
+kmnusa arm arm926ejs km_arm
Why name is not km_nusa?
Could be also km_nusa. But isn't it up to us how we name our boards?
So why your some boards named as kw_xxx and some kmxxx? to me it doesn't sound good.
Anyways the call is yours here.
keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h
b/include/configs/km/km_arm.h
index 28b5021..a35ef61 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif
Do you still need this? Your patch 03/20 takes care of this.
Yes we need it. Patch 03/20 makes it possible to overwrite these default values. And in this patch we use 5MHz as max frequency rather than 50MHz which is the default setting.
So we can only address delta.
Regards.. Prafulla . . .
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 14:04 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp;
Gerlando
Falauto; Prafulla Wadaskar Subject: [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.brunck@keymile.com
This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/128M16-1.cfg | 294 +++++++++++++++++++++++++++++++++++++
Please avoid file names starting with numbers.
would sdram128M16-1.cfg be ok? The reason for this numbering is to have a chance to know which organisation this RAM has.
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
I agree, let's separate out - 1. bugfix/updates patch series to current code 2. "Kirkwood specific" means the changes to the Kirkwood related file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/* 3. Additional board supports
And if possible these patches should be independent so that can be pulled independently
Regards. Prafulla . . .
On 06/12/2012 11:57 AM, Prafulla Wadaskar wrote:
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic kirkwood specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
I agree, let's separate out -
- bugfix/updates patch series to current code
- "Kirkwood specific" means the changes to the Kirkwood related file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
- Additional board supports
And if possible these patches should be independent so that can be pulled independently
the only patch in the serie which modifies common Kirkwood related files are: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
Do you want me to send this one seperately? I can do that. So then we resend again a new patch serie I guess...
The other stuff is only related to our boards and I would like to keep it as it is. It would cause a lot of rebasing and reorganisation and in the end the result is the same.
Regards Holger
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 16:07 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 11:57 AM, Prafulla Wadaskar wrote:
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic
kirkwood
specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
I agree, let's separate out -
- bugfix/updates patch series to current code
- "Kirkwood specific" means the changes to the Kirkwood related
file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
- Additional board supports
And if possible these patches should be independent so that can be
pulled independently
the only patch in the serie which modifies common Kirkwood related files are: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
Do you want me to send this one seperately? I can do that. So then we resend again a new patch serie I guess...
It would be a great you can split 20 patches in to smaller patch series as per above suggestion.
The other stuff is only related to our boards and I would like to keep it as it is. It would cause a lot of rebasing and reorganisation and in the end the result is the same.
I can understand what you mean, I would be happy if you can keep this stuff small, simple and more structured (preferred least usage of #ifdef)
Regards.. Prafulla . . .
On 06/12/2012 01:09 PM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 16:07 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 11:57 AM, Prafulla Wadaskar wrote:
board/keymile/km_arm/km_arm.c | 9 +- boards.cfg | 1 + include/configs/km/km_arm.h | 44 +++++- include/configs/km_kirkwood.h | 67 +++++++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org Valentin Longchamp valentin.longchamp@keymile.com
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa ARM926EJS (Kirkwood SoC)Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic
kirkwood
specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to be kirkwood specific? This is all board related code.
I agree, let's separate out -
- bugfix/updates patch series to current code
- "Kirkwood specific" means the changes to the Kirkwood related
file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
- Additional board supports
And if possible these patches should be independent so that can be
pulled independently
the only patch in the serie which modifies common Kirkwood related files are: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
Do you want me to send this one seperately? I can do that. So then we resend again a new patch serie I guess...
It would be a great you can split 20 patches in to smaller patch series as per above suggestion.
Again, the only patch wich is common Kirkwood related is the above mentioned patch. I can extract this one if you want me to.
All others are somehow interconnected and therefore it makes sense to have it in one patch serie.
Regards Holger
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 17:13 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 01:09 PM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 16:07 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 11:57 AM, Prafulla Wadaskar wrote:
> board/keymile/km_arm/km_arm.c | 9 +- > boards.cfg | 1 + > include/configs/km/km_arm.h | 44 +++++- > include/configs/km_kirkwood.h | 67 +++++++-- > 6 files changed, 392 insertions(+), 24 deletions(-) > create mode 100644 board/keymile/km_arm/128M16-1.cfg > > diff --git a/MAINTAINERS b/MAINTAINERS > index 0445539..aa11268 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org > Valentin Longchamp valentin.longchamp@keymile.com > > km_kirkwood ARM926EJS (Kirkwood SoC) > + kmnusa ARM926EJS (Kirkwood SoC)
Again.... I would like to suggest to separate out new boards
addition, bugfixes/updates specific to km_*boards and generic
kirkwood
specific patches.
It's always faster to merger small patch series that big one.
Yes ok, but was has this to do with this patch? What is meant to
be
kirkwood specific? This is all board related code.
I agree, let's separate out -
- bugfix/updates patch series to current code
- "Kirkwood specific" means the changes to the Kirkwood related
file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
- Additional board supports
And if possible these patches should be independent so that can be
pulled independently
the only patch in the serie which modifies common Kirkwood related files are: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
Do you want me to send this one seperately? I can do that. So then
we
resend again a new patch serie I guess...
It would be a great you can split 20 patches in to smaller patch
series as per above suggestion.
Again, the only patch wich is common Kirkwood related is the above mentioned patch. I can extract this one if you want me to.
Yes, extract this and send it as standalone
All others are somehow interconnected and therefore it makes sense to have it in one patch serie.
Send one patch series which are related to updates/fixes to already supported code.
Then send anther patch series for addition of new boards, mention the dependency if any.
Regards.. Prafulla . . .
On 06/12/2012 01:50 PM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 17:13 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 01:09 PM, Prafulla Wadaskar wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 12 June 2012 16:07 To: Prafulla Wadaskar Cc: Valentin Longchamp; prafulla@mavell.com; u-boot@lists.denx.de; Gerlando Falauto Subject: Re: [PATCH 04/20] arm/km: add kmnusa board support
On 06/12/2012 11:57 AM, Prafulla Wadaskar wrote:
>> board/keymile/km_arm/km_arm.c | 9 +- >> boards.cfg | 1 + >> include/configs/km/km_arm.h | 44 +++++- >> include/configs/km_kirkwood.h | 67 +++++++-- >> 6 files changed, 392 insertions(+), 24 deletions(-) >> create mode 100644 board/keymile/km_arm/128M16-1.cfg >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 0445539..aa11268 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -738,6 +738,7 @@ Sergey Lapin slapin@ossfans.org >> Valentin Longchamp valentin.longchamp@keymile.com >> >> km_kirkwood ARM926EJS (Kirkwood SoC) >> + kmnusa ARM926EJS (Kirkwood SoC) > > Again.... I would like to suggest to separate out new boards addition, bugfixes/updates specific to km_*boards and generic
kirkwood
specific patches. > > It's always faster to merger small patch series that big one. >
Yes ok, but was has this to do with this patch? What is meant to
be
kirkwood specific? This is all board related code.
I agree, let's separate out -
- bugfix/updates patch series to current code
- "Kirkwood specific" means the changes to the Kirkwood related
file that may affects other boards, for ex arch/arm/cpu/arm926ejs/mach-kirkwood/*
- Additional board supports
And if possible these patches should be independent so that can be
pulled independently
the only patch in the serie which modifies common Kirkwood related files are: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
Do you want me to send this one seperately? I can do that. So then
we
resend again a new patch serie I guess...
It would be a great you can split 20 patches in to smaller patch
series as per above suggestion.
Again, the only patch wich is common Kirkwood related is the above mentioned patch. I can extract this one if you want me to.
Yes, extract this and send it as standalone
ok done.
All others are somehow interconnected and therefore it makes sense to have it in one patch serie.
Send one patch series which are related to updates/fixes to already supported code.
Then send anther patch series for addition of new boards, mention the dependency if any.
Sorry but this does not make sense to me, why should we provide independent patch series which are in the end not independent?
Why is it important to first add updates for old boards and then add new boards? This causes a lot of work for rebasing and retesting for an already well tested patch serie. Can't we focus on your precise inputs to the real code and not on the sequence of the patches?
Best regards Holger
From: Holger Brunck holger.brunck@keymile.com
For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- MAINTAINERS | 1 + board/keymile/km_arm/256M8-1.cfg | 296 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/km_kirkwood.h | 16 ++- 4 files changed, 312 insertions(+), 2 deletions(-) create mode 100644 board/keymile/km_arm/256M8-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index aa11268..ef57cd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Valentin Longchamp valentin.longchamp@keymile.com km_kirkwood ARM926EJS (Kirkwood SoC) kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) + kmcoge5un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC)
Nishanth Menon nm@ti.com diff --git a/board/keymile/km_arm/256M8-1.cfg b/board/keymile/km_arm/256M8-1.cfg new file mode 100644 index 0000000..3e1237b --- /dev/null +++ b/board/keymile/km_arm/256M8-1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles + +DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 1a4c2ad..d174371 100644 --- a/boards.cfg +++ b/boards.cfg @@ -142,6 +142,7 @@ km_kirkwood arm arm926ejs km_arm keymile km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood +kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 97aa617..e6f0e36 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -39,15 +39,18 @@
#if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_HOSTNAME km_kirkwood #undef CONFIG_KIRKWOOD_PCIE_INIT #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_HOSTNAME km_kirkwood_pci #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile NUSA" +#define CONFIG_HOSTNAME kmnusa #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg @@ -55,6 +58,17 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352
+#elif defined(CONFIG_KMCOGE5UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE5UN" +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/256M8-1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_HOSTNAME kmcoge5un +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6352 #else #error ("Board unsupported") #endif @@ -62,8 +76,6 @@ /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h"
-#define CONFIG_HOSTNAME km_kirkwood - #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ #endif
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 05/20] arm/km: add kmcoge5un board support
From: Holger Brunck holger.brunck@keymile.com
For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new
What are the changes in SDRAM? Can that be handled through board_init() instead of adding a configuration file?
SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
MAINTAINERS | 1 + board/keymile/km_arm/256M8-1.cfg | 296
Please do not use names starting with numbers.
++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/km_kirkwood.h | 16 ++- 4 files changed, 312 insertions(+), 2 deletions(-) create mode 100644 board/keymile/km_arm/256M8-1.cfg
diff --git a/MAINTAINERS b/MAINTAINERS index aa11268..ef57cd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Valentin Longchamp valentin.longchamp@keymile.com km_kirkwood ARM926EJS (Kirkwood SoC) kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC)
kmcoge5un ARM926EJS (Kirkwood SoC)
Can it be km_coge5un?
portl2 ARM926EJS (Kirkwood SoC)Nishanth Menon nm@ti.com diff --git a/board/keymile/km_arm/256M8-1.cfg b/board/keymile/km_arm/256M8-1.cfg new file mode 100644 index 0000000..3e1237b --- /dev/null +++ b/board/keymile/km_arm/256M8-1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C
+# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7]
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23]
+# MPP Control 3-6 Register untouched (MPP24-49)
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved
+# ??? Missing register # CPU RAM Management Control2 Register
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin
+# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay
+DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved
+DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required
+DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required
+DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB)
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required
+DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved
+# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 1a4c2ad..d174371 100644 --- a/boards.cfg +++ b/boards.cfg @@ -142,6 +142,7 @@ km_kirkwood arm arm926ejs km_arm keymile km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood +kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 97aa617..e6f0e36 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -39,15 +39,18 @@
#if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_HOSTNAME km_kirkwood #undef CONFIG_KIRKWOOD_PCIE_INIT #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_HOSTNAME km_kirkwood_pci #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile NUSA" +#define CONFIG_HOSTNAME kmnusa #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/128M16-1.cfg @@ -55,6 +58,17 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352
+#elif defined(CONFIG_KMCOGE5UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE5UN" +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/256M8-1.cfg+#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_HOSTNAME kmcoge5un
Changes related to CONFIG_HOSTNAME does not looks new board addition related, it's good to abstract them out as updates of bugfixes.
Regards.. Prafulla . . .
From: Holger Brunck holger.brunck@keymile.com
Use the generic header km_kirkwood.h and get rid of the board specific header.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 9 ++-- boards.cfg | 2 +- include/configs/km_kirkwood.h | 46 +++++++++++++++++++++ include/configs/mgcoge3un.h | 87 ----------------------------------------- 4 files changed, 51 insertions(+), 93 deletions(-) delete mode 100644 include/configs/mgcoge3un.h
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ffe13cd..5133446 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -113,7 +113,7 @@ u32 kwmpp_config[] = { 0 };
-#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -133,8 +133,7 @@ int startup_allowed(void) } #endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ - defined(CONFIG_KM_PIGGY4_88E6352)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* * All boards with PIGGY4 connected via a simple switch have ethernet always * present. @@ -202,7 +201,7 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -351,7 +350,7 @@ void dram_init_banksize(void) } }
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
#define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index d174371..9e4de8e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -141,7 +141,7 @@ dns325 arm arm926ejs - d-link km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA -mgcoge3un arm arm926ejs km_arm keymile kirkwood +mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index e6f0e36..d1f3351 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -58,6 +58,20 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352
+/* KM_MGCOGE3UN */ +#elif defined(CONFIG_KM_MGCOGE3UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE3UN" +#define CONFIG_HOSTNAME mgcoge3un +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6061 + +/* KMCOGE5UN */ #elif defined(CONFIG_KMCOGE5UN) #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ @@ -111,7 +125,39 @@
#endif
+#ifdef CONFIG_KM_PIGGY4_88E6061 +/* + * Some keymile boards like mgcoge3un have their PIGGY4 connected via + * an Marvell 88E6061 simple switch. + * In this case we have to change the default settings for the + * ethernet phy connected to the kirkwood. + * In this case 100MB full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) +#endif + /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39
+#ifdef CONFIG_KM_DISABLE_PCI +#undef CONFIG_KIRKWOOD_PCIE_INIT +#endif #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h deleted file mode 100644 index 156821c..0000000 --- a/include/configs/mgcoge3un.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_MGCOGE3UN_H -#define _CONFIG_MGCOGE3UN_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN" -#define CONFIG_HOSTNAME mgcoge3un -#define CONFIG_MGCOGE3UN - -#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ - -/* we use a new RAM type on mgcoge3un board */ -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg - -/* - * mgcoge3un has a fixed link to the marvell switch - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" -#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 - -/* - * PCIe port not used on mgcoge3un - */ -#undef CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_MGCOGE3UN_H */
From: Holger Brunck holger.brunck@keymile.com
The additional headerfile is unneeded here, we can use the generic km_kirkwood.h instead. And we can use the better config option KM_PIGGY4_88E6061 for the specific features for boards with this design in km_arm.c.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 2 +- boards.cfg | 2 +- include/configs/km_kirkwood.h | 8 ++++ include/configs/portl2.h | 85 ----------------------------------------- 4 files changed, 10 insertions(+), 87 deletions(-) delete mode 100644 include/configs/portl2.h
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5133446..f59ebfc 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -350,7 +350,7 @@ void dram_init_banksize(void) } }
-#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061))
#define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 9e4de8e..4ca611a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -143,7 +143,7 @@ km_kirkwood_pci arm arm926ejs km_arm keymile kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN -portl2 arm arm926ejs km_arm keymile kirkwood +portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index d1f3351..fbe714b 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -83,6 +83,14 @@ #define CONFIG_HOSTNAME kmcoge5un #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_PIGGY4_88E6352 + +/* KM_PORTL2 */ +#elif defined(CONFIG_KM_PORTL2) +#define CONFIG_IDENT_STRING "\nKeymile Port-L2" +#define CONFIG_HOSTNAME portl2 +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_PIGGY4_88E6061 + #else #error ("Board unsupported") #endif diff --git a/include/configs/portl2.h b/include/configs/portl2.h deleted file mode 100644 index e436cfe..0000000 --- a/include/configs/portl2.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar prafulla@marvell.com - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. - * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_PORTL2_H -#define _CONFIG_PORTL2_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile Port-L2" -#define CONFIG_HOSTNAME portl2 -#define CONFIG_PORTL2 - -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ -/* - * Note: This is only valid for HW > P1A if you got an outdated P1A - * use KM_ENV_BUS "pca9544a:70:a" - */ -#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ - -/* - * portl2 has a fixed link to the XMPP backplane - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -/* - * portl2 does use the PCIe Port0 - */ -#define CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_PORTL2_H */
This is achieved thanks to the support read/write regs for the external 88e6352 switch. The functions for this are added into an own file managed_switch.c. This is compiled if the define CONFIG_KM_MANAGED_SW_ADDR was set in the board setup. This define specifies the phy address.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/common/common.h | 6 + board/keymile/km_arm/Makefile | 4 + board/keymile/km_arm/km_arm.c | 26 +++++- board/keymile/km_arm/managed_switch.c | 166 +++++++++++++++++++++++++++++++++ include/configs/km_kirkwood.h | 13 +++ 5 files changed, 214 insertions(+), 1 deletions(-) create mode 100644 board/keymile/km_arm/managed_switch.c
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 6c1f640..49225b8 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -125,6 +125,12 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void);
+ +int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 data); +int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 *data); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index aa51255..06079e9 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_MANAGED_SW_ADDR +COBJS += managed_switch.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index f59ebfc..8f0a7c3 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -9,6 +9,9 @@ * (C) Copyright 2010 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * + * (C) Copyright 2011, 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -35,6 +38,7 @@ #include <miiphy.h> #include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/errno.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h>
@@ -384,7 +388,27 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } -#elif !defined(CONFIG_KM_PIGGY4_88E6352) +#elif defined(CONFIG_KM_PIGGY4_88E6352) + +#if defined(CONFIG_KM_MANAGED_SW_ADDR) +void reset_phy(void) +{ + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* enable autoneg on port 0 phy */ + ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300); + + /* egress broadcast franes on all macs, with forwarding */ + ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f); + ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f); + ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f); +} +#endif + +#else /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { diff --git a/board/keymile/km_arm/managed_switch.c b/board/keymile/km_arm/managed_switch.c new file mode 100644 index 0000000..482c18d --- /dev/null +++ b/board/keymile/km_arm/managed_switch.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/errno.h> + +#define SMI_HDR ((0x8 | 0x1) << 12) +#define SMI_BUSY_MASK (0x8000) +#define SMIRD_OP (0x2 << 10) +#define SMIWR_OP (0x1 << 10) +#define SMI_MASK 0x1f +#define PORT_SHIFT 5 + +#define COMMAND_REG 0 +#define DATA_REG 1 + +static int ext_switch_wait_rdy(const char *devname, u8 phy_addr) +{ + u16 command; + u32 timeout = 100; + int ret; + + /* wait till the SMI is not busy */ + do { + /* read command register */ + ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); + if (ret < 0) { + printf("%s: Error reading command register\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf("Err..(%s) SMI busy timeout\n", __func__); + return -EFAULT; + } + } while (command & SMI_BUSY_MASK); + + return 0; +} + +int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 *data) +{ + int ret; + u16 command; + + ret = ext_switch_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + command = SMI_HDR | SMIRD_OP | ((port&SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, command); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, command); + if (ret) + return ret; + + ret = ext_switch_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + ret = miiphy_read(devname, phy_addr, DATA_REG, data); + + return ret; +} + +int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, + u8 reg, u16 data) +{ + int ret; + u16 value; + + ret = ext_switch_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + debug("%s: write to data: %#x\n", __func__, data); + ret = miiphy_write(devname, phy_addr, DATA_REG, data); + if (ret) + return ret; + + value = SMI_HDR | SMIWR_OP | ((port & SMI_MASK) << PORT_SHIFT) | + (reg & SMI_MASK); + debug("%s: write to command: %#x\n", __func__, value); + ret = miiphy_write(devname, phy_addr, COMMAND_REG, value); + if (ret) + return ret; + + ret = ext_switch_wait_rdy(devname, phy_addr); + if (ret) + return ret; + + return 0; +} + +int do_sw_reg_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name = "egiga0"; + u16 value = 0, phyaddr, reg, port; + int ret; + + if (argc < 4) + return cmd_usage(cmdtp); + + phyaddr = simple_strtoul(argv[1], NULL, 16); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + + ret = ext_switch_reg_read(name, phyaddr, port, reg, &value); + printf("%#x\n", value); + + return ret; +} + +U_BOOT_CMD( + sw_reg_read, 4, 1, do_sw_reg_read, + "read the switch registers", + "<phyaddr> <port> <reg>\n" + ); + +int do_sw_reg_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name = "egiga0"; + u16 value = 0, phyaddr, reg, port; + int ret; + + if (argc < 5) + return cmd_usage(cmdtp); + + phyaddr = simple_strtoul(argv[1], NULL, 16); + port = simple_strtoul(argv[2], NULL, 10); + reg = simple_strtoul(argv[3], NULL, 10); + value = simple_strtoul(argv[4], NULL, 16); + + ret = ext_switch_reg_write(name, phyaddr, port, reg, value); + + return ret; +} + +U_BOOT_CMD( + sw_reg_write, 5, 1, do_sw_reg_write, + "write the the switch registers", + "<phyaddr> <port> <reg> <value>\n" + ); + diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index fbe714b..059fdbc 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -58,6 +58,7 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352
+#define CONFIG_KM_MANAGED_SW_ADDR 0x10 /* KM_MGCOGE3UN */ #elif defined(CONFIG_KM_MGCOGE3UN) #define CONFIG_IDENT_STRING "\nKeymile COGE3UN" @@ -131,6 +132,18 @@ MVGBE_SET_GMII_SPEED_TO_1000 |\ MVGBE_SET_MII_SPEED_TO_100)
+/* + * There is no phy on the eth interface, but an external switch + * For kmcoge5un it is completely unmanaged, so we disable an access to it + * For km_nusa, we an MDIO(MII) interface that can configure the switch trough + * an indirect access, so we do not disable the MII + */ +#ifndef CONFIG_KM_MANAGED_SW_ADDR +#undef CONFIG_MII +#undef CONFIG_CMD_MII +#undef CONFIG_RESET_PHY_R +#endif + #endif
#ifdef CONFIG_KM_PIGGY4_88E6061
This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running
The boards with a PCIe FPGA but without BOCO2 still are supported.
The config option name is CONFIG_KM_FPGA_CONFIG
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/common/common.h | 6 + board/keymile/km_arm/Makefile | 4 + board/keymile/km_arm/fpga_config.c | 212 ++++++++++++++++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 21 +++- boards.cfg | 2 +- include/configs/km/km_arm.h | 3 + include/configs/km_kirkwood.h | 8 +- 7 files changed, 246 insertions(+), 10 deletions(-) create mode 100644 board/keymile/km_arm/fpga_config.c
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 49225b8..c58e565 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -131,6 +131,12 @@ int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, u8 reg, u16 *data);
+ +int trigger_fpga_config(void); +int wait_for_fpga_config(void); +int fpga_reset(void); +int toggle_eeprom_spi_bus(void); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index 06079e9..bd824e2 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_FPGA_CONFIG +COBJS += fpga_config.o +endif + ifdef CONFIG_KM_MANAGED_SW_ADDR COBJS += managed_switch.o endif diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c new file mode 100644 index 0000000..4356b9a --- /dev/null +++ b/board/keymile/km_arm/fpga_config.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> + +/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ +#define KM_XLX_PROGRAM_B_PIN 39 + +#define BOCO_ADDR 0x10 + +#define ID_REG 0x00 +#define BOCO2_ID 0x5b + +static int check_boco2(void) +{ + int ret; + u8 id; + + ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); + if (ret) { + printf("%s: error reading the BOCO id !!\n", __func__); + return ret; + } + + return (id == BOCO2_ID); +} + +static int boco_clear_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval &= ~flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int boco_set_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval |= flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +#define SPI_REG 0x06 +#define CFG_EEPROM 0x02 +#define FPGA_PROG 0x04 +#define FPGA_DONE 0x20 + +int trigger_fpga_config(void) +{ + int ret = 0; + + if (check_boco2()) { + /* we have a BOCO2, this has to be triggered here */ + + /* make sure the FPGA_can access the EEPROM */ + ret = boco_clear_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + /* trigger the config start */ + ret = boco_clear_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + /* up signal for pulse end */ + ret = boco_set_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + } else { + /* we do it the old way, with the gpio pin */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + /* small delay for the pulse */ + udelay(10); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + } + + return 0; +} + +int wait_for_fpga_config(void) +{ + int ret = 0; + u8 spictrl; + u32 timeout = 20000; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe FPGA config:"); + do { + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); + if (ret) { + printf("%s: error reading the BOCO spictrl !!\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + return -EFAULT; + } + udelay(10); + } while (!(spictrl & FPGA_DONE)); + + printf(" done\n"); + + return 0; +} + +#define PRST1 0x4 +#define BRIDGE_RST 0x4 + +int fpga_reset(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_clear_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + ret = boco_set_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + return 0; +} + +/* the FPGA was configured, we configure the BOCO2 so that the EEPROM + * is available from the Bobcat SPI bus */ +int toggle_eeprom_spi_bus(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_set_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + return 0; +} + diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 8f0a7c3..a062333 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -268,12 +268,6 @@ int board_early_init_f(void) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); -#endif return 0; }
@@ -282,6 +276,21 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif + return 0; }
diff --git a/boards.cfg b/boards.cfg index 4ca611a..0fb8811 100644 --- a/boards.cfg +++ b/boards.cfg @@ -139,7 +139,7 @@ calimain arm arm926ejs calimain omicron pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index a35ef61..66f382b 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -311,4 +311,7 @@ int get_scl(void); #define CONFIG_POST_EXTERNAL_WORD_FUNCS #define CONFIG_CMD_DIAG
+/* we do the whole PCIe FPGA config stuff here */ +#define BOARD_LATE_INIT + #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 059fdbc..7d38413 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -175,10 +175,12 @@ MVGBE_SET_MII_SPEED_TO_100) #endif
-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 - #ifdef CONFIG_KM_DISABLE_PCI #undef CONFIG_KIRKWOOD_PCIE_INIT #endif + +#ifndef CONFIG_KM_FPGA_CONFIG +#undef BOARD_LATE_INIT +#endif + #endif /* _CONFIG_KM_KIRKWOOD */
From: Holger Brunck holger.brunck@keymile.com
Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- boards.cfg | 4 ++-- include/configs/km_kirkwood.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 0fb8811..9569d1a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 7d38413..549122b 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -37,15 +37,20 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H
+/* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #define CONFIG_HOSTNAME km_kirkwood -#undef CONFIG_KIRKWOOD_PCIE_INIT +#define CONFIG_KM_DISABLE_PCIE #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ + +/* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" #define CONFIG_HOSTNAME km_kirkwood_pci #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_FPGA_CONFIG + /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 10/20] arm/km: cleanup km_kirkwood boards
From: Holger Brunck holger.brunck@keymile.com
Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
boards.cfg | 4 ++-- include/configs/km_kirkwood.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 0fb8811..9569d1a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN
Can you maintain uniform naming here KMCODE5SUN should be KM_CODE5UN?
Regards.. Prafulla . . .
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Holger Brunck; u-boot@lists.denx.de; Valentin Longchamp; Gerlando Falauto; Prafulla Wadaskar Subject: [PATCH 10/20] arm/km: cleanup km_kirkwood boards
From: Holger Brunck holger.brunck@keymile.com
Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
boards.cfg | 4 ++-- include/configs/km_kirkwood.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/boards.cfg b/boards.cfg index 0fb8811..9569d1a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KMCOGE5UN
Can you maintain uniform naming here KMCODE5SUN should be KM_CODE5UN?
ok, I can fix this.
Regards Holger
Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm).
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 22 +++++++++++----------- 1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index a062333..4a6bff1 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -365,13 +365,13 @@ void dram_init_banksize(void)
#if (defined(CONFIG_KM_PIGGY4_88E6061))
-#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1)
/* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -383,15 +383,15 @@ void reset_phy(void) return;
/* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n");
/* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n");
/* reset the phy */
This can be used if we do not want to use an EEPROM for the configuration.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/common/common.h | 7 -- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++ 3 files changed, 258 insertions(+), 17 deletions(-) create mode 100644 board/keymile/km_arm/managed_switch.h
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index c58e565..e9abfcd 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -125,13 +125,6 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void);
- -int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, - u8 reg, u16 data); -int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, - u8 reg, u16 *data); - - int trigger_fpga_config(void); int wait_for_fpga_config(void); int fpga_reset(void); diff --git a/board/keymile/km_arm/managed_switch.c b/board/keymile/km_arm/managed_switch.c index 482c18d..3b022cd 100644 --- a/board/keymile/km_arm/managed_switch.c +++ b/board/keymile/km_arm/managed_switch.c @@ -25,15 +25,43 @@ #include <miiphy.h> #include <asm/errno.h>
-#define SMI_HDR ((0x8 | 0x1) << 12) -#define SMI_BUSY_MASK (0x8000) -#define SMIRD_OP (0x2 << 10) -#define SMIWR_OP (0x1 << 10) -#define SMI_MASK 0x1f -#define PORT_SHIFT 5 +#include "managed_switch.h"
-#define COMMAND_REG 0 -#define DATA_REG 1 +#if defined(CONFIG_KM_NUSA) +struct switch_reg sw_conf[] = { + /* port 0, PIGY4, autoneg */ + { PORT(0), PORT_PHY, NO_SPEED_FOR }, + { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | + FULL_DUPLEX }, + { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, + /* port 1, unused */ + { PORT(1), PORT_CTRL, PORT_DIS }, + { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 2, unused */ + { PORT(2), PORT_CTRL, PORT_DIS }, + { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 3, unused */ + { PORT(3), PORT_CTRL, PORT_DIS }, + { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 4, ICNEV, SerDes, SGMII */ + { PORT(4), PORT_STATUS, NO_PHY_DETECT }, + { PORT(4), PORT_PHY, SPEED_1000_FOR }, + { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 5, CPU_RGMII */ + { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | + FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | + FULL_DPX_FOR | SPEED_1000_FOR }, + { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* port 6, unused, this port has no phy */ + { PORT(6), PORT_CTRL, PORT_DIS }, +}; +#endif
static int ext_switch_wait_rdy(const char *devname, u8 phy_addr) { @@ -59,7 +87,7 @@ static int ext_switch_wait_rdy(const char *devname, u8 phy_addr) return 0; }
-int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, +static int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, u8 reg, u16 *data) { int ret; @@ -85,7 +113,7 @@ int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port, return ret; }
-int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, +static int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, u8 reg, u16 data) { int ret; @@ -114,6 +142,127 @@ int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port, return 0; }
+static int ppu_enable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg |= PPU_ENABLE; + + ret = ext_switch_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc000) == 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +static int ppu_disable(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg &= ~PPU_ENABLE; + + ret = ext_switch_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc000) != 0xc000) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + +int ext_switch_program(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + + /* first we need to disable the PPU */ + ret = ppu_disable(devname, phy_addr); + if (ret) { + printf("%s: Error disabling PPU\n", __func__); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(sw_conf); i++) { + ret = ext_switch_reg_write(devname, phy_addr, sw_conf[i].port, + sw_conf[i].reg, sw_conf[i].value); + if (ret) { + printf("%s: Error configuring switch\n", __func__); + ppu_enable(devname, phy_addr); + return ret; + } + } + + /* re-enable the PPU */ + ret = ppu_enable(devname, phy_addr); + if (ret) { + printf("%s: Error enabling PPU\n", __func__); + return ret; + } + + return 0; +} + +int ext_switch_reset(const char *devname, u8 phy_addr) +{ + int i, ret = 0; + u16 reg; + + ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®); + if (ret) { + printf("%s: Error reading global ctrl reg\n", __func__); + return ret; + } + + reg = SW_RESET | PPU_ENABLE | 0x0400; + + ret = ext_switch_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg); + if (ret) { + printf("%s: Error writing global ctrl reg\n", __func__); + return ret; + } + + for (i = 0; i < 1000; i++) { + ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS, + ®); + if ((reg & 0xc800) != 0xc800) + return 0; + udelay(1000); + } + + return -ETIMEDOUT; +} + int do_sw_reg_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *name = "egiga0"; diff --git a/board/keymile/km_arm/managed_switch.h b/board/keymile/km_arm/managed_switch.h new file mode 100644 index 0000000..c0dcf82 --- /dev/null +++ b/board/keymile/km_arm/managed_switch.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MANAGED_SWITCH_H +#define __MANAGED_SWITCH_H + +#include <common.h> + +#define SMI_HDR ((0x8 | 0x1) << 12) +#define SMI_BUSY_MASK (0x8000) +#define SMIRD_OP (0x2 << 10) +#define SMIWR_OP (0x1 << 10) +#define SMI_MASK 0x1f +#define PORT_SHIFT 5 + +#define COMMAND_REG 0 +#define DATA_REG 1 + +/* global registers */ +#define GLOBAL 0x1b + +#define GLOBAL_STATUS 0x00 +#define PPU_STATE 0x8000 + +#define GLOBAL_CTRL 0x04 +#define SW_RESET 0x8000 +#define PPU_ENABLE 0x4000 + +/* PHY registers */ +#define PHY(itf) (itf) + +#define PHY_CTRL 0x00 +#define PHY_100_MBPS 0x2000 +#define AUTONEG_EN 0x1000 +#define AUTONEG_RST 0x0200 +#define FULL_DUPLEX 0x0100 +#define PHY_PWR_DOWN 0x0800 + +#define PHY_STATUS 0x01 + +#define PHY_SPEC_CTRL 0x10 +#define SPEC_PWR_DOWN 0x0004 +#define AUTO_MDIX_EN 0x0060 + +/* PORT or MAC registers */ +#define PORT(itf) (itf+0x10) + +#define PORT_STATUS 0x00 +#define NO_PHY_DETECT 0x0000 + +#define PORT_PHY 0x01 +#define RX_RGMII_TIM 0x8000 +#define TX_RGMII_TIM 0x4000 +#define FLOW_CTRL_EN 0x0080 +#define FLOW_CTRL_FOR 0x0040 +#define LINK_VAL 0x0020 +#define LINK_FOR 0x0010 +#define FULL_DPX 0x0008 +#define FULL_DPX_FOR 0x0004 +#define NO_SPEED_FOR 0x0003 +#define SPEED_1000_FOR 0x0002 +#define SPEED_100_FOR 0x0001 +#define SPEED_10_FOR 0x0000 + +#define PORT_CTRL 0x04 +#define FORWARDING 0x0003 +#define EGRS_FLD_ALL 0x000c +#define PORT_DIS 0x0000 + +struct switch_reg { + u8 port; + u8 reg; + u16 value; +}; + +int ext_switch_reset(const char *devname, u8 phy_addr); +int ext_switch_program(const char *devname, u8 phy_addr); + +#endif
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Valentin Longchamp Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: [U-Boot] [PATCH 12/20] arm/km: add support for external switch configuration
This can be used if we do not want to use an EEPROM for the configuration.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com
board/keymile/common/common.h | 7 -- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++
What is managed switch? Which chip it supports? Why it is sitting here and not in generic folder?
Regards.. Prafulla . . .
Hi Prafulla,
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Valentin Longchamp Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: [U-Boot] [PATCH 12/20] arm/km: add support for external switch configuration
This can be used if we do not want to use an EEPROM for the configuration.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com
board/keymile/common/common.h | 7 -- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++
What is managed switch? Which chip it supports? Why it is sitting here and not in generic folder?
In this case, the switch is a Marvell 88E52xxx (don't remember the exact model) that is connected to the GE port of the Kirkwood and that gets configured by the Kirkwood through a MDIO link, using indirect addressing.
We do not have the pretention to write a generic driver for such switches/addressing, but we need this functionnality on some boards, that's why we have kept it in our own folder and not in a generic driver folder.
I will add the above precisions to the commit message for an optional v3 of the "updates for the Keymile Marvell boards" series so that this is more clear.
Valentin
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 21 June 2012 18:40 To: Prafulla Wadaskar Cc: prafulla@mavell.com; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 12/20] arm/km: add support for external switchconfiguration
Hi Prafulla,
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Valentin Longchamp Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: [U-Boot] [PATCH 12/20] arm/km: add support for external switch configuration
This can be used if we do not want to use an EEPROM for the configuration.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com
board/keymile/common/common.h | 7 -- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++
What is managed switch? Which chip it supports? Why it is sitting
here and not in generic folder?
In this case, the switch is a Marvell 88E52xxx (don't remember the exact model) that is connected to the GE port of the Kirkwood and that gets configured by the Kirkwood through a MDIO link, using indirect addressing.
We do not have the pretention to write a generic driver for such switches/addressing, but we need this functionnality on some boards, that's why we have kept it in our own folder and not in a generic driver folder.
I will add the above precisions to the commit message for an optional v3 of the "updates for the Keymile Marvell boards" series so that this is more clear.
Dear Valentin We must keep develop it as generic driver.
Regards... Prafulla . . .
Hello Prafulla,
On 07/03/2012 10:17 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 21 June 2012 18:40 To: Prafulla Wadaskar Cc: prafulla@mavell.com; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 12/20] arm/km: add support for external switchconfiguration
Hi Prafulla,
On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Valentin Longchamp Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de Subject: [U-Boot] [PATCH 12/20] arm/km: add support for external switch configuration
This can be used if we do not want to use an EEPROM for the configuration.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com
board/keymile/common/common.h | 7 -- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++
What is managed switch? Which chip it supports? Why it is sitting
here and not in generic folder?
In this case, the switch is a Marvell 88E52xxx (don't remember the exact model) that is connected to the GE port of the Kirkwood and that gets configured by the Kirkwood through a MDIO link, using indirect addressing.
We do not have the pretention to write a generic driver for such switches/addressing, but we need this functionnality on some boards, that's why we have kept it in our own folder and not in a generic driver folder.
I will add the above precisions to the commit message for an optional v3 of the "updates for the Keymile Marvell boards" series so that this is more clear.
Dear Valentin We must keep develop it as generic driver.
Regards... Prafulla . . .
Sure it would be great if we had the time and resources to contribute a generic driver for these switches. Unfortunately it is not the case and we have only developed a simple driver with limited features that suits our current needs.
Since we know it's very limited, we have intentionally chosen to put in in our board/keymile directory so that it's obvious that it is (currently) not intended to be used nor was it tested on other boards or with other switches.
The question now is: does u-boot allow some boards (or family of boards) to integrate some board codes or drivers ? It was until now our understanding that u-boot allows this. This code definitely fits into this category.
As for the generic driver, if someone contributes one (the current driver can be used as a basis), we will be very happy to drop this code and use the generic driver.
Valentin
Hi Valentin and Prafulla,
[...]
Dear Valentin We must keep develop it as generic driver.
Regards... Prafulla . . .
Sure it would be great if we had the time and resources to contribute a generic driver for these switches. Unfortunately it is not the case and we have only developed a simple driver with limited features that suits our current needs.
Since we know it's very limited, we have intentionally chosen to put in in our board/keymile directory so that it's obvious that it is (currently) not intended to be used nor was it tested on other boards or with other switches.
Personally I welcome such a driver submission to mainline as it can be a starting point for someone else later.
The question now is: does u-boot allow some boards (or family of boards) to integrate some board codes or drivers ? It was until now our understanding that u-boot allows this. This code definitely fits into this category.
This is also my understanding and actually our source code has lots of them and many people are thankful to find such code (if they are able to find it ;)
As for the generic driver, if someone contributes one (the current driver can be used as a basis), we will be very happy to drop this code and use the generic driver.
Actually I would go even further and say that a generic driver can only be started when there are at least two or more users of the code. One should probably think about not making too many short-sighted assumptions when working on a driver but to think that one could develop a generic driver from one device only would be foolish.
So Prafulla, can you please reconsider to add the driver?
Thanks Detlev
-----Original Message----- From: Detlev Zundel [mailto:dzu@denx.de] Sent: 04 July 2012 13:38 To: Valentin Longchamp Cc: Prafulla Wadaskar; u-boot@lists.denx.de; holger.brunck@keymile.com Subject: Re: [U-Boot] [PATCH 12/20] arm/km: add support for external switchconfiguration
Hi Valentin and Prafulla,
[...]
Dear Valentin We must keep develop it as generic driver.
Regards... Prafulla . . .
Sure it would be great if we had the time and resources to
contribute a generic
driver for these switches. Unfortunately it is not the case and we
have only
developed a simple driver with limited features that suits our
current needs.
Since we know it's very limited, we have intentionally chosen to put
in in our
board/keymile directory so that it's obvious that it is (currently)
not intended
to be used nor was it tested on other boards or with other switches.
Personally I welcome such a driver submission to mainline as it can be a starting point for someone else later.
The question now is: does u-boot allow some boards (or family of
boards) to
integrate some board codes or drivers ? It was until now our
understanding that
u-boot allows this. This code definitely fits into this category.
This is also my understanding and actually our source code has lots of them and many people are thankful to find such code (if they are able to find it ;)
As for the generic driver, if someone contributes one (the current
driver can be
used as a basis), we will be very happy to drop this code and use
the generic
driver.
Actually I would go even further and say that a generic driver can only be started when there are at least two or more users of the code. One should probably think about not making too many short-sighted assumptions when working on a driver but to think that one could develop a generic driver from one device only would be foolish.
So Prafulla, can you please reconsider to add the driver?
Hi Detlev Clear NAK for this patch
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_ATHEROS" include/configs/* include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS 1 [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_BROADCOM" include/configs/* include/configs/microblaze-generic.h:347:# define CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
Regards... Prafulla . . .
Hi,
On 07/04/2012 11:20 AM, Prafulla Wadaskar wrote:
Sure it would be great if we had the time and resources to
contribute a generic
driver for these switches. Unfortunately it is not the case and we
have only
developed a simple driver with limited features that suits our
current needs.
Since we know it's very limited, we have intentionally chosen to put
in in our
board/keymile directory so that it's obvious that it is (currently)
not intended
to be used nor was it tested on other boards or with other switches.
Personally I welcome such a driver submission to mainline as it can be a starting point for someone else later.
The question now is: does u-boot allow some boards (or family of
boards) to
integrate some board codes or drivers ? It was until now our
understanding that
u-boot allows this. This code definitely fits into this category.
This is also my understanding and actually our source code has lots of them and many people are thankful to find such code (if they are able to find it ;)
As for the generic driver, if someone contributes one (the current
driver can be
used as a basis), we will be very happy to drop this code and use
the generic
driver.
Actually I would go even further and say that a generic driver can only be started when there are at least two or more users of the code. One should probably think about not making too many short-sighted assumptions when working on a driver but to think that one could develop a generic driver from one device only would be foolish.
So Prafulla, can you please reconsider to add the driver?
Hi Detlev Clear NAK for this patch
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_ATHEROS" include/configs/* include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS 1 [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_BROADCOM" include/configs/* include/configs/microblaze-generic.h:347:# define CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
yes there are maybe drivers which proof your concept, but there are many others in the board related code which do the opposite.
But I think this topic should be discussed not in the context of this patch. It's a general question. I 100% agree with Detlev's explanation. If a new very limited HW driver is added to the repo I see good reasons to keep it in the folder for the board. If a second user comes up and wants to enhance the driver for his needs he can still move driver then. But if no other user for this driver is there and maybe in the future the board needs to be removed because it's broken it's much easier to remove _all_ related code when it's located in one directory. If the code is spread over several directories it's much harder to track.
Regards Holger
Dear Holger,
In message 4FFAC8C9.1020603@keymile.com you wrote:
Anyways peripheral driver should go in drivers/
yes there are maybe drivers which proof your concept, but there are many others in the board related code which do the opposite.
Yes, but bad examples are not a good reason to repeat mistakes either.
But I think this topic should be discussed not in the context of this patch. It's a general question. I 100% agree with Detlev's explanation. If a new very limited HW driver is added to the repo I see good reasons to keep it in the folder for the board. If a second user comes up and wants to enhance the driver for his needs he can still move driver then. But if no other user for this driver is there and maybe in the future the board needs to be removed because it's broken it's much easier to remove _all_ related code when it's located in one directory. If the code is spread over several directories it's much harder to track.
Sorry, but I disagree. How many board directories are there in U-Boot? Several hundreds... How many board directories did you check to make sure none of them contains any driver that is similar to what you implement here?
If we place the driver in your board diretory, the chances are huge it will simply sit there and rot, and the next one who needs something similar will reinvent the wheel because he did not find your copy.
I agree that even very simple and uncomplete implementations can co in if the fulfil some purpose, and can form a basis for future extensions.
To make sure everybody sees such code, we should really add it to the standard locations.
Thanks.
Best regards,
Wolfgang Denk
Hi Wolfgang,
[...]
Sorry, but I disagree. How many board directories are there in U-Boot? Several hundreds... How many board directories did you check to make sure none of them contains any driver that is similar to what you implement here?
If we place the driver in your board diretory, the chances are huge it will simply sit there and rot, and the next one who needs something similar will reinvent the wheel because he did not find your copy.
I agree that even very simple and uncomplete implementations can co in if the fulfil some purpose, and can form a basis for future extensions.
To make sure everybody sees such code, we should really add it to the standard locations.
According to the current situation, we have the choice of getting good code into a board directory or no code at all because Prafulla doesn't accept the code in its current incarnation into a general place. I don't need a crystal ball to see that the project will loose code this way. I'm sorry that the project rejects working code and I re-ask Prafulla to reconsider his NAK which has impact on the whole project.
Cheers Detlev
Dear Detlev,
In message m27gudp08t.fsf@lamuella.denx.de you wrote:
I agree that even very simple and uncomplete implementations can co in
should read: ...can go in...
if the fulfil some purpose, and can form a basis for future extensions.
To make sure everybody sees such code, we should really add it to the standard locations.
According to the current situation, we have the choice of getting good code into a board directory or no code at all because Prafulla doesn't accept the code in its current incarnation into a general place. I
I just tried to explain that my wish is that 1) this code can go in, even if not perfectly universal yet, and 2) that it should go into the standard location for such drivers.
don't need a crystal ball to see that the project will loose code this way. I'm sorry that the project rejects working code and I re-ask Prafulla to reconsider his NAK which has impact on the whole project.
I don't see why you are taking about rejecting code here. Didn't I make clear that I vote for adding this code?
I hope Prafulla finds this recommendation acceptable (especially after I added him to Cc: so he actually gets aware of this discussion).
Best regards,
Wolfgang Denk
Hi Wolfgang,
[...]
If we place the driver in your board diretory, the chances are huge it will simply sit there and rot, and the next one who needs something similar will reinvent the wheel because he did not find your copy.
I agree that even very simple and uncomplete implementations can co in if the fulfil some purpose, and can form a basis for future extensions.
I just read through our documentation on the Wiki and found nothing relavant to such a topic. If we make this a requirement, we should add it so people know about it beforehand.
How about amending the U-Boot design principles with
11. Keep It Generic
- Generic code shall be added as high as possible to the U-Boot abstraction hierarchy and only as a last resort into board directories. This entails that peripheral drivers should be put below "drivers" even if they start out supporting only one specific configuration. Note that it is not a requirement for such a first instance to be generic as genericity generally cannot be extrapolated from a single data point.
How does that sound?
Cheers Detlev
Hi Detlev,
On 07/09/2012 03:06 PM, Detlev Zundel wrote:
If we place the driver in your board diretory, the chances are huge it will simply sit there and rot, and the next one who needs something similar will reinvent the wheel because he did not find your copy.
I agree that even very simple and uncomplete implementations can co in if the fulfil some purpose, and can form a basis for future extensions.
I just read through our documentation on the Wiki and found nothing relavant to such a topic. If we make this a requirement, we should add it so people know about it beforehand.
How about amending the U-Boot design principles with
- Keep It Generic
- Generic code shall be added as high as possible to the U-Boot abstraction hierarchy and only as a last resort into board directories. This entails that peripheral drivers should be put below "drivers" even if they start out supporting only one specific configuration. Note that it is not a requirement for such a first instance to be generic as genericity generally cannot be extrapolated from a single data point.
How does that sound?
shouldn't be there an exception for strictly board specific peripheral drivers like an custom-made FPGA?
Regards Holger
Dear Holger,
In message 4FFAEE4F.3090600@keymile.com you wrote:
shouldn't be there an exception for strictly board specific peripheral drivers like an custom-made FPGA?
I see two situations:
1) We are talking about code to load a bitstream into the FPGA, i. e. to "program it". Such code should always be generic enough to put it under drivers/fpga/ (if the existing code there does not already cover the task).
2) We are talking about driver code for some preipheral implemented in the FPGA. In many cases we find these peripherals to be pretty generic (say, UARTs, GPIOs, network interfaces, etc.). In such cases there is no doubt that driver code should go to drivers/ . ONly in case you have areally, really special feature implemented that you need supported in U-Boot. OK, then such drivers are probably better kept in your board directory.
Note that there will always be cases where hindsight will show that the initial location was not perfect. That is perfectly normal ;-)
Best regards,
Wolfgang Denk
Dear Detlev,
In message m2zk79nkx6.fsf@lamuella.denx.de you wrote:
I just read through our documentation on the Wiki and found nothing relavant to such a topic. If we make this a requirement, we should add it so people know about it beforehand.
You know all too well that our wiki suffers from a mismatch of what people expect to it and what htey contribute to it.
How about amending the U-Boot design principles with
Go for it - it's a wiki.
Best regards,
Wolfgang Denk
Hi,
How about amending the U-Boot design principles with
Go for it - it's a wiki.
Thinking about it, I turned it not into a rule, but into a Lemma from the 10 rules:
Lemmas from the golden rules
1. Generic Code is Good Code
New code shall be as generic as possible and added to the U-Boot abstraction hierarchy as high as possible. As few code as possible shall be added in board directories as people usually do not expect re-usable code there. Thus peripheral drivers should be put below "drivers" even if they start out supporting only one specific configuration. Note that it is not a requirement for such a first instance to be generic as genericity generally cannot be extrapolated from a single data point.
Feel free to amend / modify that.
Cheers Detlev
[1] http://www.denx.de/wiki/rdiff/U-Boot/DesignPrinciples?rev1=1.14&rev2=1.1...
PS: Ok, actually I didn't want to ruin the magic 10 ;)
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 09 July 2012 17:34 To: Prafulla Wadaskar Cc: Detlev Zundel; Valentin Longchamp; u-boot@lists.denx.de Subject: Re: [PATCH 12/20] arm/km: add support for external switchconfiguration
...snip...
Hi Detlev Clear NAK for this patch
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim
drivers/net/phy/Makefile
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn
"CONFIG_PHY_ATHEROS" include/configs/*
include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS
1
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim
drivers/net/phy/Makefile
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn
"CONFIG_PHY_BROADCOM" include/configs/*
include/configs/microblaze-generic.h:347:# define
CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
yes there are maybe drivers which proof your concept, but there are many others in the board related code which do the opposite.
But I think this topic should be discussed not in the context of this patch. It's a general question. I 100% agree with Detlev's explanation. If a new very limited HW driver is added to the repo I see good reasons to keep it in the folder for the board. If a second user comes up and wants to enhance the driver for his needs he can still move driver then. But if no other user for this driver is there and maybe in the future the board needs to be removed because it's broken it's much easier to remove _all_ related code when it's located in one directory. If the code is spread over several directories it's much harder to track.
Dear Holger, The peripheral (switch/PHY) is being considered to be supported as a driver is interfaced through standard interface and can be used by any other CPU/architecture/SoC on any other board.
So I think there is no reason to keep it in board specific folder. Someone may correct me if I am wrong.
Copying Joe (net custodian)
Regards... Prafulla . . .
Hi Prafulla,
On Mon, Jul 9, 2012 at 3:42 PM, Prafulla Wadaskar prafulla@marvell.com wrote:
-----Original Message----- From: Holger Brunck [mailto:holger.brunck@keymile.com] Sent: 09 July 2012 17:34 To: Prafulla Wadaskar Cc: Detlev Zundel; Valentin Longchamp; u-boot@lists.denx.de Subject: Re: [PATCH 12/20] arm/km: add support for external switchconfiguration
...snip...
Hi Detlev Clear NAK for this patch
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim
drivers/net/phy/Makefile
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn
"CONFIG_PHY_ATHEROS" include/configs/*
include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS
1
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim
drivers/net/phy/Makefile
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn
"CONFIG_PHY_BROADCOM" include/configs/*
include/configs/microblaze-generic.h:347:# define
CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
yes there are maybe drivers which proof your concept, but there are many others in the board related code which do the opposite.
But I think this topic should be discussed not in the context of this patch. It's a general question. I 100% agree with Detlev's explanation. If a new very limited HW driver is added to the repo I see good reasons to keep it in the folder for the board. If a second user comes up and wants to enhance the driver for his needs he can still move driver then. But if no other user for this driver is there and maybe in the future the board needs to be removed because it's broken it's much easier to remove _all_ related code when it's located in one directory. If the code is spread over several directories it's much harder to track.
Dear Holger, The peripheral (switch/PHY) is being considered to be supported as a driver is interfaced through standard interface and can be used by any other CPU/architecture/SoC on any other board.
So I think there is no reason to keep it in board specific folder. Someone may correct me if I am wrong.
I agree. It belongs in drivers/net/phy/.
Thanks, -Joe
Hi Prafulla,
[...]
Hi Detlev Clear NAK for this patch
Do you mean clear NAK for "the patch" or "for the location of the files"?
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_ATHEROS" include/configs/* include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS 1 [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_BROADCOM" include/configs/* include/configs/microblaze-generic.h:347:# define CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
Ok, so if the files are moved to drivers/net/phy, then you will ACK the patch? If this is the case, then Valentin please move the files and be done with it.
Cheers Detlev
Hi Detlev,
On 07/09/2012 04:31 PM, Detlev Zundel wrote:
Hi Prafulla,
[...]
Hi Detlev Clear NAK for this patch
Do you mean clear NAK for "the patch" or "for the location of the files"?
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_ATHEROS" include/configs/* include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS 1 [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_BROADCOM" include/configs/* include/configs/microblaze-generic.h:347:# define CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
Ok, so if the files are moved to drivers/net/phy, then you will ACK the patch? If this is the case, then Valentin please move the files and be done with it.
Already working on it ;)
Valentin
-----Original Message----- From: Detlev Zundel [mailto:dzu@denx.de] Sent: 09 July 2012 20:02 To: Prafulla Wadaskar Cc: Valentin Longchamp; u-boot@lists.denx.de; holger.brunck@keymile.com Subject: Re: [U-Boot] [PATCH 12/20] arm/km: add support for external switchconfiguration
Hi Prafulla,
[...]
Hi Detlev Clear NAK for this patch
Do you mean clear NAK for "the patch" or "for the location of the files"?
Dear Detlev
Location, I have not gone through the rest of the patch.
Let's put it in drivers/net/phy/ FYI: there are several drivers used by just one board, [prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_ATHEROS" include/configs/* include/configs/microblaze-generic.h:346:# define CONFIG_PHY_ATHEROS
1
[prafulla@pe-dt061 u-boot-marvell.git (master)]$ vim drivers/net/phy/Makefile [prafulla@pe-dt061 u-boot-marvell.git (master)]$ grep -Irn "CONFIG_PHY_BROADCOM" include/configs/* include/configs/microblaze-generic.h:347:# define
CONFIG_PHY_BROADCOM 1
Anyways peripheral driver should go in drivers/
Ok, so if the files are moved to drivers/net/phy, then you will ACK the patch? If this is the case, then Valentin please move the files and be done with it.
Thanks... Regards... Prafulla . . .
The configuration EEPROM should be removed for P1B.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/km_arm/km_arm.c | 11 +++++------ board/keymile/km_arm/managed_switch.c | 3 ++- board/keymile/km_arm/managed_switch.h | 7 +++++++ 3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 4a6bff1..edaadb9 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -43,6 +43,7 @@ #include <asm/arch/mpp.h>
#include "../common/common.h" +#include "managed_switch.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -407,13 +408,11 @@ void reset_phy(void) if (miiphy_set_current_dev(name)) return;
- /* enable autoneg on port 0 phy */ - ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300); +#if defined(CONFIG_KM_NUSA) + ext_switch_program(name, CONFIG_KM_MANAGED_SW_ADDR); +#endif
- /* egress broadcast franes on all macs, with forwarding */ - ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f); - ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f); - ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f); + ext_switch_reset(name, CONFIG_KM_MANAGED_SW_ADDR); } #endif
diff --git a/board/keymile/km_arm/managed_switch.c b/board/keymile/km_arm/managed_switch.c index 3b022cd..a776f1d 100644 --- a/board/keymile/km_arm/managed_switch.c +++ b/board/keymile/km_arm/managed_switch.c @@ -32,9 +32,10 @@ struct switch_reg sw_conf[] = { /* port 0, PIGY4, autoneg */ { PORT(0), PORT_PHY, NO_SPEED_FOR }, { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(0), PHY_1000_CTRL, NO_ADV }, + { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | FULL_DUPLEX }, - { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, /* port 1, unused */ { PORT(1), PORT_CTRL, PORT_DIS }, { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, diff --git a/board/keymile/km_arm/managed_switch.h b/board/keymile/km_arm/managed_switch.h index c0dcf82..d5b938a 100644 --- a/board/keymile/km_arm/managed_switch.h +++ b/board/keymile/km_arm/managed_switch.h @@ -51,6 +51,7 @@
#define PHY_CTRL 0x00 #define PHY_100_MBPS 0x2000 +#define PHY_1_GBPS 0x0040 #define AUTONEG_EN 0x1000 #define AUTONEG_RST 0x0200 #define FULL_DUPLEX 0x0100 @@ -62,6 +63,12 @@ #define SPEC_PWR_DOWN 0x0004 #define AUTO_MDIX_EN 0x0060
+#define PHY_1000_CTRL 0x9 + +#define NO_ADV 0x0000 +#define ADV_1000_FDPX 0x0200 +#define ADV_1000_HDPX 0x0100 + /* PORT or MAC registers */ #define PORT(itf) (itf+0x10)
In order to be able to perform board resets without interrupting the traffic, the configuration of an already properly configured FPGA is skipped.
This is because some PCIe FPGAs embed some other function that must continue to work over reset.
It is then the responsibility of the application to trigger a reconfiguration when needed. This is done by lowering the FPGA_INIT_B pin for delaying the configuration to u-boot @ next reboot, and then lower the FPGA_PROGRAM_B signal.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/km_arm/fpga_config.c | 41 +++++++++++++++++++++++++++++++++++- 1 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 4356b9a..8ac6393 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -96,12 +96,43 @@ static int boco_set_bits(u8 reg, u8 flags) #define SPI_REG 0x06 #define CFG_EEPROM 0x02 #define FPGA_PROG 0x04 +#define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20
+static int fpga_done() +{ + int ret = 0; + u8 regval; + + /* this is only supported with the boco2 design */ + if (!check_boco2()) + return 0; + + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, SPI_REG); + return 0; + } + + return regval & FPGA_DONE ? 1 : 0; +} + +int skip; + int trigger_fpga_config(void) { int ret = 0;
+ /* if the FPGA is already configured, we do not want to + * reconfigure it */ + skip = 0; + if (fpga_done()) { + printf("PCIe FPGA config: skipped\n"); + skip = 1; + return 0; + } + if (check_boco2()) { /* we have a BOCO2, this has to be triggered here */
@@ -111,7 +142,7 @@ int trigger_fpga_config(void) return ret;
/* trigger the config start */ - ret = boco_clear_bits(SPI_REG, FPGA_PROG); + ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); if (ret) return ret;
@@ -123,6 +154,11 @@ int trigger_fpga_config(void) if (ret) return ret;
+ /* finally, raise INIT_B to remove the config delay */ + ret = boco_set_bits(SPI_REG, FPGA_INIT_B); + if (ret) + return ret; + } else { /* we do it the old way, with the gpio pin */ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); @@ -141,6 +177,9 @@ int wait_for_fpga_config(void) u8 spictrl; u32 timeout = 20000;
+ if (skip) + return 0; + if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0;
The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part.
When the FPGA is not reconfigured, we only reset the PCIe part.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/km_arm/fpga_config.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 8ac6393..fcc5fe6 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags) #define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20
-static int fpga_done() +static int fpga_done(void) { int ret = 0; u8 regval; @@ -206,25 +206,30 @@ int wait_for_fpga_config(void) }
#define PRST1 0x4 -#define BRIDGE_RST 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04
int fpga_reset(void) { int ret = 0; + u8 resets;
if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0; }
- ret = boco_clear_bits(PRST1, BRIDGE_RST); + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); if (ret) return ret;
/* small delay for the pulse */ udelay(10);
- ret = boco_set_bits(PRST1, BRIDGE_RST); + ret = boco_set_bits(PRST1, resets); if (ret) return ret;
From: Thomas Herzmann thomas.herzmann@keymile.com
Add a function to read the dip_switch on kmcoge5un. If the switch is set the actual_bank is set to 0 and this SW is booted.
Signed-off-by: Thomas Herzmann thomas.herzmann@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com --- board/keymile/km_arm/km_arm.c | 14 +++++++++++++- include/configs/km_kirkwood.h | 3 --- 2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index edaadb9..d6da632 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -286,12 +286,24 @@ int board_init(void)
int board_late_init(void) { +#if defined(CONFIG_KMCOGE5UN) +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); + + /* if pin 1 do full erase */ + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } +#endif + #if defined(CONFIG_KM_FPGA_CONFIG) wait_for_fpga_config(); fpga_reset(); toggle_eeprom_spi_bus(); #endif - return 0; }
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 549122b..9ecfcf4 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -184,8 +184,5 @@ #undef CONFIG_KIRKWOOD_PCIE_INIT #endif
-#ifndef CONFIG_KM_FPGA_CONFIG -#undef BOARD_LATE_INIT -#endif
#endif /* _CONFIG_KM_KIRKWOOD */
From: Thomas Herzmann thomas.herzmann@keymile.com
On kmcoge5un unfortunately the HW wiring is differently to other km arm boards.
Signed-off-by: Thomas Herzmann thomas.herzmann@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com --- board/keymile/km_arm/km_arm.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index d6da632..8e4c382 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -533,7 +533,11 @@ int get_scl(void)
int post_hotkeys_pressed(void) { +#if defined(CONFIG_KMCOGE5UN) + return kw_gpio_get_value(KM_POST_EN_L); +#else return !kw_gpio_get_value(KM_POST_EN_L); +#endif }
ulong post_word_load(void)
They are needed on all km_arm boards where we have the environement variables in the NOR Flash. First boards using this feature are kmcoge5un and kmnusa.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Holger Brunck holger.brunck@keymile.com cc: Gerlando Falauto gerlando.falauto@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 26 ++++++++------------------ 1 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 8e4c382..a71bd2f 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -36,6 +36,7 @@ #include <nand.h> #include <netdev.h> #include <miiphy.h> +#include <spi.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/errno.h> @@ -307,29 +308,18 @@ int board_late_init(void) return 0; }
-int km_hw_spi_bus_claim(int on) +int board_spi_claim_bus(struct spi_slave *slave) { - int gpio_value = !on; - - if (on) { - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - } else { - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - } - - /* Multi-Purpose Pins Functionality configuration */ - kirkwood_mpp_conf(kwmpp_config, NULL); - kw_gpio_set_value(KM_FLASH_GPIO_PIN, gpio_value); + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
return 0; }
+void board_spi_release_bus(struct spi_slave *slave) +{ + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); +} + #if defined(CONFIG_CMD_SF) int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
From: Holger Brunck holger.brunck@keymile.com
Now we toggle between SPI and NAND flash automatically if we claim the SPI bus. So we can get rid of this command.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 26 -------------------------- include/configs/km/km_arm.h | 5 ++--- 2 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index a71bd2f..2581d61 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -320,32 +320,6 @@ void board_spi_release_bus(struct spi_slave *slave) kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); }
-#if defined(CONFIG_CMD_SF) -int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "off") == 0)) { - printf("SPI FLASH disabled, NAND enabled\n"); - km_hw_spi_bus_claim(0); - } else if ((strcmp(argv[1], "on") == 0)) { - printf("SPI FLASH enabled, NAND disabled\n"); - km_hw_spi_bus_claim(1); - } else { - return cmd_usage(cmdtp); - } - - return 0; -} - -U_BOOT_CMD( - spitoggle, 2, 0, do_spi_toggle, - "En-/disable SPI FLASH access", - "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" - ); -#endif - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 66f382b..5fbb590 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -257,9 +257,8 @@ int get_scl(void);
#define CONFIG_KM_UPDATE_UBOOT \ "update=" \ - "spi on;sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};" \ - "spi off\0" + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0"
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_KM_NEW_ENV \
These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u-boot binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com --- board/keymile/km_arm/km_arm.c | 34 ++++++++++++++++++++++++---------- include/configs/km/km_arm.h | 1 + 2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2581d61..c13be71 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -248,9 +248,27 @@ int misc_init_r(void)
int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp;
+ /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
/* * The KM_FLASH_GPIO_PIN switches between using a @@ -259,24 +277,20 @@ int board_early_init_f(void) */ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); + #if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ + /* reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
#if defined(CONFIG_KM_FPGA_CONFIG) trigger_fpga_config(); diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 5fbb590..8a6b345 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -192,6 +192,7 @@ int get_sda(void); int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 #define KM_KIRKWOOD_ENV_WP 38
#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Prafulla Wadaskar Subject: [PATCH 20/20] arm/km: remove calls to kw_gpio_* in board_early_init_f
These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u- boot binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 34 ++++++++++++++++++++++++--------
include/configs/km/km_arm.h | 1 + 2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2581d61..c13be71 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -248,9 +248,27 @@ int misc_init_r(void)
int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp;
- /* set the 2 bitbang i2c pins as output gpios */
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
+}
+int board_init(void) +{
/*
* arch number of board*/gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
/*
- The KM_FLASH_GPIO_PIN switches between using a
@@ -259,24 +277,20 @@ int board_early_init_f(void) */ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
- /* init the GPIO for I2C Bitbang driver */
- /* reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to* direction output in are not necessary, they are already done in* board_early_init_f */
Comments are not as per coding standard
Regards.. Prafulla . . .
On 06/12/2012 09:58 AM, Prafulla Wadaskar wrote:
-----Original Message----- From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] Sent: 07 June 2012 15:37 To: prafulla@mavell.com Cc: Valentin Longchamp; holger.brunck@keymile.com; u- boot@lists.denx.de; Prafulla Wadaskar Subject: [PATCH 20/20] arm/km: remove calls to kw_gpio_* in board_early_init_f
These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u- boot binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com cc: Holger Brunck holger.brunck@keymile.com cc: Prafulla Wadaskar prafulla@marvell.com
board/keymile/km_arm/km_arm.c | 34 ++++++++++++++++++++++++--------
include/configs/km/km_arm.h | 1 + 2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 2581d61..c13be71 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -248,9 +248,27 @@ int misc_init_r(void)
int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp;
- /* set the 2 bitbang i2c pins as output gpios */
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
+}
+int board_init(void) +{
/*
* arch number of board*/gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
/*
- The KM_FLASH_GPIO_PIN switches between using a
@@ -259,24 +277,20 @@ int board_early_init_f(void) */ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
- /* init the GPIO for I2C Bitbang driver */
- /* reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to* direction output in are not necessary, they are already done in* board_early_init_f */Comments are not as per coding standard
Ok I'll fix this in v2.
Regards Holger
participants (6)
-
Detlev Zundel -
Holger Brunck -
Joe Hershberger -
Prafulla Wadaskar -
Valentin Longchamp -
Wolfgang Denk