[PATCH 0/4] arm: mvebu: turris_mox: Fix and enable PCIe devices
This patch series fix PCIe on Armada 3720 and enable PCIe devices (USB and NVMe) on Turris MOX.
Marek Behún (1): arm: mvebu: turris_mox: Enable NVMe support
Pali Rohár (3): arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes arm: mvebu: turris_mox: Enable CONFIG_PCI_PNP arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI
configs/turris_mox_defconfig | 3 ++- drivers/pci/pci-aardvark.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-)
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller.
This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification.
Linux has this code too.
Signed-off-by: Pali Rohár pali@kernel.org --- drivers/pci/pci-aardvark.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 8713b88461..b4e1b60240 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -42,6 +42,10 @@ #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 #define PCIE_CORE_LINK_TRAINING BIT(5) #define PCIE_CORE_ERR_CAPCTL_REG 0x118 @@ -534,6 +538,10 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | + (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE << + PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) | + (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE << + PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE; advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
Reviewed-by: Marek Behún marek.behun@nic.cz
On 05.02.21 15:32, Pali Rohár wrote:
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller.
This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification.
Linux has this code too.
Signed-off-by: Pali Rohár pali@kernel.org
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
drivers/pci/pci-aardvark.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 8713b88461..b4e1b60240 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -42,6 +42,10 @@ #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2 +#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 #define PCIE_CORE_LINK_TRAINING BIT(5) #define PCIE_CORE_ERR_CAPCTL_REG 0x118 @@ -534,6 +538,10 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
Viele Grüße, Stefan
PCIe devices do not work in U-Boot without proper initialization and configuration of PCI config space like the PCI_BASE_ADDRESS_0 register.
Signed-off-by: Pali Rohár pali@kernel.org --- configs/turris_mox_defconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index dde7437f24..329c596cea 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -64,7 +64,6 @@ CONFIG_MVNETA=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y -# CONFIG_PCI_PNP is not set CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y
Reviewed-by: Marek Behún marek.behun@nic.cz
On 05.02.21 15:32, Pali Rohár wrote:
PCIe devices do not work in U-Boot without proper initialization and configuration of PCI config space like the PCI_BASE_ADDRESS_0 register.
Signed-off-by: Pali Rohár pali@kernel.org
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
configs/turris_mox_defconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index dde7437f24..329c596cea 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -64,7 +64,6 @@ CONFIG_MVNETA=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y -# CONFIG_PCI_PNP is not set CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y
Viele Grüße, Stefan
USB devices can be connected to Turris MOX also via MOX F extension which contains VL805 PCIe based USB 3.0 controller.
Signed-off-by: Pali Rohár pali@kernel.org --- configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 329c596cea..27a5179fe5 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -77,6 +77,7 @@ CONFIG_MVEBU_A3700_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y
Reviewed-by: Marek Behún marek.behun@nic.cz
On 05.02.21 15:32, Pali Rohár wrote:
USB devices can be connected to Turris MOX also via MOX F extension which contains VL805 PCIe based USB 3.0 controller.
Signed-off-by: Pali Rohár pali@kernel.org
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 329c596cea..27a5179fe5 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -77,6 +77,7 @@ CONFIG_MVEBU_A3700_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y
Viele Grüße, Stefan
From: Marek Behún marek.behun@nic.cz
NVMe drives can be connected to Turris MOX via MOX B and MOX G extensions.
Signed-off-by: Marek Behún marek.behun@nic.cz --- configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 27a5179fe5..f938fbb475 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y
Reviewed-by: Marek Behún marek.behun@nic.cz
On 05.02.21 15:32, Pali Rohár wrote:
From: Marek Behún marek.behun@nic.cz
NVMe drives can be connected to Turris MOX via MOX B and MOX G extensions.
Signed-off-by: Marek Behún marek.behun@nic.cz
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 27a5179fe5..f938fbb475 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -61,6 +61,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y
Viele Grüße, Stefan
On 05.02.21 15:32, Pali Rohár wrote:
This patch series fix PCIe on Armada 3720 and enable PCIe devices (USB and NVMe) on Turris MOX.
Marek Behún (1): arm: mvebu: turris_mox: Enable NVMe support
Pali Rohár (3): arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes arm: mvebu: turris_mox: Enable CONFIG_PCI_PNP arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI
configs/turris_mox_defconfig | 3 ++- drivers/pci/pci-aardvark.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-)
Applied to u-boot-marvell/master
Thanks, Stefan
participants (3)
-
Marek Behun -
Pali Rohár -
Stefan Roese