[U-Boot] [PATCH 1/2] driver/ddr/fsl: Add more debug registers
From: York Sun york.sun@nxp.com
32 more debug registers are added for newer DDR controllers.
Signed-off-by: York Sun york.sun@nxp.com Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com --- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/interactive.c | 4 ++-- include/fsl_ddr_sdram.h | 2 +- include/fsl_immap.h | 3 +-- 4 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index d37e247..c2f8a8b 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -218,7 +218,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->err_disable, regs->err_disable); #endif ddr_out32(&ddr->err_int_en, regs->err_int_en); - for (i = 0; i < 32; i++) { + for (i = 0; i < 64; i++) { if (regs->debug[i]) { debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index d23e6e5..49352b3 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -670,7 +670,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
print_option_table(options, n_opts, ddr);
- for (i = 0; i < 32; i++) + for (i = 0; i < 64; i++) printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); }
@@ -771,7 +771,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, if (handle_option_table(options, n_opts, ddr, regname, value_str)) return;
- for (i = 0; i < 32; i++) { + for (i = 0; i < 64; i++) { unsigned int value = simple_strtoul(value_str, NULL, 0); sprintf(buf, "debug_%u", i + 1); if (strcmp(buf, regname) == 0) { diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 486e47e..36bd9d7 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -299,7 +299,7 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_cdr2; unsigned int err_disable; unsigned int err_int_en; - unsigned int debug[32]; + unsigned int debug[64]; } fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s { diff --git a/include/fsl_immap.h b/include/fsl_immap.h index e4addad..b1c4fe7 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -131,7 +131,6 @@ struct ccsr_ddr { u32 capture_ext_address; /* Error Extended Addr Capture */ u32 err_sbe; /* Single-Bit ECC Error Management */ u8 res_e5c[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res_f80[128]; + u32 debug[64]; /* debug_1 to debug_64 */ }; #endif /* __FSL_IMMAP_H */
From: York Sun york.sun@nxp.com
DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off.
Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled.
Signed-off-by: York Sun york.sun@nxp.com --- drivers/ddr/fsl/fsl_ddr_gen4.c | 83 ++++++++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 36 deletions(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index c2f8a8b..aaf7c02 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -238,7 +238,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511 /* Part 1 of 2 */ - /* This erraum only applies to verion 5.2.0 */ if (fsl_ddr_get_version(ctrl_num) == 0x50200) { /* Disable DRAM VRef training */ ddr_out32(&ddr->ddr_cdr2, @@ -247,13 +246,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, temp32 = ddr_in32(&ddr->debug[28]); temp32 |= DDR_TX_BD_DIS; ddr_out32(&ddr->debug[28], temp32); - /* Disable D_INIT */ - ddr_out32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); ddr_out32(&ddr->debug[25], 0x9000); + } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) { + /* Output enable forced off */ + ddr_out32(&ddr->debug[37], 1 << 31); + /* Enable Vref training */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN); + } else { + debug("Erratum A008511 doesn't apply.\n"); } #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008511) + /* Disable D_INIT */ + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009801 temp32 = ddr_in32(&ddr->debug[25]); temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; @@ -331,21 +342,21 @@ step2: #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ defined(CONFIG_SYS_FSL_ERRATUM_A009803) /* Part 2 of 2 */ - /* This erraum only applies to verion 5.2.0 */ - if (fsl_ddr_get_version(ctrl_num) == 0x50200) { - /* Wait for idle */ - timeout = 40; - while (!(ddr_in32(&ddr->debug[1]) & 0x2) && - (timeout > 0)) { - udelay(1000); - timeout--; - } - if (timeout <= 0) { - printf("Controler %d timeout, debug_2 = %x\n", - ctrl_num, ddr_in32(&ddr->debug[1])); - } + timeout = 40; + /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */ + while (!(ddr_in32(&ddr->debug[1]) & 0x2) && + (timeout > 0)) { + udelay(1000); + timeout--; + } + if (timeout <= 0) { + printf("Controler %d timeout, debug_2 = %x\n", + ctrl_num, ddr_in32(&ddr->debug[1])); + }
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511 + /* This erraum only applies to verion 5.2.0 */ + if (fsl_ddr_get_version(ctrl_num) == 0x50200) { /* The vref setting sequence is different for range 2 */ if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) vref_seq = vref_seq2; @@ -392,32 +403,32 @@ step2: printf("Controler %d timeout, debug_2 = %x\n", ctrl_num, ddr_in32(&ddr->debug[1])); } - /* Restore D_INIT */ - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + } #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803 - if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { - /* if it's RDIMM */ - if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) - continue; - set_wait_for_bits_clear(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL(i) | - 0x070000ed, - MD_CNTL_MD_EN); - udelay(1); - } + if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + /* if it's RDIMM */ + if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) + continue; + set_wait_for_bits_clear(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL(i) | + 0x070000ed, + MD_CNTL_MD_EN); + udelay(1); } - - ddr_out32(&ddr->err_disable, - regs->err_disable & ~DDR_ERR_DISABLE_APED); } -#endif + + ddr_out32(&ddr->err_disable, + regs->err_disable & ~DDR_ERR_DISABLE_APED); } #endif + /* Restore D_INIT */ + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); +#endif
total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
On 08/29/2016 02:16 AM, Shengzhou Liu wrote:
From: York Sun york.sun@nxp.com
DDR controller 5.2.1 has this erratum A008511 partially fixed. The workaround needs to be adjusted to take advantage of Vref training. This patch enables the training and force output enable to be off.
Erratum A009803 requires the controller to be idel before enabling address parity. It was combined with workaround for A008511. With new A008511 flow, this flow needs to be changed to enabling data init (D_INIT) after the address parity is enabled.
Signed-off-by: York Sun york.sun@nxp.com
Added your signed-off-by.
Applied to fsl-qoriq master. Awaiting upstream. Thanks.
York
On 08/29/2016 02:16 AM, Shengzhou Liu wrote:
From: York Sun york.sun@nxp.com
32 more debug registers are added for newer DDR controllers.
Signed-off-by: York Sun york.sun@nxp.com Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
Applied to fsl-qoriq master. Awaiting upstream.
York
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