From: Sandeep Gopalpet sandeep.kumar@freescale.com

The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions.

Signed-off-by: Sandeep Gopalpet sandeep.kumar@freescale.com --- cpu/mpc85xx/release.S | 7 +++++++ cpu/mpc85xx/start.S | 7 +++++++ include/asm-ppc/processor.h | 1 + 3 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 36ea8c3..5883ce6 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -57,6 +57,13 @@ __secondary_start_page:

#ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: mtspr SPRN_HID1,r3 #endif

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 5f63979..f746e29 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -180,6 +180,13 @@ _start_e500:

#ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: mtspr HID1,r0 #endif

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f4e7a7b..358bd7e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */