[U-Boot] [PATCH 00/12] Add SPI and QSPI boot for LS2080A
From: Yuan Yao yao.yuan@nxp.com
Yuan Yao (12): armv8: ls2080aqds: Select QSPI CLK div via SCFG configs: ls2080a_common: Remove duplicate NOR configs configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI configs: ls2080aqds: Enable QSPI flash support dm: dts: ls2080aqds: Add QSPI dts node armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot configs: ls2080a: Increase load image len in NAND boot ls2080aqds_nand_defconfig: Enable QSPI & its dependence armv8: ls2080aqds: Enable QSPI boot support ls2080aqds: Enable support for boot from QSPI freescale: cmd: qixis: tidy up the duplicated code LS2080QDS: QSPI boot: fix issues.
arch/arm/dts/fsl-ls2080a-qds.dts | 14 +++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 +++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 ++ board/freescale/common/qixis.c | 12 ++---- board/freescale/ls2080aqds/ls2080aqds.c | 16 ++++++++ common/board_f.c | 6 +-- configs/ls2080aqds_nand_defconfig | 9 +++++ configs/ls2080aqds_qspi_defconfig | 10 +++++ include/configs/ls2080a_common.h | 11 ++---- include/configs/ls2080a_simu.h | 7 ++++ include/configs/ls2080aqds.h | 43 +++++++++++++++++++++- 12 files changed, 124 insertions(+), 21 deletions(-) create mode 100644 configs/ls2080aqds_qspi_defconfig
From: Yuan Yao yao.yuan@nxp.com
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..e5acae8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -101,6 +101,7 @@ /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 +#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..6e73829 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -25,6 +25,7 @@
#define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
@@ -218,6 +219,10 @@ int board_init(void) int board_early_init_f(void) { fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif return 0; }
From: Yuan Yao yao.yuan@nxp.com
The NOR flash related configure options also appear in ls2080aqds.h and ls2080ardb.h, and the two files all have included ls2080a_common.h. This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080a_common.h | 7 ------- include/configs/ls2080a_simu.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 64b82e8..82af464 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -148,13 +148,6 @@ #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-#ifndef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); #endif diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 2c2ce7b..6a59afe 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -38,6 +38,13 @@ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#endif + /* * NOR Flash Timing Params */
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 02/12] configs: ls2080a_common: Remove duplicate NOR configs
From: Yuan Yao yao.yuan@nxp.com
The NOR flash related configure options also appear in ls2080aqds.h and ls2080ardb.h, and the two files all have included ls2080a_common.h. This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080a_common.h | 7 ------- include/configs/ls2080a_simu.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 64b82e8..82af464 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -148,13 +148,6 @@ #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-#ifndef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif
#ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); #endif diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 2c2ce7b..6a59afe 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -38,6 +38,13 @@ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define +CONFIG_SYS_FLASH_QUIET_TEST #endif
/*
- NOR Flash Timing Params
*/
I will suggest other way around-->. Remove above defines from qds, rdb, simu header file and put in ls2080a_common.h.
--prabhakar
On 03/03/2016 10:58AM, Prabhakar Kushwaha wrote:
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 02/12] configs: ls2080a_common: Remove duplicate NOR configs
From: Yuan Yao yao.yuan@nxp.com
The NOR flash related configure options also appear in ls2080aqds.h and ls2080ardb.h, and the two files all have included ls2080a_common.h. This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080a_common.h | 7 ------- include/configs/ls2080a_simu.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 64b82e8..82af464 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -148,13 +148,6 @@ #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-#ifndef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif
#ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); #endif diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 2c2ce7b..6a59afe 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -38,6 +38,13 @@ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define +CONFIG_SYS_FLASH_QUIET_TEST #endif
/*
- NOR Flash Timing Params
*/
I will suggest other way around-->. Remove above defines from qds, rdb, simu header file and put in ls2080a_common.h.
--prabhakar
Hi Prabhakar,
Because of the macro CONFIG_SYS_NO_FLASH Is must be define or not define in different board config file. So the #ifndef CONFIG_SYS_NO_FLASH can't put in ls2080a_common.h.
From: Yuan Yao yao.yuan@nxp.com
When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through IFC due to pin muxing.
Enable QIXIS accessing through I2C.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080aqds.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index dab3820..3edb0b9 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void); #endif
#define CONFIG_SYS_FSL_CLK + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_DDR_SPD
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 03/12] configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI
From: Yuan Yao yao.yuan@nxp.com
When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through IFC due to pin muxing.
Enable QIXIS accessing through I2C.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080aqds.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index dab3820..3edb0b9 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void); #endif
#define CONFIG_SYS_FSL_CLK
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 +#define CONFIG_QIXIS_I2C_ACCESS
If we are accessing QIXIS via I2c then why hard-coding SYSCLK and DDRCLK?
--prabhakar
On 03/03/2016 10:58AM, Prabhakar Kushwaha wrote:
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 03/12] configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI
From: Yuan Yao yao.yuan@nxp.com
When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through IFC due to pin muxing.
Enable QIXIS accessing through I2C.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080aqds.h | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index dab3820..3edb0b9 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void); #endif
#define CONFIG_SYS_FSL_CLK
+#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 +#define CONFIG_QIXIS_I2C_ACCESS
If we are accessing QIXIS via I2c then why hard-coding SYSCLK and DDRCLK?
If we aren't hard-coding SYSCLK and DDRCLK. We don't have any other way to get the SYSCLK and DDRCLK. We can't get it by read FPGA before config I2C.
From: Yuan Yao yao.yuan@nxp.com
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080aqds.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 3edb0b9..3cba10a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -292,11 +292,22 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_CH_DEFAULT 0x8
/* SPI */ -#ifdef CONFIG_FSL_DSPI +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH #endif
+#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ +#define FSL_QSPI_FLASH_NUM 4 +#endif /* * MMC */
From: Yuan Yao yao.yuan@nxp.com
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++++++++++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 547ec27..0a7f1ff 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -15,6 +15,7 @@ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases { + spi0 = &qspi; spi1 = &dspi; }; }; @@ -51,3 +52,16 @@ reg = <2>; }; }; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs256s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index a5c579c..68ed133 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -126,4 +126,14 @@ interrupts = <0 26 0x4>; /* Level high type */ num-cs = <6>; }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + num-cs = <4>; + }; };
From: Yuan Yao yao.yuan@nxp.com
If we want to access QSPI flash when boot from NAND, we need below board configuration: Boot Source ISO1 ISO2 IBOOT On-board NAND 1 0 0 IFCCARD NAND 0 0 1
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ board/freescale/ls2080aqds/ls2080aqds.c | 9 +++++++++ include/configs/ls2080aqds.h | 6 ++++++ 3 files changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e5acae8..828a53b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -94,6 +94,8 @@ #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR13 0x130 #define DCFG_RCWSR13_DSPI (0 << 8) +#define DCFG_RCWSR15 0x138 +#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 6e73829..7e09f11 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -207,6 +207,15 @@ int board_init(void) else config_board_mux(MUX_TYPE_SDHC);
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI) + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + QIXIS_WRITE(brdcfg[9], + (QIXIS_READ(brdcfg[9]) & 0xf8) | + FSL_QIXIS_BRDCFG9_QSPI); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 3cba10a..ee51348 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -307,6 +307,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ #define FSL_QSPI_FLASH_NUM 4 +/* + * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. + * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 + * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 + */ +#define FSL_QIXIS_BRDCFG9_QSPI 0x1 #endif /* * MMC
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
If we want to access QSPI flash when boot from NAND,
Is this "either this or that" choice? Is there any limitation after configuring pin mux?
we need below board configuration: Boot Source ISO1 ISO2 IBOOT On-board NAND 1 0 0 IFCCARD NAND 0 0 1
This should be added to README file.
York
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
If we want to access QSPI flash when boot from NAND,
Is this "either this or that" choice? Is there any limitation after configuring pin mux?
No, there is no any limitation. Just make a distinction between the different NAND source. And deasserted unused ISO will approve the performance.
Such as for LS2080AQDS, the last three bits for brdcfg[9] should be set to 0b'001.
we need below board configuration: Boot Source ISO1 ISO2 IBOOT On-board NAND 1 0 0 IFCCARD NAND 0 0 1
This should be added to README file.
So I need remove it from the uboot code?
On 03/02/2016 06:28 PM, Yao Yuan wrote:
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
If we want to access QSPI flash when boot from NAND,
Is this "either this or that" choice? Is there any limitation after configuring pin mux?
No, there is no any limitation. Just make a distinction between the different NAND source. And deasserted unused ISO will approve the performance.
Such as for LS2080AQDS, the last three bits for brdcfg[9] should be set to 0b'001.
we need below board configuration: Boot Source ISO1 ISO2 IBOOT On-board NAND 1 0 0 IFCCARD NAND 0 0 1
This should be added to README file.
So I need remove it from the uboot code?
No. I misunderstood you. Your change is to isolate IFC card. I didn't see why it has something to do with QSPI. At least you didn't make it clear in the commit message. You may consider to move the comment closer to the code.
York
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 06/12] armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
From: Yuan Yao yao.yuan@nxp.com
If we want to access QSPI flash when boot from NAND, we need below board configuration: Boot Source ISO1 ISO2 IBOOT On-board NAND 1 0 0 IFCCARD NAND 0 0 1
Signed-off-by: Yuan Yao yao.yuan@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ board/freescale/ls2080aqds/ls2080aqds.c | 9 +++++++++ include/configs/ls2080aqds.h | 6 ++++++ 3 files changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e5acae8..828a53b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -94,6 +94,8 @@ #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR13 0x130 #define DCFG_RCWSR13_DSPI (0 << 8) +#define DCFG_RCWSR15 0x138 +#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 6e73829..7e09f11 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -207,6 +207,15 @@ int board_init(void) else config_board_mux(MUX_TYPE_SDHC);
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
- val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
- if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
What about this
If (val & (u32) DCFG_RCWSR15_IFCGRPABASE_QSPI) != 0)
QIXIS_WRITE(brdcfg[9],(QIXIS_READ(brdcfg[9]) & 0xf8) |FSL_QIXIS_BRDCFG9_QSPI);+#endif
#ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 3cba10a..ee51348 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -307,6 +307,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ #define FSL_QSPI_FLASH_NUM 4 +/*
- Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
- If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
- If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 */
A minor comment, Put "*/" in next line. If you want can skip :)
--prabhakar
From: Yuan Yao yao.yuan@nxp.com
Freescale QSPI and DSPI driver have been converted to Driver Mode. This converting bring dtb file for u-boot and this increase the size of u-boot image. LS2080A nand boot use SPL framework. This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080aqds.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 82af464..8048753 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -305,7 +305,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index ee51348..eaca55c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -240,7 +240,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
From: Yuan Yao yao.yuan@nxp.com
The Freescale QSPI driver has been converted to Driver Model. This patch enable FSL_QSPI and its dependence options, DM, DM_SPI, OF_CONTROL and so on.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- configs/ls2080aqds_nand_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index b7d64f6..3a970b0 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -2,6 +2,15 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- configs/ls2080aqds_qspi_defconfig | 10 ++++++++++ include/configs/ls2080a_common.h | 2 ++ include/configs/ls2080aqds.h | 12 +++++++++++- 3 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 configs/ls2080aqds_qspi_defconfig
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig new file mode 100644 index 0000000..8f84b23 --- /dev/null +++ b/configs/ls2080aqds_qspi_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_QSPI=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 8048753..c131441 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -29,11 +29,13 @@ #define CONFIG_ARCH_MISC_INIT
/* Link Definitions */ +#ifndef CONFIG_QSPI_BOOT #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif +#endif
#ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index eaca55c..513a2e3 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -17,8 +17,16 @@ unsigned long get_board_ddr_clk(void); #endif
#define CONFIG_SYS_FSL_CLK +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x20010000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif
-#ifdef CONFIG_FSL_QSPI +#if defined(CONFIG_QSPI_BOOT) || \ + (defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)) #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS #define CONFIG_SYS_CLK_FREQ 100000000 @@ -270,11 +278,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif +#endif
/* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Please update the README file to include procedure to deply QSPI image.
York
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Please update the README file to include procedure to deply QSPI image.
York
Hi York,
Thanks for your review. So where should I put the README file?
On 03/02/2016 06:30 PM, Yao Yuan wrote:
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Please update the README file to include procedure to deply QSPI image.
York
Hi York,
Thanks for your review. So where should I put the README file?
board/freescale/ls2080aqds/README
York
On 03/04/2016 12:49 AM, York Sun wrote:
On 03/02/2016 06:30 PM, Yao Yuan wrote:
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Please update the README file to include procedure to deply QSPI image.
York
Hi York,
Thanks for your review. So where should I put the README file?
board/freescale/ls2080aqds/README
York
Hi York,
Do you know is there any example exist in uboot that I can take reference? Or is there any format and content requirement for the procedure to deply QSPI image?
Thanks.
On 03/06/2016 10:09 PM, Yao Yuan wrote:
On 03/04/2016 12:49 AM, York Sun wrote:
On 03/02/2016 06:30 PM, Yao Yuan wrote:
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Please update the README file to include procedure to deply QSPI image.
York
Hi York,
Thanks for your review. So where should I put the README file?
board/freescale/ls2080aqds/README
York
Hi York,
Do you know is there any example exist in uboot that I can take reference? Or is there any format and content requirement for the procedure to deply QSPI image?
Yuan,
There are some README files with similar information, for example
doc/README.pblimage board/freescale/t102xqds/README
York
From: Yuan Yao yao.yuan@nxp.com
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080aqds.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 513a2e3..064e341 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -183,11 +183,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080aqds.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 513a2e3..064e341 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -183,11 +183,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
Why wasn't this patch squashed with the 9th patch in this set?
York
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
Signed-off-by: Yuan Yao yao.yuan@nxp.com
include/configs/ls2080aqds.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 513a2e3..064e341 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -183,11 +183,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
Why wasn't this patch squashed with the 9th patch in this set?
York
This patch is just adding the command: qixis_reset qspi support on LS2080AQDS.
9th patch is used for add the QSPI Boot support.
The function is different. But I can also merge them into one patch. It seems more tidy.
From: Yuan Yao yao.yuan@nxp.com
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- board/freescale/common/qixis.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 113295f..de9daeb 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -211,8 +211,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_NAND); set_rcw_src(QIXIS_RCW_SRC_NAND); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + qixis_bank_reset(); #else printf("Not implemented\n"); #endif @@ -222,8 +221,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + qixis_bank_reset(); #else printf("Not implemented\n"); #endif @@ -233,8 +231,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_SD_QSPI); set_rcw_src(QIXIS_RCW_SRC_SD); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_bank_reset(); #else printf("Not implemented\n"); #endif @@ -244,8 +241,7 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) QIXIS_WRITE(rcfg_ctl, 0); set_lbmap(QIXIS_LBMAP_QSPI); set_rcw_src(QIXIS_RCW_SRC_QSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); + qixis_bank_reset(); #else printf("Not implemented\n"); #endif
From: Yuan Yao yao.yuan@nxp.com
This patch is used for fix the bug below: /*******************************************/ "Synchronous Abort" handler, esr 0x86000210 ELR: fff6cfb4 LR: fff6d3f0 x0 : 0000000000000022 x1 : 00000000fff78c6f x2 : 00000000ffd0ecb0 x3 : 0000000000000000 x4 : 00000000ffd0ecd0 x5 : 0000000000000000 x6 : 00000000ffffffc8 x7 : 000000003fe00000 x8 : 00000083ffe00000 x9 : 000000000000000c x10: 0000008400000000 x11: 000000000000000c x12: 0000000000000015 x13: 0000000040000000 x14: 0000000000200000 x15: 0000000000000001 x16: 000000001800f188 x17: 0000000000000001 x18: 00000000ffd11d78 x19: 00000000ffd0f010 x20: 00000000ffd0ed39 x21: 00000000fff80935 x22: 00000000fff78c6f x23: 0000000000000001 x24: 00000000ffd0f010 x25: 00000000ffd0ed38 x26: 00000000fff738e0 x27: 00000000fff72460 x28: 00000000fff92000 x29: 00000000ffd0ebd0
Resetting CPU ... /*******************************************/
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ common/board_f.c | 6 +++--- 3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 15ade84..794b764 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[] = { PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PMD_SECT_NON_SHARE}, /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, @@ -172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PMD_SECT_NON_SHARE}, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7e09f11..8e174c3 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -80,6 +80,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); + else if (sw == 0xf) + puts("QSPI\n"); else if (sw == 0x15) printf("IFCCard\n"); else diff --git a/common/board_f.c b/common/board_f.c index 622093a..1af1b4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_DISPLAY_BOARDINFO) - show_board_info, -#endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, @@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_DISPLAY_BOARDINFO) + show_board_info, +#endif #if defined(CONFIG_HARD_SPI) init_func_spi, #endif
First, please do not add a period sign in the subject. Second, the subject doesn't have much useful information.
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch is used for fix the bug below: /*******************************************/ "Synchronous Abort" handler, esr 0x86000210 ELR: fff6cfb4 LR: fff6d3f0 x0 : 0000000000000022 x1 : 00000000fff78c6f x2 : 00000000ffd0ecb0 x3 : 0000000000000000 x4 : 00000000ffd0ecd0 x5 : 0000000000000000 x6 : 00000000ffffffc8 x7 : 000000003fe00000 x8 : 00000083ffe00000 x9 : 000000000000000c x10: 0000008400000000 x11: 000000000000000c x12: 0000000000000015 x13: 0000000040000000 x14: 0000000000200000 x15: 0000000000000001 x16: 000000001800f188 x17: 0000000000000001 x18: 00000000ffd11d78 x19: 00000000ffd0f010 x20: 00000000ffd0ed39 x21: 00000000fff80935 x22: 00000000fff78c6f x23: 0000000000000001 x24: 00000000ffd0f010 x25: 00000000ffd0ed38 x26: 00000000fff738e0 x27: 00000000fff72460 x28: 00000000fff92000 x29: 00000000ffd0ebd0
Resetting CPU ... /*******************************************/
This commit message is not appropriate. It doesn't match the change either. You should explain why a new entry was added to MMU table, and why you moved "show_board_info" down.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ common/board_f.c | 6 +++--- 3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 15ade84..794b764 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[] = { PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PMD_SECT_NON_SHARE},@@ -172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PMD_SECT_NON_SHARE},diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7e09f11..8e174c3 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -80,6 +80,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n");
- else if (sw == 0xf)
puts("QSPI\n");diff --git a/common/board_f.c b/common/board_f.c index 622093a..1af1b4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
-#endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, @@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
+#endif #if defined(CONFIG_HARD_SPI) init_func_spi, #endif
York
On 03/03/2016 12:52 AM, York Sun wrote:
On 03/02/2016 02:41 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
This patch is used for fix the bug below: /*******************************************/ "Synchronous Abort" handler, esr 0x86000210 ELR: fff6cfb4 LR: fff6d3f0 x0 : 0000000000000022 x1 : 00000000fff78c6f x2 : 00000000ffd0ecb0 x3 : 0000000000000000 x4 : 00000000ffd0ecd0 x5 : 0000000000000000 x6 : 00000000ffffffc8 x7 : 000000003fe00000 x8 : 00000083ffe00000 x9 : 000000000000000c x10: 0000008400000000 x11: 000000000000000c x12: 0000000000000015 x13: 0000000040000000 x14: 0000000000200000 x15: 0000000000000001 x16: 000000001800f188 x17: 0000000000000001 x18: 00000000ffd11d78 x19: 00000000ffd0f010 x20: 00000000ffd0ed39 x21: 00000000fff80935 x22: 00000000fff78c6f x23: 0000000000000001 x24: 00000000ffd0f010 x25: 00000000ffd0ed38 x26: 00000000fff738e0 x27: 00000000fff72460 x28: 00000000fff92000 x29: 00000000ffd0ebd0
Resetting CPU ... /*******************************************/
This commit message is not appropriate. It doesn't match the change either. You should explain why a new entry was added to MMU table, and why you moved "show_board_info" down.
Ok, I will update the commit message in the next version. Thanks.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ common/board_f.c | 6 +++--- 3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 15ade84..794b764 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[]
= {
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL,
PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL,
PMD_SECT_NON_SHARE }, @@
-172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, diff -
-git
a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7e09f11..8e174c3 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -80,6 +80,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n");
- else if (sw == 0xf)
puts("QSPI\n");diff --git a/common/board_f.c b/common/board_f.c index 622093a..1af1b4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
-#endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, @@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
+#endif #if defined(CONFIG_HARD_SPI) init_func_spi, #endif
York
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 12/12] LS2080QDS: QSPI boot: fix issues.
From: Yuan Yao yao.yuan@nxp.com
This patch is used for fix the bug below: /*******************************************/ "Synchronous Abort" handler, esr 0x86000210 ELR: fff6cfb4 LR: fff6d3f0 x0 : 0000000000000022 x1 : 00000000fff78c6f x2 : 00000000ffd0ecb0 x3 : 0000000000000000 x4 : 00000000ffd0ecd0 x5 : 0000000000000000 x6 : 00000000ffffffc8 x7 : 000000003fe00000 x8 : 00000083ffe00000 x9 : 000000000000000c x10: 0000008400000000 x11: 000000000000000c x12: 0000000000000015 x13: 0000000040000000 x14: 0000000000200000 x15: 0000000000000001 x16: 000000001800f188 x17: 0000000000000001 x18: 00000000ffd11d78 x19: 00000000ffd0f010 x20: 00000000ffd0ed39 x21: 00000000fff80935 x22: 00000000fff78c6f x23: 0000000000000001 x24: 00000000ffd0f010 x25: 00000000ffd0ed38 x26: 00000000fff738e0 x27: 00000000fff72460 x28: 00000000fff92000 x29: 00000000ffd0ebd0
Resetting CPU ... /*******************************************/
Can you please share more detail about error
Signed-off-by: Yuan Yao yao.yuan@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ common/board_f.c | 6 +++--- 3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 15ade84..794b764 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[] = { PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE}, /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, @@ -172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE}, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7e09f11..8e174c3 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -80,6 +80,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n");
- else if (sw == 0xf)
puts("QSPI\n");
This fix is nowhere related to the error you are fixing?
else if (sw == 0x15) printf("IFCCard\n"); else diff --git a/common/board_f.c b/common/board_f.c index 622093a..1af1b4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
-#endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, @@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
+#endif
This fix is nowhere related to the error you are fixing?
--prabhakar
On 03/03/2016 10:58AM, Prabhakar Kushwaha wrote:
-----Original Message----- From: Yuan Yao [mailto:yao.yuan@freescale.com] Sent: Wednesday, March 02, 2016 4:02 PM To: york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; pratiyush.srivastava@freescale.com; u-boot@lists.denx.de; Yunhui Cui yunhui.cui@nxp.com; Yao Yuan yao.yuan@nxp.com Subject: [PATCH 12/12] LS2080QDS: QSPI boot: fix issues.
From: Yuan Yao yao.yuan@nxp.com
This patch is used for fix the bug below: /*******************************************/ "Synchronous Abort" handler, esr 0x86000210 ELR: fff6cfb4 LR: fff6d3f0 x0 : 0000000000000022 x1 : 00000000fff78c6f x2 : 00000000ffd0ecb0 x3 : 0000000000000000 x4 : 00000000ffd0ecd0 x5 : 0000000000000000 x6 : 00000000ffffffc8 x7 : 000000003fe00000 x8 : 00000083ffe00000 x9 : 000000000000000c x10: 0000008400000000 x11: 000000000000000c x12: 0000000000000015 x13: 0000000040000000 x14: 0000000000200000 x15: 0000000000000001 x16: 000000001800f188 x17: 0000000000000001 x18: 00000000ffd11d78 x19: 00000000ffd0f010 x20: 00000000ffd0ed39 x21: 00000000fff80935 x22: 00000000fff78c6f x23: 0000000000000001 x24: 00000000ffd0f010 x25: 00000000ffd0ed38 x26: 00000000fff738e0 x27: 00000000fff72460 x28: 00000000fff92000 x29: 00000000ffd0ebd0
Resetting CPU ... /*******************************************/
Can you please share more detail about error
Sorry, what do you means? I will update the commit message as York suggested before.
Thanks.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ common/board_f.c | 6 +++--- 3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 15ade84..794b764 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -120,6 +120,8 @@ static const struct sys_mmu_table early_mmu_table[] = { PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL,
PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE}, /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL,
PMD_SECT_NON_SHARE }, @@
-172,6 +174,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL,PMD_SECT_NON_SHARE}, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, diff -
-git
a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7e09f11..8e174c3 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -80,6 +80,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n");
- else if (sw == 0xf)
puts("QSPI\n");This fix is nowhere related to the error you are fixing?
Yes, I will rewrite my commit for those patch. This patch is used to fix two issue when QSPI boot.
else if (sw == 0x15) printf("IFCCard\n"); else diff --git a/common/board_f.c b/common/board_f.c index 622093a..1af1b4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -912,9 +912,6 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_MPC5xxx) prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
-#endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) misc_init_f, @@ -923,6 +920,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_DISPLAY_BOARDINFO)
- show_board_info,
+#endif
This fix is nowhere related to the error you are fixing?
--prabhakar
Yes, I will rewrite my commit for those patch. This patch is used to fix two issue when QSPI boot.
participants (4)
-
Prabhakar Kushwaha -
Yao Yuan -
york sun -
Yuan Yao