From: Matt Porter matt.porter@linaro.org

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter matt.porter@linaro.org Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 7 +++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap5/omap.h | 3 +++ arch/arm/include/asm/arch-omap5/spl.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 5 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 07b1108..4d0eb45 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -425,6 +425,9 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, + #ifdef CONFIG_TI_QSPI + (*prcm)->cm_l4per_qspi_clkctrl, + #endif 0 };

@@ -453,6 +456,10 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1);

+#ifdef CONFIG_TI_QSPI + setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); +#endif + /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e839ff5..7d41744 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -942,6 +942,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_l4per_gpio8_clkctrl = 0x4a009818, .cm_l4per_mmcsd3_clkctrl = 0x4a009820, .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_qspi_clkctrl = 0x4a009838, .cm_l4per_uart1_clkctrl = 0x4a009840, .cm_l4per_uart2_clkctrl = 0x4a009848, .cm_l4per_uart3_clkctrl = 0x4a009850, diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 5e6d82e..30c913e 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -77,6 +77,9 @@ /* GPMC */ #define OMAP54XX_GPMC_BASE 0x50000000

+/* QSPI */ +#define QSPI_BASE 0x4B300000 + /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index d4d353c..8905cb8 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -31,6 +31,7 @@ #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10

#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0dbe81b..e37de8c 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -281,6 +281,7 @@ struct prcm_regs { u32 cm_l4per_mmcsd4_clkctrl; u32 cm_l4per_msprohg_clkctrl; u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_qspi_clkctrl; u32 cm_l4per_uart1_clkctrl; u32 cm_l4per_uart2_clkctrl; u32 cm_l4per_uart3_clkctrl;

From: Matt Porter matt.porter@linaro.org

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter matt.porter@linaro.org Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/spi/Makefile | 1 + drivers/spi/ti_qspi.c | 262 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 263 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/ti_qspi.c

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..f51033d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o

COBJS := $(COBJS-y) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c new file mode 100644 index 0000000..1973b85 --- /dev/null +++ b/drivers/spi/ti_qspi.c @@ -0,0 +1,262 @@ +/* + * TI QSPI driver + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/omap.h> +#include <malloc.h> +#include <spi.h> + +struct qspi_slave { + struct spi_slave slave; + unsigned int mode; + u32 cmd; + u32 dc; +}; + +#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave) + +struct qspi_regs { + u32 pid; + u32 pad0[3]; + u32 sysconfig; + u32 pad1[3]; + u32 intr_status_raw_set; + u32 intr_status_enabled_clear; + u32 intr_enable_set; + u32 intr_enable_clear; + u32 intc_eoi; + u32 pad2[3]; + u32 spi_clock_cntrl; + u32 spi_dc; + u32 spi_cmd; + u32 spi_status; + u32 spi_data; + u32 spi_setup0; + u32 spi_setup1; + u32 spi_setup2; + u32 spi_setup3; + u32 spi_switch; + u32 spi_data1; + u32 spi_data2; + u32 spi_data3; +}; + +static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; + +#define QSPI_TIMEOUT 2000000 + +#define QSPI_FCLK 192000000 + +/* Clock Control */ +#define QSPI_CLK_EN (1 << 31) +#define QSPI_CLK_DIV_MAX 0xffff + +/* Command */ +#define QSPI_EN_CS(n) (n << 28) +#define QSPI_WLEN(n) ((n-1) << 19) +#define QSPI_3_PIN (1 << 18) +#define QSPI_RD_SNGL (1 << 16) +#define QSPI_WR_SNGL (2 << 16) +#define QSPI_INVAL (4 << 16) + +/* Device Control */ +#define QSPI_DD(m, n) (m << (3 + n*8)) +#define QSPI_CKPHA(n) (1 << (2 + n*8)) +#define QSPI_CSPOL(n) (1 << (1 + n*8)) +#define QSPI_CKPOL(n) (1 << (n*8)) + +/* Status */ +#define QSPI_WC (1 << 1) +#define QSPI_BUSY (1 << 0) +#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) +#define QSPI_XFER_DONE QSPI_WC + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_init(void) +{ + /* nothing to do */ +} + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + uint clk_div; + + if (!hz) + clk_div = 0; + else + clk_div = (QSPI_FCLK / hz) - 1; + + debug("%s: hz: %d, clock divider %d\n", __func__, hz, clk_div); + + /* disable SCLK */ + writel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN, &qspi->spi_clock_cntrl); + + if (clk_div < 0) { + debug("%s: clock divider < 0, using /1 divider\n", __func__); + clk_div = 0; + } + + if (clk_div > QSPI_CLK_DIV_MAX) { + debug("%s: clock divider >%d , using /%d divider\n", + __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); + clk_div = QSPI_CLK_DIV_MAX; + } + + /* enable SCLK */ + writel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl); + debug("%s: spi_clock_cntrl %08x\n", __func__, readl(&qspi->spi_clock_cntrl)); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct qspi_slave *qslave; + + qslave = spi_alloc_slave(struct qspi_slave, bus, cs); + if (!qslave) + return NULL; + + spi_set_speed(&qslave->slave, max_hz); + qslave->mode = mode; + debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode); + + return &qslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct qspi_slave *qslave = to_qspi_slave(slave); + free(qslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + writel(0, &qspi->spi_dc); + writel(0, &qspi->spi_cmd); + writel(0, &qspi->spi_data); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + writel(0, &qspi->spi_dc); + writel(0, &qspi->spi_cmd); + writel(0, &qspi->spi_data); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct qspi_slave *qslave = to_qspi_slave(slave); + uint words = bitlen >> 3; /* fixed 8-bit word length */ + const uchar *txp = dout; + uchar *rxp = din; + uint status; + int timeout; + + debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, words, flags); + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + return -1; + } + + /* setup command reg */ + qslave->cmd = 0; + qslave->cmd |= QSPI_WLEN(8); + qslave->cmd |= QSPI_EN_CS(slave->cs); + if (flags & SPI_3WIRE) + qslave->cmd |= QSPI_3_PIN; + qslave->cmd |= 0xfff; + + /* setup device control reg */ + qslave->dc = 0; + if (qslave->mode & SPI_CPHA) + qslave->dc |= QSPI_CKPHA(slave->cs); + if (qslave->mode & SPI_CPOL) + qslave->dc |= QSPI_CKPOL(slave->cs); + if (qslave->mode & SPI_CS_HIGH) + qslave->dc |= QSPI_CSPOL(slave->cs); + + while (words--) { + if (txp) { + debug("tx cmd %08x dc %08x data %02x\n", + qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); + writel(*txp++, &qspi->spi_data); + writel(qslave->dc, &qspi->spi_dc); + writel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd); + status = readl(&qspi->spi_status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("QSPI tx timed out\n"); + return -1; + } + status = readl(&qspi->spi_status); + } + debug("tx done, status %08x\n", status); + } + if (rxp) { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_SNGL, qslave->dc); + writel(qslave->dc, &qspi->spi_dc); + writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd); + status = readl(&qspi->spi_status); + timeout = QSPI_TIMEOUT; + while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { + if (--timeout < 0) { + printf("QSPI rx timed out\n"); + return -1; + } + status = readl(&qspi->spi_status); + } + *rxp++ = readl(&qspi->spi_data); + debug("rx done, status %08x, read %02x\n", + status, *(rxp-1)); + } + } + + /* Terminate frame */ + if (flags & SPI_XFER_END) + writel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd); + + return 0; +}

Reading using the already supported read command is causing regression after 4k bytes, as a result doing a page by page read. Its happening, because ti qpsi controller CS will get de asserted after 4096 bytes.

Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/mtd/spi/spi_flash.c | 32 +++++++++++++++++++++++++++++++- 1 files changed, 31 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6a6fe37..5f8db7b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, else read_len = remain_len;

+#ifdef CONFIG_TI_QSPI + unsigned long page_addr, byte_addr, page_size; + size_t chunk_len, actual; + int ret = 0; + + page_size = flash->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + for (actual = 0; actual < read_len; actual += chunk_len) { + chunk_len = min(read_len - actual, page_size - byte_addr); + + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + ret = spi_flash_read_common(flash, cmd, sizeof(cmd), + data + actual, chunk_len); + if (ret < 0) { + debug("SF: read failed"); + break; + } + + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } + } +#else spi_flash_addr(offset, cmd);

ret = spi_flash_read_common(flash, cmd, sizeof(cmd), @@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, debug("SF: read failed\n"); break; } - +#endif offset += read_len; len -= read_len; data += read_len;

From: Ravikumar Kattekola rk@ti.com

Add Quad read mode (6 pin interface) support to spi flash and ti qspi driver.

Quad mode (0x6bh on spansion) uses two extra pins (D2 and D3) for data transfer apart from the usual D0 and D1 pins thus transfering 4 bits per cycle.

Signed-off-by: Ravikumar Kattekola rk@ti.com Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/mtd/spi/spi_flash.c | 110 +++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi_flash_internal.h | 2 + drivers/spi/ti_qspi.c | 18 ++++-- include/configs/dra7xx_evm.h | 1 + include/spi.h | 2 + 5 files changed, 127 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5f8db7b..c81f402 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -42,7 +42,12 @@ static int spi_flash_read_write(struct spi_slave *spi, debug("SF: Failed to send command (%zu bytes): %d\n", cmd_len, ret); } else if (data_len != 0) { - ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); + if (spi->quad_enable) + flags = SPI_6WIRE; + else + flags = 0; + + ret = spi_xfer(spi, data_len * 8, data_out, data_in, flags | SPI_XFER_END); if (ret) debug("SF: Failed to transfer %zu bytes of data: %d\n", data_len, ret); @@ -271,6 +276,51 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, return ret; }

+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + + unsigned long page_addr, byte_addr, page_size; + size_t chunk_len, actual; + int ret = 0; + u8 cmd[5]; + + spi->quad_enable = 1; + /* Handle memory-mapped SPI */ + if (flash->memory_map) + memcpy(data, flash->memory_map + offset, len); + + page_size = flash->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = CMD_READ_ARRAY_QUAD; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + cmd[4] = 0x0; + + ret = spi_flash_read_common(flash, cmd, sizeof(cmd), + data + actual, chunk_len); + if (ret < 0) { + debug("SF: read failed"); + break; + } + + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } + } + + return ret; +} + int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, size_t len, void *data) { @@ -424,6 +474,56 @@ int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) } #endif

+int spi_flash_en_quad_mode(struct spi_flash *flash) +{ + u8 stat, con, cd; + u16 cr; + int ret; + cd = CMD_WRITE_STATUS; + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + goto out; + } + ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1); + ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1); + if (ret < 0) { + debug("%s: SF: read CR failed\n", __func__); + goto out; + } + /* Byte 1 - status reg, Byte 2 - config reg */ + cr = ((con | (0x1 << 1)) << 8) | (stat << 0); + + ret = spi_flash_cmd_write(flash->spi, &cd, 1, &cr, 2); + if (ret) { + debug("SF: fail to write conf register\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write conf register timed out\n"); + goto out; + } + + ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1); + ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1); + if (ret < 0) { + debug("%s: SF: read CR failed\n", __func__); + goto out; + } + debug("%s: *** CR = %x\n", __func__, con); + + ret = spi_flash_cmd_write_disable(flash); + if (ret < 0) { + debug("SF: disabling write failed\n"); + goto out; + } +out: + return ret; +} + #ifdef CONFIG_OF_CONTROL int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) { @@ -578,6 +678,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; #endif

+#ifdef CONFIG_SF_QUAD_RD + spi_flash_en_quad_mode(flash); +#endif + #ifdef CONFIG_OF_CONTROL if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { debug("SF: FDT decode error\n"); @@ -628,7 +732,11 @@ void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, flash->name = name; flash->poll_cmd = CMD_READ_STATUS;

+#ifdef CONFIG_SF_QUAD_RD + flash->read = spi_flash_cmd_read_quad; +#else flash->read = spi_flash_cmd_read_fast; +#endif flash->write = spi_flash_cmd_write_multi; flash->erase = spi_flash_cmd_erase;

diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index af1afa9..1205a7a 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -17,11 +17,13 @@

#define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_ARRAY_QUAD 0x6b

#define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 #define CMD_WRITE_ENABLE 0x06 #define CMD_ERASE_4K 0x20 diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 1973b85..12bba11 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -72,6 +72,7 @@ static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; #define QSPI_RD_SNGL (1 << 16) #define QSPI_WR_SNGL (2 << 16) #define QSPI_INVAL (4 << 16) +#define QSPI_RD_QUAD (7 << 16)

/* Device Control */ #define QSPI_DD(m, n) (m << (3 + n*8)) @@ -235,10 +236,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, debug("tx done, status %08x\n", status); } if (rxp) { - debug("rx cmd %08x dc %08x\n", - qslave->cmd | QSPI_RD_SNGL, qslave->dc); - writel(qslave->dc, &qspi->spi_dc); - writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd); + if (flags & SPI_6WIRE) { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_QUAD, qslave->dc); + writel(qslave->cmd | QSPI_RD_QUAD, + &qspi->spi_cmd); + } else { + debug("rx cmd %08x dc %08x\n", + qslave->cmd | QSPI_RD_SNGL, qslave->dc); + writel(qslave->cmd | QSPI_RD_SNGL, + &qspi->spi_cmd); + } status = readl(&qspi->spi_status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { @@ -250,7 +258,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } *rxp++ = readl(&qspi->spi_data); debug("rx done, status %08x, read %02x\n", - status, *(rxp-1)); + status, *(rxp-1)); } }

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f30a795..9d11820 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -50,6 +50,7 @@ #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_CMD_SPI +#define CONFIG_SF_QUAD_RD #define CONFIG_SF_DEFAULT_SPEED 12000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3

diff --git a/include/spi.h b/include/spi.h index e8e6544..d5a0ead 100644 --- a/include/spi.h +++ b/include/spi.h @@ -39,6 +39,7 @@ #define SPI_LOOP 0x20 /* loopback mode */ #define SPI_SLAVE 0x40 /* slave mode */ #define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ +#define SPI_6WIRE 0x10 /* 4 data lines */

/* SPI transfer flags */ #define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ @@ -61,6 +62,7 @@ struct spi_slave { unsigned int bus; unsigned int cs; unsigned int max_write_size; + bool quad_enable; };

/*-----------------------------------------------------------------------

Qspi controller has a memory mapped port which can be used for data transfers. First controller need to be configured through configuration port, then for data read switch the controller to memory mapped and read from the predefined location.

Signed-off-by: Sourav Poddar sourav.poddar@ti.com --- drivers/mtd/spi/spansion.c | 1 + drivers/mtd/spi/spi_flash.c | 8 +++- drivers/spi/ti_qspi.c | 85 +++++++++++++++++++++++++++++++++++------- include/configs/dra7xx_evm.h | 3 +- include/spi.h | 3 + 5 files changed, 84 insertions(+), 16 deletions(-)

diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 3ec2151..1f60456 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -151,6 +151,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) flash->page_size = 256; flash->sector_size = 256 * params->pages_per_sector; flash->size = flash->sector_size * params->nr_sectors; + flash->memory_map = spi->memory_map;

return flash; } diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c81f402..c1173d8 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -288,8 +288,12 @@ int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,

spi->quad_enable = 1; /* Handle memory-mapped SPI */ - if (flash->memory_map) + if (flash->memory_map) { + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP); memcpy(data, flash->memory_map + offset, len); + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END); + return 0; + }

page_size = flash->page_size; page_addr = offset / page_size; @@ -330,7 +334,9 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,

/* Handle memory-mapped SPI */ if (flash->memory_map) { + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP); memcpy(data, flash->memory_map + offset, len); + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END); return 0; }

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 12bba11..d314b6e 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -23,8 +23,8 @@ struct qspi_slave { struct spi_slave slave; unsigned int mode; - u32 cmd; - u32 dc; + u32 cmd; + u32 dc; };

#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave) @@ -86,6 +86,24 @@ static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE; #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC

+#define MM_SWITCH 0x01 +#define MEM_CS 0x100 +#define MEM_CS_UNSELECT 0xfffff0ff +#define MMAP_START_ADDR 0x5c000000 +#define CORE_CTRL_IO 0x4a002558 + +#define QSPI_CMD_READ (0x3 << 0) +#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_FAST (0x0b << 0) + +#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) +#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) +#define QSPI_SETUP0_READ_NORMAL (0x0 << 12) +#define QSPI_SETUP0_READ_QUAD (0x3 << 12) +#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_NUM_DUMMY_BITS (0x0 << 24) + int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return 1; @@ -108,6 +126,24 @@ void spi_init(void) /* nothing to do */ }

+void spi_set_up_spi_register(struct spi_slave *slave) +{ + u32 memval = 0; + + slave->memory_map = (void *)MMAP_START_ADDR; + +#ifdef CONFIG_SF_QUAD_RD + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_READ_QUAD | + QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS); +#else + memval |= (QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL | + QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS); +#endif + writel(memval, &qspi->spi_setup0); +} + void spi_set_speed(struct spi_slave *slave, uint hz) { uint clk_div; @@ -149,6 +185,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,

spi_set_speed(&qslave->slave, max_hz); qslave->mode = mode; + +#ifdef CONFIG_MMAP + spi_set_up_spi_register(&qslave->slave); +#endif + debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode);

return &qslave->slave; @@ -188,12 +229,37 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const uchar *txp = dout; uchar *rxp = din; uint status; - int timeout; + int timeout, val;

debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__, slave->bus, slave->cs, bitlen, words, flags); - if (bitlen == 0) - return -1; + + qslave->dc = 0; + if (qslave->mode & SPI_CPHA) + qslave->dc |= QSPI_CKPHA(slave->cs); + if (qslave->mode & SPI_CPOL) + qslave->dc |= QSPI_CKPOL(slave->cs); + if (qslave->mode & SPI_CS_HIGH) + qslave->dc |= QSPI_CSPOL(slave->cs); + + writel(qslave->dc, &qspi->spi_dc); + + if (flags == SPI_XFER_MEM_MAP) { + writel(MM_SWITCH, &qspi->spi_switch); + val = readl(CORE_CTRL_IO); + val |= MEM_CS; + writel(val, CORE_CTRL_IO); + return 0; + } else if (flags == SPI_XFER_MEM_MAP_END) { + writel(~MM_SWITCH, &qspi->spi_switch); + val = readl(CORE_CTRL_IO); + val &= MEM_CS_UNSELECT; + writel(val, CORE_CTRL_IO); + return 0; + } + + if (bitlen == 0) + return -1;

if (bitlen % 8) { flags |= SPI_XFER_END; @@ -208,15 +274,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd |= QSPI_3_PIN; qslave->cmd |= 0xfff;

- /* setup device control reg */ - qslave->dc = 0; - if (qslave->mode & SPI_CPHA) - qslave->dc |= QSPI_CKPHA(slave->cs); - if (qslave->mode & SPI_CPOL) - qslave->dc |= QSPI_CKPOL(slave->cs); - if (qslave->mode & SPI_CS_HIGH) - qslave->dc |= QSPI_CSPOL(slave->cs); - while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 9d11820..4d80a01 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -51,7 +51,8 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_SF_QUAD_RD -#define CONFIG_SF_DEFAULT_SPEED 12000000 +#define CONFIG_MMAP +#define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3

/* SPI SPL */ diff --git a/include/spi.h b/include/spi.h index d5a0ead..890e739 100644 --- a/include/spi.h +++ b/include/spi.h @@ -48,6 +48,8 @@ /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec

+#define SPI_XFER_MEM_MAP 0x05 +#define SPI_XFER_MEM_MAP_END 0x06 /*----------------------------------------------------------------------- * Representation of a SPI slave, i.e. what we're communicating with. * @@ -63,6 +65,7 @@ struct spi_slave { unsigned int cs; unsigned int max_write_size; bool quad_enable; + void *memory_map; };

/*-----------------------------------------------------------------------