[U-Boot] [PATCH 18/25] x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng bmeng.cn@gmail.com --- arch/x86/Kconfig | 13 ++++++++ arch/x86/cpu/queensbay/Kconfig | 75 ++++++++++++++++++++++++++++++++++++++++++ board/intel/crownbay/Kconfig | 20 +++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb618..ebf72b3 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CROWNBAY + bool "Support Intel Crown Bay CRB" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + endchoice
config RAMBASE @@ -310,8 +319,12 @@ endmenu
source "arch/x86/cpu/ivybridge/Kconfig"
+source "arch/x86/cpu/queensbay/Kconfig" + source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/intel/crownbay/Kconfig" + endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 0000000..3441413 --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,75 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_QUEENSBAY + bool + select HAVE_FSP + select HAVE_CMC + +if INTEL_QUEENSBAY + +config HAVE_FSP + bool "Add an Firmware Support Package binary" + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string "Firmware Support Package binary path and filename" + depends on HAVE_FSP + default "fsp.bin" + help + The path and filename of the file to use as Firmware Support Package + binary. + +config FSP_LOCATION + hex "Firmware Support Package binary location" + depends on HAVE_FSP + default 0xfffc0000 + help + FSP is not Pisition Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc0000 indicates that the binary must + be located at offset 0xc0000 from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x2000000 + +config HAVE_CMC + bool "Add a Chipset Micro Code state machine binary" + help + Select this option to add a Chipset Micro Code state machine binary + to the resulting U-Boot image. It is a binary blob which must be put + in the flash for the processor to access when power up. + +config CMC_FILE + string "Chipset Micro Code state machine binary path and filename" + depends on HAVE_CMC + default "C0_22211.BIN" + help + The path and filename of the file to use as Chipset Micro Code + state machine binary. + +config CMC_LOCATION + hex "Chipset Micro Code state machine binary location" + depends on HAVE_CMC + default 0xfffb0000 + help + The location of the CMC binary is determined by a strap. It must be + put in flash at a location matching the strap-determined base address. + + The default base address of 0xfffb0000 indicates that the binary must + be located at offset 0xb0000 from the beginning of a 1MB flash device. + +endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 0000000..4709f9b --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,20 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default "crownbay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "queensbay" + +config SYS_CONFIG_NAME + default "crownbay" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select INTEL_QUEENSBAY + select BOARD_ROMSIZE_KB_1024 + +endif
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng.cn@gmail.com wrote:
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/Kconfig | 13 ++++++++ arch/x86/cpu/queensbay/Kconfig | 75 ++++++++++++++++++++++++++++++++++++++++++ board/intel/crownbay/Kconfig | 20 +++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb618..ebf72b3 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CROWNBAY
bool "Support Intel Crown Bay CRB"helpThis is the Intel Crown Bay Customer Reference Board. It containsthe Intel Atom Processor E6xx populated on the COM Express modulewith 1GB DDR2 soldered down memory and a carrier board with theIntel Platform Controller Hub EG20T, other system components andperipheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.endchoice
config RAMBASE @@ -310,8 +319,12 @@ endmenu
source "arch/x86/cpu/ivybridge/Kconfig"
+source "arch/x86/cpu/queensbay/Kconfig"
source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/intel/crownbay/Kconfig"
endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 0000000..3441413 --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,75 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +#
+config INTEL_QUEENSBAY
boolselect HAVE_FSPselect HAVE_CMC+if INTEL_QUEENSBAY
+config HAVE_FSP
bool "Add an Firmware Support Package binary"helpSelect this option to add an Firmware Support Package binary tothe resulting U-Boot image. It is a binary blob which U-Boot usesto set up SDRAM and other chipset specific initialization.Note: Without this binary U-Boot will not be able to set up itsSDRAM so will not boot.+config FSP_FILE
string "Firmware Support Package binary path and filename"depends on HAVE_FSPdefault "fsp.bin"helpThe path and filename of the file to use as Firmware Support Packagebinary.+config FSP_LOCATION
hex "Firmware Support Package binary location"depends on HAVE_FSPdefault 0xfffc0000helpFSP is not Pisition Independent Code (PIC) and the whole FSP has to
Position
be rebased if it is placed at a location which is different from theperferred base address specified during the FSP build. Use Intel'sBinary Configuration Tool (BCT) to do the rebase.The default base address of 0xfffc0000 indicates that the binary mustbe located at offset 0xc0000 from the beginning of a 1MB flash device.+config FSP_TEMP_RAM_ADDR
hexdefault 0x2000000
help?
+config HAVE_CMC
bool "Add a Chipset Micro Code state machine binary"helpSelect this option to add a Chipset Micro Code state machine binaryto the resulting U-Boot image. It is a binary blob which must be putin the flash for the processor to access when power up.
powered up
Can you add help about what it does?
+config CMC_FILE
string "Chipset Micro Code state machine binary path and filename"depends on HAVE_CMCdefault "C0_22211.BIN"
Can we use lower case please?
helpThe path and filename of the file to use as Chipset Micro Codestate machine binary.+config CMC_LOCATION
hex "Chipset Micro Code state machine binary location"depends on HAVE_CMCdefault 0xfffb0000helpThe location of the CMC binary is determined by a strap. It must beput in flash at a location matching the strap-determined base address.The default base address of 0xfffb0000 indicates that the binary mustbe located at offset 0xb0000 from the beginning of a 1MB flash device.+endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 0000000..4709f9b --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,20 @@ +if TARGET_CROWNBAY
+config SYS_BOARD
default "crownbay"+config SYS_VENDOR
default "intel"+config SYS_SOC
default "queensbay"+config SYS_CONFIG_NAME
default "crownbay"+config BOARD_SPECIFIC_OPTIONS # dummy
def_bool yselect INTEL_QUEENSBAYselect BOARD_ROMSIZE_KB_1024+endif
1.8.2.1
Regards, Simon
Hi Simon,
On Fri, Dec 5, 2014 at 7:54 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng.cn@gmail.com wrote:
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/Kconfig | 13 ++++++++ arch/x86/cpu/queensbay/Kconfig | 75 ++++++++++++++++++++++++++++++++++++++++++ board/intel/crownbay/Kconfig | 20 +++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb618..ebf72b3 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CROWNBAY
bool "Support Intel Crown Bay CRB"helpThis is the Intel Crown Bay Customer Reference Board. It containsthe Intel Atom Processor E6xx populated on the COM Express modulewith 1GB DDR2 soldered down memory and a carrier board with theIntel Platform Controller Hub EG20T, other system components andperipheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.endchoice
config RAMBASE @@ -310,8 +319,12 @@ endmenu
source "arch/x86/cpu/ivybridge/Kconfig"
+source "arch/x86/cpu/queensbay/Kconfig"
source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/intel/crownbay/Kconfig"
endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 0000000..3441413 --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,75 @@ +# +# Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +#
+config INTEL_QUEENSBAY
boolselect HAVE_FSPselect HAVE_CMC+if INTEL_QUEENSBAY
+config HAVE_FSP
bool "Add an Firmware Support Package binary"helpSelect this option to add an Firmware Support Package binary tothe resulting U-Boot image. It is a binary blob which U-Boot usesto set up SDRAM and other chipset specific initialization.Note: Without this binary U-Boot will not be able to set up itsSDRAM so will not boot.+config FSP_FILE
string "Firmware Support Package binary path and filename"depends on HAVE_FSPdefault "fsp.bin"helpThe path and filename of the file to use as Firmware Support Packagebinary.+config FSP_LOCATION
hex "Firmware Support Package binary location"depends on HAVE_FSPdefault 0xfffc0000helpFSP is not Pisition Independent Code (PIC) and the whole FSP has toPosition
OK.
be rebased if it is placed at a location which is different from theperferred base address specified during the FSP build. Use Intel'sBinary Configuration Tool (BCT) to do the rebase.The default base address of 0xfffc0000 indicates that the binary mustbe located at offset 0xc0000 from the beginning of a 1MB flash device.+config FSP_TEMP_RAM_ADDR
hexdefault 0x2000000help?
OK.
+config HAVE_CMC
bool "Add a Chipset Micro Code state machine binary"helpSelect this option to add a Chipset Micro Code state machine binaryto the resulting U-Boot image. It is a binary blob which must be putin the flash for the processor to access when power up.powered up
Can you add help about what it does?
The datasheet does not mention too much details about CMC, but I will try adding more help about it.
+config CMC_FILE
string "Chipset Micro Code state machine binary path and filename"depends on HAVE_CMCdefault "C0_22211.BIN"Can we use lower case please?
Yes.
[snip]
Regards, Bin
participants (2)
-
Bin Meng -
Simon Glass