[PATCH v2 0/2] qcom: allow msm_gpio to set special pins direction & value
After struct msm_special_pin_data was introduced in [1], use the data to setup the pin direction and/or value if supported by the pin data.
Add the proper msm_special_pin_data for sm8250 after sm8550 and sm8650.
[1] https://lore.kernel.org/all/20240528-topic-sm8x50-pinctrl-pinconf-v1-0-54d1e...
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- Changes in v2: - dropped last line of sm8250_pin_offsets - Link to v1: https://lore.kernel.org/r/20240910-topic-sm8x50-msm-gpio-special-pins-sm8250...
--- Neil Armstrong (2): gpio: msm: add support for special pins pinctr: qcom: sm8250: add special pins pins configuration data
drivers/gpio/msm_gpio.c | 97 ++++++++++++++++++++++++++++++++--- drivers/pinctrl/qcom/pinctrl-sm8250.c | 42 +++++++++++++-- 2 files changed, 127 insertions(+), 12 deletions(-) --- base-commit: ca55cf8104c0dd78aae45fa66dd8400ef1b3d0ac change-id: 20240910-topic-sm8x50-msm-gpio-special-pins-sm8250-943311b483e2
Best regards,
Leverage the data introduced in the struct msm_special_pin_data to allow setting the gpio direction and value if supported by the pin data.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/gpio/msm_gpio.c | 97 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 8 deletions(-)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 2fb266f1285..cea073b3297 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -34,13 +34,31 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4)
+static void msm_gpio_direction_input_special(struct msm_gpio_bank *priv, + unsigned int gpio) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->ctl_reg || data->oe_bit >= 31) + return; + + /* switch direction */ + clrsetbits_le32(priv->base + data->ctl_reg, + BIT(data->oe_bit), 0); +} + static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);
- /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return; + msm_gpio_direction_input_special(priv, gpio);
/* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), @@ -49,13 +67,33 @@ static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) return; }
+static int msm_gpio_set_value_special(struct msm_gpio_bank *priv, + unsigned int gpio, int value) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->out_bit >= 31) + return 0; + + value = !!value; + /* set value */ + writel(value << data->out_bit, priv->base + data->io_reg); + + return 0; +} + static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);
- /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_set_value_special(priv, gpio, value);
value = !!value; /* set value */ @@ -64,14 +102,42 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) return 0; }
+static int msm_gpio_direction_output_special(struct msm_gpio_bank *priv, + unsigned int gpio, + int value) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->out_bit >= 31) + return 0; + + value = !!value; + /* set value */ + writel(value << data->out_bit, priv->base + data->io_reg); + + if (!data->ctl_reg || data->oe_bit >= 31) + return 0; + + /* switch direction */ + clrsetbits_le32(priv->base + data->ctl_reg, + BIT(data->oe_bit), BIT(data->oe_bit)); + + return 0; +} + static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);
- /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_direction_output_special(priv, gpio, value);
value = !!value; /* set value */ @@ -100,13 +166,28 @@ static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flag return 0; }
+static int msm_gpio_get_value_special(struct msm_gpio_bank *priv, unsigned int gpio) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->in_bit >= 31) + return 0; + + return !!(readl(priv->base + data->io_reg) >> data->in_bit); +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);
- /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_get_value_special(priv, gpio);
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); }
Add the special pins configuration data to allow setup the bias of the UFS and SDCard pins on the SM8250 SoC.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/pinctrl/qcom/pinctrl-sm8250.c | 42 +++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index dac24f11bc2..cab42fa64ed 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -18,8 +18,37 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const struct pinctrl_function msm_pinctrl_functions[] = { { "qup12", 1 }, - { "gpio", 0 }, - { "sdc2_clk", 0 } }; + { "gpio", 0 }, }; +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = pg_name, \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data sm8250_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", SOUTH + 0xb8000), + [1] = SDC_PINGROUP("sdc2_clk", NORTH + 0xb7000, 14, 6), + [2] = SDC_PINGROUP("sdc2_cmd", NORTH + 0xb7000, 11, 3), + [3] = SDC_PINGROUP("sdc2_data", NORTH + 0xb7000, 9, 0), +};
static const unsigned int sm8250_pin_offsets[] = { [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH, [4] = NORTH, [5] = NORTH, @@ -52,7 +81,6 @@ static const unsigned int sm8250_pin_offsets[] = { [162] = WEST, [163] = WEST, [164] = WEST, [165] = WEST, [166] = WEST, [167] = WEST, [168] = WEST, [169] = WEST, [170] = WEST, [171] = WEST, [172] = WEST, [173] = WEST, [174] = WEST, [175] = WEST, [176] = WEST, [177] = WEST, [178] = WEST, [179] = WEST, - [180] = 0, [181] = 0, [182] = 0, [183] = 0, };
static const char *sm8250_get_function_name(struct udevice *dev, unsigned int selector) @@ -62,7 +90,12 @@ static const char *sm8250_get_function_name(struct udevice *dev, unsigned int se
static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selector) { - snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + if (selector >= 180 && selector <= 183) + snprintf(pin_name, MAX_PIN_NAME_LEN, + sm8250_special_pins_data[selector - 180].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + return pin_name; }
@@ -76,6 +109,7 @@ static struct msm_pinctrl_data sm8250_data = { .pin_offsets = sm8250_pin_offsets, .pin_count = ARRAY_SIZE(sm8250_pin_offsets), .special_pins_start = 180, + .special_pins_data = sm8250_special_pins_data, }, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = sm8250_get_function_name,
Hi Neil,
On 11/09/2024 20:07, Neil Armstrong wrote:
After struct msm_special_pin_data was introduced in [1], use the data to setup the pin direction and/or value if supported by the pin data.
Add the proper msm_special_pin_data for sm8250 after sm8550 and sm8650.
[1] https://lore.kernel.org/all/20240528-topic-sm8x50-pinctrl-pinconf-v1-0-54d1e...
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org
Thanks for this!
Reviewed-by: Caleb Connolly caleb.connolly@linaro.org
Kind regards,
Changes in v2:
- dropped last line of sm8250_pin_offsets
- Link to v1: https://lore.kernel.org/r/20240910-topic-sm8x50-msm-gpio-special-pins-sm8250...
Neil Armstrong (2): gpio: msm: add support for special pins pinctr: qcom: sm8250: add special pins pins configuration data
drivers/gpio/msm_gpio.c | 97 ++++++++++++++++++++++++++++++++--- drivers/pinctrl/qcom/pinctrl-sm8250.c | 42 +++++++++++++-- 2 files changed, 127 insertions(+), 12 deletions(-)
base-commit: ca55cf8104c0dd78aae45fa66dd8400ef1b3d0ac change-id: 20240910-topic-sm8x50-msm-gpio-special-pins-sm8250-943311b483e2
Best regards,
On Wed, 11 Sep 2024 20:07:13 +0200, Neil Armstrong wrote:
After struct msm_special_pin_data was introduced in [1], use the data to setup the pin direction and/or value if supported by the pin data.
Add the proper msm_special_pin_data for sm8250 after sm8550 and sm8650.
[1] https://lore.kernel.org/all/20240528-topic-sm8x50-pinctrl-pinconf-v1-0-54d1e...
[...]
Applied, thanks!
[1/2] gpio: msm: add support for special pins https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/5fe73d1e... [2/2] pinctr: qcom: sm8250: add special pins pins configuration data https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/43a6e47a...
Best regards,
participants (2)
-
Caleb Connolly -
Neil Armstrong