[U-Boot] [[PATCH v2] 0/8] sunxi: Enable OTG peripheral and host mode on H3
Changes vs V1: - Add two patches from Chen-Yu to enable host mode - split USB0 base address change to separate patch - revise OTG clock enabling patch
Chen-Yu Tsai (2): sunxi: Fix USB PHY index for H3/H5/A64 sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64
Jun Nie (6): sunxi: h3: Sync OTG and HCI nodes from Linux DT sunxi: musb: Add fifo config for H3 sunxi: musb: Hack dynamic fifo support for H3 OTG sunxi: musb: Enable OTG device clock for H3 sunxi: usb_phy: Clear PHYCTL register before writing sunxi: H3: set different otg base address per mode
arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 31 +++++++++++----------- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 +++ arch/arm/mach-sunxi/usb_phy.c | 15 +++++++++-- drivers/usb/host/ehci-sunxi.c | 9 ++++++- drivers/usb/host/ohci-sunxi.c | 9 ++++++- drivers/usb/musb-new/musb_regs.h | 3 ++- drivers/usb/musb-new/sunxi.c | 38 ++++++++++++++++++++++++++- 8 files changed, 119 insertions(+), 22 deletions(-)
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller.
Signed-off-by: Jun Nie jun.nie@linaro.org --- arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa6079..d9728a7 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -218,6 +218,19 @@ #size-cells = <0>; };
+ usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, @@ -250,6 +263,25 @@ #phy-cells = <1>; };
+ ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + ehci1: usb@01c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>;
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie jun.nie@linaro.org wrote:
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller.
Signed-off-by: Jun Nie jun.nie@linaro.org
Reviewed-by: Jagan Teki jagan@openedev.com
Add fifo config for H3 as H3 differ with other SoC on ep number.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com --- drivers/usb/musb-new/sunxi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 7ee44ea..0005c1e 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -290,10 +290,42 @@ static const struct musb_platform_ops sunxi_musb_ops = { .disable = sunxi_musb_disable, };
+#if defined(CONFIG_MACH_SUN8I_H3) +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = { + { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +}; +#else +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = { + { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, + { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, + { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +}; +#endif + static struct musb_hdrc_config musb_config = { + .fifo_cfg = sunxi_musb_fifo_config, + .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_fifo_config), .multipoint = 1, .dyn_fifo = 1, +#if defined(CONFIG_MACH_SUN8I_H3) .num_eps = 6, +#else + .num_eps = 5, +#endif .ram_bits = 11, };
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie jun.nie@linaro.org wrote:
Add fifo config for H3 as H3 differ with other SoC on ep number.
Signed-off-by: Jun Nie jun.nie@linaro.org Reviewed-by: Jagan Teki jagan@openedev.com
drivers/usb/musb-new/sunxi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 7ee44ea..0005c1e 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -290,10 +290,42 @@ static const struct musb_platform_ops sunxi_musb_ops = { .disable = sunxi_musb_disable, };
+#if defined(CONFIG_MACH_SUN8I_H3) +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },+}; +#else +static struct musb_fifo_cfg sunxi_musb_fifo_config[] = {
{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },+}; +#endif
static struct musb_hdrc_config musb_config = {
.fifo_cfg = sunxi_musb_fifo_config,.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_fifo_config), .multipoint = 1, .dyn_fifo = 1,+#if defined(CONFIG_MACH_SUN8I_H3) .num_eps = 6, +#else
.num_eps = 5,+#endif
This is incorrect, H3 has 5 ep's and rest have 6
From: Chen-Yu Tsai wens@csie.org
On the new chips such as H3, H5, and A64, the USB OTG controller is paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, the USB PHY index count has to be reworked to start from this pair.
This patch reworks the USB clock gate and reset indices, and how the USB host is mapped to a USB phy, for the newer chips.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +++++++++++++-------------- drivers/usb/host/ehci-sunxi.c | 9 +++++++- drivers/usb/host/ohci-sunxi.c | 9 +++++++- 3 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d328df9..2c82d0a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -270,17 +270,18 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */ +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 -#define AHB_GATE_OFFSET_USB_EHCI0 25 -#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif @@ -339,13 +340,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 6ecb7c4..f40228e 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev) #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have EHCI with OTG */ +#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 133774f..4b8a403 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; priv->usb_gate_mask <<= priv->phy_index; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have OHCI with OTG */ +#endif
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask);
Like other Allwinner SoC, the H3 is missing the config register from the musb hardware block. Use a known working value for it like other SoC.
Signed-off-by: Jun Nie jun.nie@linaro.org --- drivers/usb/musb-new/musb_regs.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index a3cc38e..8a357ed 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -432,7 +432,8 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
static inline u8 musb_read_configdata(void __iomem *mbase) { -#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T +#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN8I_A83T) || \ + defined(CONFIG_MACH_SUNXI_H3_H5) /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde; #else
Enable OTG clock and deassert reset
Signed-off-by: Jun Nie jun.nie@linaro.org --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + drivers/usb/musb-new/sunxi.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 2c82d0a..624d624 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -279,6 +279,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI2 26 #define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 0005c1e..ce7365b 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -264,7 +264,10 @@ static int sunxi_musb_init(struct musb *musb)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0); #ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_OTG_DEVICE)); + setbits_le32(&ccm->ahb_reset0_cfg, + BIT(AHB_GATE_OFFSET_USB0) | + BIT(AHB_GATE_OFFSET_OTG_DEVICE)); #endif sunxi_usb_phy_init(0);
@@ -376,6 +379,7 @@ static int musb_usb_remove(struct udevice *dev) sunxi_usb_phy_exit(0); #ifdef CONFIG_SUNXI_GEN_SUN6I clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_OTG_DEVICE); #endif clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie jun.nie@linaro.org wrote:
Enable OTG clock and deassert reset
Signed-off-by: Jun Nie jun.nie@linaro.org
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + drivers/usb/musb-new/sunxi.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 2c82d0a..624d624 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -279,6 +279,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI2 26 #define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 0005c1e..ce7365b 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -264,7 +264,10 @@ static int sunxi_musb_init(struct musb *musb)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_OTG_DEVICE));setbits_le32(&ccm->ahb_reset0_cfg,BIT(AHB_GATE_OFFSET_USB0) |BIT(AHB_GATE_OFFSET_OTG_DEVICE));
This can certainly failed for other sun6i, because of no AHB_GATE_OFFSET_OTG_DEVICE
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jun Nie jun.nie@linaro.org --- arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..bcf5f15 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5 - if (phy->id == 0) + if (phy->id == 0) { +#ifdef CONFIG_USB_MUSB_GADGET + setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR); +#else clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); #endif + } +#endif clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); } #elif defined CONFIG_MACH_SUN8I_A83T
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie jun.nie@linaro.org wrote:
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jun Nie jun.nie@linaro.org
arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..bcf5f15 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5
if (phy->id == 0)
if (phy->id == 0) {+#ifdef CONFIG_USB_MUSB_GADGET
setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR);
This can't dependent on mode.
On Sun, Jan 28, 2018 at 2:43 PM, Jagan Teki jagannadh.teki@gmail.com wrote:
On Fri, Jan 5, 2018 at 9:45 PM, Jun Nie jun.nie@linaro.org wrote:
PHYCTL register offset at 0x10 need to be cleared before it's written. Ported from below Linux patch. d699c1d phy: sun4i-usb: change PHYCTL register clearing code
Signed-off-by: Jun Nie jun.nie@linaro.org
arch/arm/mach-sunxi/usb_phy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 2f1cad1..bcf5f15 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -156,9 +156,15 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { #if defined CONFIG_MACH_SUNXI_H3_H5
if (phy->id == 0)
if (phy->id == 0) {+#ifdef CONFIG_USB_MUSB_GADGET
setbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);writel(0, SUNXI_USB0_BASE + SUNXI_USB_CSR);This can't dependent on mode.
infact clear phyctl was already added in usb_phy_write, you can reuse the same for H3_H5
From: Chen-Yu Tsai wens@csie.org
On newer chips, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/mach-sunxi/usb_phy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index bcf5f15..4ae0a77 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -245,7 +245,12 @@ void sunxi_usb_phy_init(int index)
sunxi_usb_phy_config(phy);
- if (phy->id != 0) + /* + * Later SoCs such as the H3, H5, A64 have proper hosts for OTG. + * As such the passby settings need to be set for them as well. + */ + if (phy->id != 0 || IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5) || + IS_ENABLED(CONFIG_MACH_SUN50I)) sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
#ifdef CONFIG_MACH_SUN8I_A83T
Set different base address per host mode or peripheral mode. Phy configuration also depends on this address.
Signed-off-by: Jun Nie jun.nie@linaro.org --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 2419062..f45f53a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -64,7 +64,11 @@ #ifdef CONFIG_SUNXI_GEN_SUN6I #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 +#ifdef CONFIG_USB_MUSB_GADGET +#define SUNXI_USB0_BASE 0x01c19000 +#else #define SUNXI_USB0_BASE 0x01c1a000 +#endif #define SUNXI_USB1_BASE 0x01c1b000 #define SUNXI_USB2_BASE 0x01c1c000 #define SUNXI_USB3_BASE 0x01c1d000
participants (2)
-
Jagan Teki -
Jun Nie