From: Andreas Dannenberg dannenberg@ti.com

This is not really a new board but rather a minimal bootloader solution for the AM437x GP EVM. In terms of interfaces, it only supports booting from MMC0 or UART0 and only activates a minimal set of drivers that are that are necessary to run the device such as DDR, I2C, and PMIC.

The goal is to provide a bare minimum starting point to boot Linux for basing custom board-ports on. The limited complexity of this solution should make it easier to achieve a successful boot to U-Boot prompt vs. trying to pair down the full-featured multi-platform AM437x U-Boot available through am43xx_evm_defconfig.

Signed-off-by: Andreas Dannenberg dannenberg@ti.com [Amjad: fix compile and checkpatch warnings] Signed-off-by: Amjad Ouled-Ameur aouledameur@baylibre.com

--- Tests: - This has been tested on AM43xx platform, the board boots successfully to u-boot prompt and runs basic commands seamlessly, please find the logs here: [0] However, regarding the kernel boot test, sometimes it does boot correctly, sometimes it does not, but this patch does not actually guaranteey that since its purpose is to mainly allow the user to achieve a successful boot to U-boot prompt.

[0]: https://pastebin.com/zmCsjQRT

MAINTAINERS | 4 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/am437x-gp-evm-mini.dts | 171 ++++++++++ arch/arm/mach-omap2/am33xx/Kconfig | 22 ++ board/ti/am43xx/Kconfig | 13 +- board/ti/am43xx/Makefile | 6 +- board/ti/am43xx/board_hs_mini.h | 27 ++ board/ti/am43xx/board_mini.c | 452 +++++++++++++++++++++++++++ board/ti/am43xx/board_mini.h | 28 ++ board/ti/am43xx/mux_mini.c | 53 ++++ configs/am43xx_evm_mini_defconfig | 39 +++ configs/am43xx_hs_evm_mini_defconfig | 47 +++ include/configs/am43xx_evm_mini.h | 120 +++++++ 13 files changed, 983 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/am437x-gp-evm-mini.dts create mode 100644 board/ti/am43xx/board_hs_mini.h create mode 100644 board/ti/am43xx/board_mini.c create mode 100644 board/ti/am43xx/board_mini.h create mode 100644 board/ti/am43xx/mux_mini.c create mode 100644 configs/am43xx_evm_mini_defconfig create mode 100644 configs/am43xx_hs_evm_mini_defconfig create mode 100644 include/configs/am43xx_evm_mini.h

diff --git a/MAINTAINERS b/MAINTAINERS index 5370b550648e..0159be0e4673 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -492,6 +492,7 @@ F: arch/arm/mach-keystone/ F: arch/arm/mach-omap2/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ +F: arch/arm/dts/am437x* F: board/ti/ F: drivers/dma/ti* F: drivers/firmware/ti_sci.* @@ -518,6 +519,7 @@ F: drivers/timer/omap-timer.c F: drivers/watchdog/omap_wdt.c F: include/linux/pruss_driver.h F: include/linux/soc/ti/ +F: include/configs/am43xx_evm_mini.h

ARM U8500 M: Stephan Gerhold stephan@gerhold.net @@ -1134,6 +1136,8 @@ F: arch/arm/mach-k3/config_secure.mk F: configs/am335x_hs_evm_defconfig F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig +F: configs/am43xx_evm_mini_defconfig +F: configs/am43xx_hs_evm_mini_defconfig F: configs/am57xx_hs_evm_defconfig F: configs/am57xx_hs_evm_usb_defconfig F: configs/dra7xx_hs_evm_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fc16a57e60b0..3b8c539a6272 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -375,7 +375,10 @@ dtb-$(CONFIG_AM33XX) += \ am335x-guardian.dtb \ am335x-wega-rdk.dtb \ am335x-regor-rdk.dtb -dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ +dtb-$(CONFIG_AM43XX) += \ + am437x-gp-evm.dtb \ + am437x-gp-evm-mini.dtb \ + am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ am4372-generic.dtb \ diff --git a/arch/arm/dts/am437x-gp-evm-mini.dts b/arch/arm/dts/am437x-gp-evm-mini.dts new file mode 100644 index 000000000000..07c93c47b638 --- /dev/null +++ b/arch/arm/dts/am437x-gp-evm-mini.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* AM437x GP EVM MINI */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "TI AM437x GP EVM MINI"; + compatible = "ti,am437x-gp-evm-mini","ti,am437x-gp-evm","ti,am4372","ti,am43"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + ocp { + u-boot,dm-spl; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&am43xx_pinmux { + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + u-boot,dm-spl; +}; + +&uart0 { + u-boot,dm-spl; +}; + +&i2c0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 4268419b166b..d21d042cf868 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -244,6 +244,28 @@ config TARGET_AM43XX_EVM to write software and develop hardware around an AM43xx processor subsystem.

+config TARGET_AM43XX_EVM_MINI + bool "Support am43xx_evm_mini" + select BOARD_LATE_INIT + imply DM_I2C + imply SPL_ENV_SUPPORT + imply SPL_FS_EXT4 + imply SPL_FS_FAT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SPL_YMODEM_SUPPORT + help + This option specifies support for the AM43xx + GP and HS EVM development platforms using a minimal + system configuration, only supporting a small subset + of boot media and other features. + config TARGET_CM_T43 bool "Support cm_t43"

diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig index 9cb80cc3f1da..533e78cda916 100644 --- a/board/ti/am43xx/Kconfig +++ b/board/ti/am43xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AM43XX_EVM +if TARGET_AM43XX_EVM || TARGET_AM43XX_EVM_MINI

config SYS_BOARD default "am43xx" @@ -9,9 +9,20 @@ config SYS_VENDOR config SYS_SOC default "am33xx"

+if TARGET_AM43XX_EVM + config SYS_CONFIG_NAME default "am43xx_evm"

+endif + +if TARGET_AM43XX_EVM_MINI + +config SYS_CONFIG_NAME + default "am43xx_evm_mini" + +endif + source "board/ti/common/Kconfig"

endif diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index 60a11d8c04d2..b7606c304148 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -5,7 +5,9 @@ # Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/

ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) -obj-y := mux.o +obj-$(CONFIG_TARGET_AM43XX_EVM) := mux.o +obj-$(CONFIG_TARGET_AM43XX_EVM_MINI) := mux_mini.o endif

-obj-y += board.o +obj-$(CONFIG_TARGET_AM43XX_EVM) += board.o +obj-$(CONFIG_TARGET_AM43XX_EVM_MINI) += board_mini.o diff --git a/board/ti/am43xx/board_hs_mini.h b/board/ti/am43xx/board_hs_mini.h new file mode 100644 index 000000000000..3804bfc81d54 --- /dev/null +++ b/board/ti/am43xx/board_hs_mini.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_HS_H_ +#define _BOARD_HS_H_ + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(const void *fit, int node, + void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} + +void board_tee_image_process(ulong tee_image, size_t tee_size) +{ + secure_tee_install((u32)tee_image); +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); +#endif + +#endif diff --git a/board/ti/am43xx/board_mini.c b/board/ti/am43xx/board_mini.c new file mode 100644 index 000000000000..7560274be088 --- /dev/null +++ b/board/ti/am43xx/board_mini.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Mini board functions for TI AM43XX based boards + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <eeprom.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <linux/errno.h> +#include <spl.h> +#include <usb.h> +#include <fdt_support.h> +#include <image.h> +#include <asm/omap_sec_common.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/gpio.h> +#include <asm/emif.h> +#include <asm/omap_common.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board_mini.h" +#include "board_hs_mini.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ + {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params gp_evm_dpll_ddr = { + 50, 2, 1, -1, 2, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0xc163, +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x00048008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + if (!IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return &gp_evm_dpll_ddr; + return NULL; +} + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp, offset, i; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return 0; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp; + u32 ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + ind = get_sys_clk_index(); + + return &dpll_per[ind]; +} + +void scale_vcores_generic(u32 m) +{ + int mpu_vdd, ddr_volt; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + if (IS_ENABLED(CONFIG_DM_I2C)) { + if (power_tps65218_init(0)) + return; + } else { + if (i2c_probe(TPS65218_CHIP_PM)) + return; + } + + switch (m) { + case 1000: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + printf("%s failure\n", __func__); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } + + ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV; + + /* Set DCDC3 (DDR) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) { + printf("%s failure\n", __func__); + return; + } +} + +void gpi2c_init(void) +{ + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + if (first_time) { + enable_i2c0_pin_mux(); + + if (!IS_ENABLED(CONFIG_DM_I2C)) + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + + first_time = false; + } +} + +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* Ensure I2C is initialized for PMIC configuration */ + gpi2c_init(); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + scale_vcores_generic(mpu_params->m); +} + +void set_uart_mux_conf(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + enable_board_pin_mux(); +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO5_7 */ + writel(GPIO_SETDATAOUT(7), + AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +void sdram_init(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* GP EVM has 1GB DDR3 connected to EMIF along with VTT regulator */ + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400mhz_production, 0); +} + +/* setup board specific PMIC */ +int power_init_board(void) +{ + int rc; + struct pmic *p = NULL; + + rc = power_tps65218_init(0); + if (rc) + goto done; + + if (!IS_ENABLED(CONFIG_DM_I2C)) { + p = pmic_get("TPS65218_PMIC"); + if (!p || pmic_probe(p)) + goto done; + } + + puts("PMIC: TPS65218\n"); + +done: + return 0; +} + +int board_init(void) +{ + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + /* + * Call this to initialize *ctrl again + */ + hw_data_init(); + + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwidth for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_BOARD_LATE_INIT) && + IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", CONFIG_SYS_BOARD); + + /* + * Default FIT boot on HS devices. Non FIT images are not allowed + * on HS devices. + */ + if (get_device_type() == HS_DEVICE) + env_set("boot_fit", "1"); + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + if (IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)) + ft_cpu_setup(blob, bd); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +int embedded_dtb_select(void) +{ + if (IS_ENABLED(CONFIG_DTB_RESELECT)) + do_board_detect(); + + return 0; +} diff --git a/board/ti/am43xx/board_mini.h b/board/ti/am43xx/board_mini.h new file mode 100644 index 000000000000..927057465cac --- /dev/null +++ b/board/ti/am43xx/board_mini.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include <asm/arch/omap.h> + +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); + +#ifdef CONFIG_DM_I2C +#define pmic_get(name) (NULL) +#define pmic_probe(p) (NULL) +#define i2c_init(speed, slaveaddr) +#define i2c_probe(chip) (NULL) +#endif + +#endif diff --git a/board/ti/am43xx/mux_mini.c b/board/ti/am43xx/mux_mini.c new file mode 100644 index 000000000000..1230248e3b29 --- /dev/null +++ b/board/ti/am43xx/mux_mini.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board_mini.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux gpio5_7_pin_mux[] = { + {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(gpio5_7_pin_mux); /* DDR VTT Enable */ +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} diff --git a/configs/am43xx_evm_mini_defconfig b/configs/am43xx_evm_mini_defconfig new file mode 100644 index 000000000000..451118cc2a21 --- /dev/null +++ b/configs/am43xx_evm_mini_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm-mini" +CONFIG_AM43XX=y +CONFIG_TARGET_AM43XX_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_MISC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SERIAL=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/am43xx_hs_evm_mini_defconfig b/configs/am43xx_hs_evm_mini_defconfig new file mode 100644 index 000000000000..97582c4d1b23 --- /dev/null +++ b/configs/am43xx_hs_evm_mini_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_ISW_ENTRY_ADDR=0x403018e0 +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm-mini" +CONFIG_AM43XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_TARGET_AM43XX_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_MISC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SERIAL=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/include/configs/am43xx_evm_mini.h b/include/configs/am43xx_evm_mini.h new file mode 100644 index 000000000000..3f7c3e7c7fba --- /dev/null +++ b/include/configs/am43xx_evm_mini.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_AM43XX_EVM_MINI_H +#define __CONFIG_AM43XX_EVM_MINI_H + +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include <asm/arch/omap.h> + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_SERIAL +#endif + +/* I2C Configuration */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Power */ +#ifndef CONFIG_DM_I2C +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif +#define CONFIG_POWER_TPS65218 + +/* SPL defines. */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ + +/* Now bring in the rest of the common code. */ +#include <configs/ti_armv7_omap.h> + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_TIMER +#endif + +#ifndef CONFIG_SPL_BUILD +#include <environment/ti/mmc.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyS0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "default_device_tree=am437x-gp-evm.dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" + +#define CONFIG_BOOTCOMMAND \ + "if test ${boot_fit} -eq 1; then " \ + "run update_to_fit;" \ + "fi;" \ + "run findfdt;" \ + "run envboot;" \ + "run mmcboot;" + +#endif + +#if defined(CONFIG_TI_SECURE_DEVICE) +/* Avoid relocating onto firewalled area at end of DRAM */ +#define CONFIG_PRAM (64 * 1024) +#endif /* CONFIG_TI_SECURE_DEVICE */ + +#endif /* __CONFIG_AM43XX_EVM_MINI_H */