[U-Boot] [PATCH v2 0/6] rockchip: rk3368: remove secure timer usage and use DM timer
Although this was originally inteded as a RFC to test out a concept, it's not become the tail-end of the RK3368 SPL/TPL enablement series. So here's v2 with everyone's requests integrated.
Trying to answer Simon's question whether the address of the secure timer (for initialising stimer1 and starting up the ARMv8 generic timer) can be obtained from the DTS, here's a series that tries to give an answer.
To summarise this answer in plain English: - The answer to the original question is: "no, but..." - The "but" is what's implemented here: we don't need the ARMv8 generic timer ticking in U-Boot, so we won't have to initialise it at all (this removing the need to obtain the address for stimer1). - We also have a "however": the size of the TPL binary increases by approx. 800 bytes (AArch64 code), as we need the DM timer support.
This series is based on-top-of my RK3368 enablement series and will remove the secure timer initialisation.
Support for the Rk3399 should be added in the next iteration.
Changes in v2: - marks blob as maybe_unused (to accomodate the OF_CONTROL case w/o warnings) - remove the DEBUG (missed this initially, as there were no debug() calls in the file anyway) - rework the reload_value code for improved readability - pull the uc_priv->clock_rate init into the OF_PLATDATA block - add 'clock-frequency' prop to timer in the -u-boot.dtsi
Philipp Tomsich (6): timer: add OF_PLATDATA support for timer-uclass dm: timer: normalise SPL and TPL support rockchip: timer: add device-model timer driver for RK3368 (and similar) dts: rk3368: make timer0 accessible for SPL and TPL rockchip: lion-rk3368: defconfig: enable DM timer for all stages rockchip: rk3368: remove setup of secure timer from TPL/SPL
arch/arm/cpu/armv8/Makefile | 2 + arch/arm/dts/rk3368-lion-u-boot.dtsi | 5 ++ arch/arm/dts/rk3368.dtsi | 2 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 20 ------ arch/arm/mach-rockchip/rk3368-board-tpl.c | 19 ------ common/spl/Kconfig | 8 --- configs/chromebook_link64_defconfig | 2 +- configs/lion-rk3368_defconfig | 4 ++ configs/qemu-x86_64_defconfig | 2 +- drivers/Makefile | 3 +- drivers/timer/Kconfig | 25 +++++++ drivers/timer/Makefile | 3 +- drivers/timer/rockchip_timer.c | 107 ++++++++++++++++++++++++++++++ drivers/timer/timer-uclass.c | 8 ++- 14 files changed, 155 insertions(+), 55 deletions(-) create mode 100644 drivers/timer/rockchip_timer.c
The timer-uclass depends on full OF_CONTROL through its interrogation of /chosen and the code to determine the clock-frequency.
For the OF_PLATDATA case, these code-paths are disabled and it becomes the timer driver's responsibility to correctly set the clock-frequency in the uclass priv-data.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v2: - marks blob as maybe_unused (to accomodate the OF_CONTROL case w/o warnings)
drivers/timer/timer-uclass.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index ec10b28..a84755f 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -42,6 +42,7 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
static int timer_pre_probe(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct clk timer_clk; int err; @@ -56,6 +57,7 @@ static int timer_pre_probe(struct udevice *dev) } else uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock-frequency", 0); +#endif
return 0; } @@ -81,16 +83,18 @@ u64 timer_conv_64(u32 count)
int notrace dm_timer_init(void) { - const void *blob = gd->fdt_blob; + __maybe_unused const void *blob = gd->fdt_blob; struct udevice *dev = NULL; - int node; + int node = -ENOENT; int ret;
if (gd->timer) return 0;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA) /* Check for a chosen timer to be used for tick */ node = fdtdec_get_chosen_node(blob, "tick-timer"); +#endif if (node < 0) { /* No chosen timer, trying first available timer */ ret = uclass_first_device_err(UCLASS_TIMER, &dev);
The timer-uclass depends on full OF_CONTROL through its interrogation of /chosen and the code to determine the clock-frequency.
For the OF_PLATDATA case, these code-paths are disabled and it becomes the timer driver's responsibility to correctly set the clock-frequency in the uclass priv-data.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2:
- marks blob as maybe_unused (to accomodate the OF_CONTROL case w/o warnings)
drivers/timer/timer-uclass.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Applied to u-boot-rockchip, thanks!
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 2 ++ common/spl/Kconfig | 8 -------- configs/chromebook_link64_defconfig | 2 +- configs/qemu-x86_64_defconfig | 2 +- drivers/Makefile | 3 +-- drivers/timer/Kconfig | 18 ++++++++++++++++++ drivers/timer/Makefile | 2 +- 7 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index c447085..1249547 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -8,7 +8,9 @@ extra-y := start.o
obj-y += cpu.o +ifndef CONFIG_$(SPL_TPL_)TIMER obj-y += generic_timer.o +endif obj-y += cache_v8.o obj-y += exceptions.o obj-y += cache.o diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 08013b7..1386760 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -602,14 +602,6 @@ config SPL_SPI_SUPPORT enable SPI drivers that are needed for other purposes also, such as a SPI PMIC.
-config SPL_TIMER_SUPPORT - bool "Support timer drivers" - help - Enable support for timer drivers in SPL. These can be used to get - a timer value when in SPL, or perhaps for implementing a delay - function. This enables the drivers in drivers/timer as part of an - SPL build. - config SPL_USB_HOST_SUPPORT bool "Support USB host drivers" help diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 11ceb76..5cf409c 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_PCI_SUPPORT=y CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y -CONFIG_SPL_TIMER_SUPPORT=y +CONFIG_SPL_TIMER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index fc1c70d..9517001 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_PCI_SUPPORT=y CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y -CONFIG_SPL_TIMER_SUPPORT=y +CONFIG_SPL_TIMER=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set diff --git a/drivers/Makefile b/drivers/Makefile index b98550e..9d4680a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ +obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD @@ -38,7 +39,6 @@ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ -obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/ @@ -82,7 +82,6 @@ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ obj-y += sysreset/ -obj-y += timer/ obj-y += tpm/ obj-y += video/ obj-y += watchdog/ diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 17e7dfe..fb5af4d 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -9,6 +9,24 @@ config TIMER will be used. The timer is usually a 32 bits free-running up counter. There may be no real tick, and no timer interrupt.
+config SPL_TIMER + bool "Enable driver model for timer drivers in SPL" + depends on TIMER && SPL + help + Enable support for timer drivers in SPL. These can be used to get + a timer value when in SPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + SPL build. + +config TPL_TIMER + bool "Enable driver model for timer drivers in TPL" + depends on TIMER && TPL + help + Enable support for timer drivers in TPL. These can be used to get + a timer value when in TPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + TPL build. + config TIMER_EARLY bool "Allow timer to be used early in U-Boot" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index ced7bd6..d16ea53 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-$(CONFIG_TIMER) += timer-uclass.o +obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 2 ++ common/spl/Kconfig | 8 -------- configs/chromebook_link64_defconfig | 2 +- configs/qemu-x86_64_defconfig | 2 +- drivers/Makefile | 3 +-- drivers/timer/Kconfig | 18 ++++++++++++++++++ drivers/timer/Makefile | 2 +- 7 files changed, 24 insertions(+), 13 deletions(-)
Applied to u-boot-rockchip, thanks!
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v2: - remove the DEBUG (missed this initially, as there were no debug() calls in the file anyway) - rework the reload_value code for improved readability - pull the uc_priv->clock_rate init into the OF_PLATDATA block
drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/rockchip_timer.c | 107 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/timer/rockchip_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index fb5af4d..151a699 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -104,4 +104,11 @@ config AE3XX_TIMER help Select this to enable a timer for AE3XX devices.
+config ROCKCHIP_TIMER + bool "Rockchip timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Rockchip devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index d16ea53..fa7ce7c 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o +obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c new file mode 100644 index 0000000..0848033 --- /dev/null +++ b/drivers/timer/rockchip_timer.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <mapmem.h> +#include <asm/arch/timer.h> +#include <dt-structs.h> +#include <timer.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct rockchip_timer_plat { + struct dtd_rockchip_rk3368_timer dtd; +}; +#endif + +/* Driver private data. Contains timer id. Could be either 0 or 1. */ +struct rockchip_timer_priv { + struct rk_timer *timer; +}; + +static int rockchip_timer_get_count(struct udevice *dev, u64 *count) +{ + struct rockchip_timer_priv *priv = dev_get_priv(dev); + uint64_t timebase_h, timebase_l; + uint64_t cntr; + + timebase_l = readl(&priv->timer->timer_curr_value0); + timebase_h = readl(&priv->timer->timer_curr_value1); + + /* timers are down-counting */ + cntr = timebase_h << 32 | timebase_l; + *count = ~0ull - cntr; + return 0; +} + +static int rockchip_clk_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_timer_priv *priv = dev_get_priv(dev); + + priv->timer = (struct rk_timer *)devfdt_get_addr(dev); +#endif + + return 0; +} + +static int rockchip_timer_start(struct udevice *dev) +{ + struct rockchip_timer_priv *priv = dev_get_priv(dev); + const uint64_t reload_val = ~0uLL; + const uint32_t reload_val_l = reload_val & 0xffffffff; + const uint32_t reload_val_h = reload_val >> 32; + + /* disable timer and reset all control */ + writel(0, &priv->timer->timer_ctrl_reg); + /* write reload value */ + writel(reload_val_l, &priv->timer->timer_load_count0); + writel(reload_val_h, &priv->timer->timer_load_count1); + /* enable timer */ + writel(1, &priv->timer->timer_ctrl_reg); + + return 0; +} + +static int rockchip_timer_probe(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct rockchip_timer_priv *priv = dev_get_priv(dev); + struct rockchip_timer_plat *plat = dev_get_platdata(dev); + + priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); + uc_priv->clock_rate = plat->dtd.clock_frequency; +#endif + + return rockchip_timer_start(dev); +} + +static const struct timer_ops rockchip_timer_ops = { + .get_count = rockchip_timer_get_count, +}; + +static const struct udevice_id rockchip_timer_ids[] = { + { .compatible = "rockchip,rk3368-timer" }, + {} +}; + +U_BOOT_DRIVER(arc_timer) = { + .name = "rockchip_rk3368_timer", + .id = UCLASS_TIMER, + .of_match = rockchip_timer_ids, + .probe = rockchip_timer_probe, + .ops = &rockchip_timer_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv), +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat), +#endif + .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata, +};
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2:
- remove the DEBUG (missed this initially, as there were no debug() calls in the file anyway)
- rework the reload_value code for improved readability
- pull the uc_priv->clock_rate init into the OF_PLATDATA block
drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/rockchip_timer.c | 107 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/timer/rockchip_timer.c
Applied to u-boot-rockchip, thanks!
To use it with the DM timer driver in SPL and TPL, timer0 needs to be marked as pre-reloc.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v2: - add 'clock-frequency' prop to timer in the -u-boot.dtsi
arch/arm/dts/rk3368-lion-u-boot.dtsi | 5 +++++ arch/arm/dts/rk3368.dtsi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi index 2053fb1..6052e8a 100644 --- a/arch/arm/dts/rk3368-lion-u-boot.dtsi +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi @@ -85,4 +85,9 @@ }; };
+&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; +
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 22fb7e7..b4f4f61 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -687,7 +687,7 @@ status = "disabled"; };
- timer@ff810000 { + timer0: timer@ff810000 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
To use it with the DM timer driver in SPL and TPL, timer0 needs to be marked as pre-reloc.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2:
- add 'clock-frequency' prop to timer in the -u-boot.dtsi
arch/arm/dts/rk3368-lion-u-boot.dtsi | 5 +++++ arch/arm/dts/rk3368.dtsi | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-)
Applied to u-boot-rockchip, thanks!
There is no reasonably robust way (this will be needed so early that diagnostics will be limited) to specify the base-address of the secure timer through the DTS for TPL and SPL. In order to allow us a cleaner way to structure our SPL and TPL stage, we now move to a DM timer driver.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/lion-rk3368_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 92058b3..f37bac1 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -85,6 +85,10 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_TPL_TIMER=y +CONFIG_ROCKCHIP_TIMER=y CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y CONFIG_LZO=y
There is no reasonably robust way (this will be needed so early that diagnostics will be limited) to specify the base-address of the secure timer through the DTS for TPL and SPL. In order to allow us a cleaner way to structure our SPL and TPL stage, we now move to a DM timer driver.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2: None
configs/lion-rk3368_defconfig | 4 ++++ 1 file changed, 4 insertions(+)
Applied to u-boot-rockchip, thanks!
When using DM timers w/ the timer0 block within the RK3368, we no longer depend on the ARMv8 generic timer counting. This allows us to drop the secure timer initialisation from the TPL and SPL stages.
The secure timer will later be set up by ATF, which starts the ARMv8 generic timer. Thus, there will be a dependency from Linux to the ATF through the ARMv8 generic timer... this seems reasonable, as Linux will require the ATF (and PSCI) to start up the secondary cores anyway (in other words: we don't add any new dependencies).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v2: None
arch/arm/mach-rockchip/rk3368-board-spl.c | 20 -------------------- arch/arm/mach-rockchip/rk3368-board-tpl.c | 19 ------------------- 2 files changed, 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index 691db41..cabf344 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -19,23 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* - * The ARMv8 generic timer uses the STIMER1 as its clock-source. - * Set up the STIMER1 to free-running (i.e. auto-reload) to start - * the generic timer counting (if we don't do this, udelay will not - * work and block indefinitively). - */ -static void secure_timer_init(void) -{ - struct rk_timer * const stimer1 = - (struct rk_timer * const)0xff830020; - const u32 TIMER_EN = BIT(0); - - writel(~0u, &stimer1->timer_load_count0); - writel(~0u, &stimer1->timer_load_count1); - writel(TIMER_EN, &stimer1->timer_ctrl_reg); -} - void board_debug_uart_init(void) { } @@ -52,9 +35,6 @@ void board_init_f(ulong dummy) hang(); }
- /* Make sure the ARMv8 generic timer counts */ - secure_timer_init(); - /* Set up our preloader console */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index 2a91007..c610cfc 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -21,23 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* - * The ARMv8 generic timer uses the STIMER1 as its clock-source. - * Set up the STIMER1 to free-running (i.e. auto-reload) to start - * the generic timer counting (if we don't do this, udelay will not - * work and block indefinitively). - */ -static void secure_timer_init(void) -{ - struct rk_timer * const stimer1 = - (struct rk_timer * const)0xff830020; - const u32 TIMER_EN = BIT(0); - - writel(~0u, &stimer1->timer_load_count0); - writel(~0u, &stimer1->timer_load_count1); - writel(TIMER_EN, &stimer1->timer_ctrl_reg); -} - -/* * The SPL (and also the full U-Boot stage on the RK3368) will run in * secure mode (i.e. EL3) and an ATF will eventually be booted before * starting up the operating system... so we can initialize the SGRF @@ -153,8 +136,6 @@ void board_init_f(ulong dummy) hang(); }
- /* Make sure the ARMv8 generic timer counts */ - secure_timer_init(); /* Reset security, so we can use DMA in the MMC drivers */ sgrf_init();
When using DM timers w/ the timer0 block within the RK3368, we no longer depend on the ARMv8 generic timer counting. This allows us to drop the secure timer initialisation from the TPL and SPL stages.
The secure timer will later be set up by ATF, which starts the ARMv8 generic timer. Thus, there will be a dependency from Linux to the ATF through the ARMv8 generic timer... this seems reasonable, as Linux will require the ATF (and PSCI) to start up the secondary cores anyway (in other words: we don't add any new dependencies).
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/arm/mach-rockchip/rk3368-board-spl.c | 20 -------------------- arch/arm/mach-rockchip/rk3368-board-tpl.c | 19 ------------------- 2 files changed, 39 deletions(-)
Applied to u-boot-rockchip, thanks!
participants (1)
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Philipp Tomsich