On 05/11/2017 11:25 AM, tien.fong.chee@intel.com wrote:

From: Tien Fong Chee tien.fong.chee@intel.com

Remove unused passing parameter of socfpga_bridges_reset function in SoCFPGA Arria10.

The commit message is supposed to explain the purpose of the patch, but there's just no explanation here except for what I can already see in the patch itself.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 7922db8..b6d7f4f 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_assert_fpga_connected_peripherals(void); void socfpga_reset_deassert_osc1wd0(void); void socfpga_reset_uart(int assert); -int socfpga_bridges_reset(int enable); +int socfpga_bridges_reset(void);

struct socfpga_reset_manager { u32 stat; diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index d8c858c..66f1ec2 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void) }

#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { /* For SoCFPGA-VT, this is NOP. */ return 0; } #else -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { int ret;

On Kha, 2017-05-11 at 14:03 +0200, Marek Vasut wrote:

On 05/11/2017 11:25 AM, tien.fong.chee@intel.com wrote:

...

From: Tien Fong Chee tien.fong.chee@intel.com

Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move header files into include/intel_socfpga and FPGA manager driver from arch/arm into driver/fpga/ .

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

arch/arm/mach-socfpga/Makefile                     |   2 +-  arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 ++----  .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---  drivers/Makefile                                   |   1 +  drivers/fpga/Makefile                              |   1 +  drivers/fpga/socfpga.c                             | 243 +------

---

drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  57 +----  7 files changed, 53 insertions(+), 390 deletions(-)  copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)  copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (82%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach- socfpga/Makefile index 41b779c..286bfef 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@    obj-y += board.o  obj-y += clock_manager.o -obj-y += fpga_manager.o  obj-y += misc.o  obj-y += reset_manager.o  obj-y += timer.o @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o  obj-y += scan_manager.o  obj-y += system_manager_gen5.o  obj-y += wrap_pll_config.o +obj-y += fpga_manager.o  endif    ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index a077e22..f259854 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -1,5 +1,5 @@  /*

• • Copyright (C) 2012 Altera Corporation <www.altera.com>

• • Copyright (C) 2012-2017 Altera Corporation <www.altera.com>

* All rights reserved.   *   * SPDX-License-Identifier:    BSD-3-Clause @@ -10,58 +10,9 @@    #include <altera.h>   -struct socfpga_fpga_manager {

• /* FPGA Manager Module */
• u32 stat; /* 0x00 */
• u32 ctrl;
• u32 dclkcnt;
• u32 dclkstat;
• u32 gpo; /* 0x10 */
• u32 gpi;
• u32 misci; /* 0x18 */
• u32 _pad_0x1c_0x82c[517];
• /* Configuration Monitor (MON) Registers */
• u32 gpio_inten; /* 0x830 */
• u32 gpio_intmask;
• u32 gpio_inttype_level;
• u32 gpio_int_polarity;
• u32 gpio_intstatus; /* 0x840 */
• u32 gpio_raw_intstatus;
• u32 _pad_0x848;
• u32 gpio_porta_eoi;
• u32 gpio_ext_porta; /* 0x850 */
• u32 _pad_0x854_0x85c[3];
• u32 gpio_1s_sync; /* 0x860 */
• u32 _pad_0x864_0x868[2];
• u32 gpio_ver_id_code;
• u32 gpio_config_reg2; /* 0x870 */
• u32 gpio_config_reg1;

-};

-#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3

-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6

-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1

-/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/fpga_manager_gen5.h> +#endif    /* FPGA CD Ratio Value */  #define CDRATIO_x1 0x0 @@ -70,8 +21,17 @@ struct socfpga_fpga_manager {  #define CDRATIO_x8 0x3    /* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void);  int fpgamgr_get_mode(void); +int fpgamgr_poll_fpga_ready(void); +void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size);

use size_t for size .

Okay.

...

+int fpgamgr_test_fpga_ready(void);

+#define FPGA_TIMEOUT_CNT 0x1000000

Does that need to be in header file ?

Yeah, gen5 and Arria10 driver need this macro.

...

+#ifndef __ASSEMBLY__

+/* Common prototypes */ +int fpgamgr_dclkcnt_set(unsigned long cnt);   +#endif /* __ASSEMBLY__ */  #endif /* _FPGA_MANAGER_H_ */

[...]

...

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c similarity index 82% copy from drivers/fpga/socfpga.c copy to drivers/fpga/socfpga_gen5.c index f1b2f2c..269e81e 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga_gen5.c @@ -1,5 +1,5 @@  /*

• • Copyright (C) 2012 Altera Corporation <www.altera.com>

• • Copyright (C) 2012-2017 Altera Corporation <www.altera.com>

Removal of code doesn't extend copyright IMO.

Oh....okay, understood. I will revert back.

...

* All rights reserved.   *   * SPDX-License-Identifier: BSD-3-Clause @@ -14,9 +14,6 @@    DECLARE_GLOBAL_DATA_PTR;   -/* Timeout count */ -#define FPGA_TIMEOUT_CNT 0x1000000

static struct socfpga_fpga_manager *fpgamgr_regs =   (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;  static struct socfpga_system_manager *sysmgr_regs = @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)   (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);  }   -static int fpgamgr_dclkcnt_set(unsigned long cnt) -{

• unsigned long i;
• /* Clear any existing done status */
• if (readl(&fpgamgr_regs->dclkstat))

• writel(0x1, &fpgamgr_regs->dclkstat);
  

• /* Write the dclkcnt */
• writel(cnt, &fpgamgr_regs->dclkcnt);
• /* Wait till the dclkcnt done */
• for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {

• if (!readl(&fpgamgr_regs->dclkstat))
  

• 	continue;
  

• writel(0x1, &fpgamgr_regs->dclkstat);
  

• return 0;
  

• }
• return -ETIMEDOUT;

-}

/* Start the FPGA programming by initialize the FPGA Manager */  static int fpgamgr_program_init(void)  { @@ -143,34 +117,6 @@ static int fpgamgr_program_init(void)   return 0;  }   -/* Write the RBF data to FPGA Manager */ -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) -{

• uint32_t src = (uint32_t)rbf_data;
• uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
• /* Number of loops for 32-byte long copying. */
• uint32_t loops32 = rbf_size / 32;
• /* Number of loops for 4-byte long copying + trailing

bytes */

• uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
• asm volatile(

• "1:	ldmia	%0!,	{r0-r7}\n"
  

• "	stmia	%1!,	{r0-r7}\n"
  

• "	sub	%1,	#32\n"
  

• "	subs	%2,	#1\n"
  

• "	bne	1b\n"
  

• "	cmp	%3,	#0\n"
  

• "	beq	3f\n"
  

• "2:	ldr	%2,	[%0],	#4\n
  

"

• "	str	%2,	[%1]\n"
  

• "	subs	%3,	#1\n"
  

• "	bne	2b\n"
  

• "3:	nop\n"
  

• : "+r"(src), "+r"(dst), "+r"(loops32),
  

"+r"(loops4) :

• : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  

"cc"); -}

/* Ensure the FPGA entering config done */  static int fpgamgr_program_poll_cd(void)  { @@ -267,7 +213,6 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)   }     /* Prior programming the FPGA, all bridges need to be shut off */

Drop this bit

Are you means dropping "-"? Ermm... how to drop this as this is generated from git.

...

/* Disable all signals from hps peripheral controller to fpga */   writel(0, &sysmgr_regs->fpgaintfgrp_module);

On Jum, 2017-05-12 at 09:26 +0200, Marek Vasut wrote:

On 05/12/2017 05:45 AM, Chee, Tien Fong wrote:

...

On Kha, 2017-05-11 at 14:03 +0200, Marek Vasut wrote:

...

On 05/11/2017 11:25 AM, tien.fong.chee@intel.com wrote:

...

From: Tien Fong Chee tien.fong.chee@intel.com

Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move header files into include/intel_socfpga and FPGA manager driver from arch/arm into driver/fpga/ .

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

[...]

...

...

...

+int fpgamgr_test_fpga_ready(void);

+#define FPGA_TIMEOUT_CNT 0x1000000

Does that need to be in header file ?

Yeah, gen5 and Arria10 driver need this macro.

Do they share the block of code which uses this macro ? If so, maybe this can be factored out into common code ? Otherwise, wrap this into both drivers, it's not worth to have it here ...

Okay, i will move them into C files.

...

...

...

+#ifndef __ASSEMBLY__

+/* Common prototypes */ +int fpgamgr_dclkcnt_set(unsigned long cnt);   +#endif /* __ASSEMBLY__ */  #endif /* _FPGA_MANAGER_H_ */

[...]

...

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c similarity index 82% copy from drivers/fpga/socfpga.c copy to drivers/fpga/socfpga_gen5.c index f1b2f2c..269e81e 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga_gen5.c @@ -1,5 +1,5 @@  /*

• • Copyright (C) 2012 Altera Corporation <www.altera.com>

• • Copyright (C) 2012-2017 Altera Corporation <www.altera.com>

Removal of code doesn't extend copyright IMO.

Oh....okay, understood. I will revert back.

...

...

* All rights reserved.   *   * SPDX-License-Identifier: BSD-3-Clause @@ -14,9 +14,6 @@    DECLARE_GLOBAL_DATA_PTR;   -/* Timeout count */ -#define FPGA_TIMEOUT_CNT 0x1000000

static struct socfpga_fpga_manager *fpgamgr_regs =   (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;  static struct socfpga_system_manager *sysmgr_regs = @@ -30,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)   (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);  }   -static int fpgamgr_dclkcnt_set(unsigned long cnt) -{

• unsigned long i;
• /* Clear any existing done status */
• if (readl(&fpgamgr_regs->dclkstat))

• writel(0x1, &fpgamgr_regs->dclkstat);
  

• /* Write the dclkcnt */
• writel(cnt, &fpgamgr_regs->dclkcnt);
• /* Wait till the dclkcnt done */
• for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {

• if (!readl(&fpgamgr_regs->dclkstat))
  

• 	continue;
  

• writel(0x1, &fpgamgr_regs->dclkstat);
  

• return 0;
  

• }
• return -ETIMEDOUT;

-}

/* Start the FPGA programming by initialize the FPGA Manager */  static int fpgamgr_program_init(void)  { @@ -143,34 +117,6 @@ static int fpgamgr_program_init(void)   return 0;  }   -/* Write the RBF data to FPGA Manager */ -static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) -{

• uint32_t src = (uint32_t)rbf_data;
• uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
• /* Number of loops for 32-byte long copying. */
• uint32_t loops32 = rbf_size / 32;
• /* Number of loops for 4-byte long copying + trailing

bytes */

• uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
• asm volatile(

• "1:	ldmia	%0!,	{r0-r7}\n"
  

• "	stmia	%1!,	{r0-r7}\n"
  

• "	sub	%1,	#32\n"
  

• "	subs	%2,	#1\n"
  

• "	bne	1b\n"
  

• "	cmp	%3,	#0\n"
  

• "	beq	3f\n"
  

• "2:	ldr	%2,	[%0],	
  

#4\n "

• "	str	%2,	[%1]\n"
  

• "	subs	%3,	#1\n"
  

• "	bne	2b\n"
  

• "3:	nop\n"
  

• : "+r"(src), "+r"(dst), "+r"(loops32),
  

"+r"(loops4) :

• : "r0", "r1", "r2", "r3", "r4", "r5", "r6",
  

"r7", "cc"); -}

/* Ensure the FPGA entering config done */  static int fpgamgr_program_poll_cd(void)  { @@ -267,7 +213,6 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)   }     /* Prior programming the FPGA, all bridges need to be shut off */

Drop this bit

Are you means dropping "-"? Ermm... how to drop this as this is generated from git.

You deleted a line ... re-add it ... it's generated by you, not by git.

Ohh...okay, i will revert it.

...

...

...

/* Disable all signals from hps peripheral controller to fpga */   writel(0, &sysmgr_regs->fpgaintfgrp_module);

On Kha, 2017-05-11 at 14:04 +0200, Marek Vasut wrote:

On 05/11/2017 11:25 AM, tien.fong.chee@intel.com wrote:

...

From: Tien Fong Chee tien.fong.chee@intel.com

Move arch/arm FPGA driver header to include/intel_socfpga which would be shared between arch platform drivers and FPGA drivers.

Doesn't this patchset only add support for arria10 FPGA ? If so, this patch is pointless in the context of this patchset.

Arria10 FPGA header include fpga_manager.h as common header.There are other headers depend on above common header. So that means they are all related to each others. Hence this patch is needed to ensure all related restructure properly before adding Arria10 FPGA driver.

...

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

arch/arm/mach-socfpga/reset_manager_arria10.c |  2 +-  arch/arm/mach-socfpga/reset_manager_gen5.c    |  5 +-  arch/arm/mach-socfpga/system_manager_gen5.c   |  2 +-  drivers/ddr/altera/sdram.c                    |  5 +-  drivers/fpga/socfpga.c                        |  5 +-  drivers/fpga/socfpga_gen5.c                   |  2 +-  include/intel_socfpga/fpga_manager.h          | 37 +++++++++++++++  include/intel_socfpga/fpga_manager_gen5.h     | 68 +++++++++++++++++++++++++++  8 files changed, 116 insertions(+), 10 deletions(-)  create mode 100644 include/intel_socfpga/fpga_manager.h  create mode 100644 include/intel_socfpga/fpga_manager_gen5.h

diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 66f1ec2..bfc375e 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -5,13 +5,13 @@   */    #include <asm/io.h> -#include <asm/arch/fpga_manager.h>  #include <asm/arch/misc.h>  #include <asm/arch/reset_manager.h>  #include <asm/arch/system_manager.h>  #include <common.h>  #include <errno.h>  #include <fdtdec.h> +#include <intel_socfpga/fpga_manager.h>  #include <wait_bit.h>    DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index aa88adb..3d76913 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -1,13 +1,12 @@  /*

• *  Copyright (C) 2013 Altera Corporation <www.altera.com>

• *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>

*   * SPDX-License-Identifier: GPL-2.0+   */

#include <common.h>  #include <asm/io.h> -#include <asm/arch/fpga_manager.h> +#include <intel_socfpga/fpga_manager.h>  #include <asm/arch/reset_manager.h>  #include <asm/arch/system_manager.h>   diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c index 3588a57..a32250b 100644 --- a/arch/arm/mach-socfpga/system_manager_gen5.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -7,7 +7,7 @@  #include <common.h>  #include <asm/io.h>  #include <asm/arch/system_manager.h> -#include <asm/arch/fpga_manager.h> +#include <intel_socfpga/fpga_manager.h>    DECLARE_GLOBAL_DATA_PTR;   diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index e74c5b0..0ff2549 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -1,13 +1,14 @@  /*

• • Copyright Altera Corporation (C) 2014-2015

• • Copyright Altera Corporation (C) 2014-2017

*   * SPDX-License-Identifier: GPL-2.0+   */

#include <common.h>  #include <errno.h>  #include <div64.h>  #include <watchdog.h> -#include <asm/arch/fpga_manager.h> +#include <intel_socfpga/fpga_manager.h>  #include <asm/arch/sdram.h>  #include <asm/arch/system_manager.h>  #include <asm/io.h> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index d3633ea..4c9f238 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -8,7 +8,7 @@  #include <common.h>  #include <asm/io.h>  #include <linux/errno.h> -#include <asm/arch/fpga_manager.h> +#include <intel_socfpga/fpga_manager.h>  #include <asm/arch/reset_manager.h>  #include <asm/arch/system_manager.h>   @@ -66,4 +66,5 @@ void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)   "3: nop\n"   : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :   : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); -} \ No newline at end of file +}

diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index 03285f8..743ed4d 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -8,7 +8,7 @@  #include <common.h>  #include <asm/io.h>  #include <linux/errno.h> -#include <asm/arch/fpga_manager.h> +#include <intel_socfpga/fpga_manager.h>  #include <asm/arch/reset_manager.h>  #include <asm/arch/system_manager.h>   diff --git a/include/intel_socfpga/fpga_manager.h b/include/intel_socfpga/fpga_manager.h new file mode 100644 index 0000000..e02e4be --- /dev/null +++ b/include/intel_socfpga/fpga_manager.h @@ -0,0 +1,37 @@ +/*

• • Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
• • All rights reserved.
• • SPDX-License-Identifier:    BSD-3-Clause
• */

+#ifndef _FPGA_MANAGER_H_ +#define _FPGA_MANAGER_H_

+#include <altera.h>

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <intel_socfpga/fpga_manager_gen5.h> +#endif

+/* FPGA CD Ratio Value */ +#define CDRATIO_x1 0x0 +#define CDRATIO_x2 0x1 +#define CDRATIO_x4 0x2 +#define CDRATIO_x8 0x3

+/* SoCFPGA support functions */ +int fpgamgr_get_mode(void); +int fpgamgr_poll_fpga_ready(void); +void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size); +int fpgamgr_test_fpga_ready(void);;

+#define FPGA_TIMEOUT_CNT 0x1000000

+#ifndef __ASSEMBLY__

+/* Common prototypes */ +int fpgamgr_dclkcnt_set(unsigned long cnt);

+#endif /* __ASSEMBLY__ */ +#endif /* _FPGA_MANAGER_H_ */ diff --git a/include/intel_socfpga/fpga_manager_gen5.h b/include/intel_socfpga/fpga_manager_gen5.h new file mode 100644 index 0000000..2de7a11 --- /dev/null +++ b/include/intel_socfpga/fpga_manager_gen5.h @@ -0,0 +1,68 @@ +/*

• • Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
• • All rights reserved.
• • SPDX-License-Identifier:    BSD-3-Clause
• */

+#ifndef _FPGA_MANAGER_GEN5_H_ +#define _FPGA_MANAGER_GEN5_H_

+#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3

+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6

+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)

+/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5

+#ifndef __ASSEMBLY__

+struct socfpga_fpga_manager {

• /* FPGA Manager Module */
• u32 stat; /* 0x00 */
• u32 ctrl;
• u32 dclkcnt;
• u32 dclkstat;
• u32 gpo; /* 0x10 */
• u32 gpi;
• u32 misci; /* 0x18 */
• u32 _pad_0x1c_0x82c[517];
• /* Configuration Monitor (MON) Registers */
• u32 gpio_inten; /* 0x830 */
• u32 gpio_intmask;
• u32 gpio_inttype_level;
• u32 gpio_int_polarity;
• u32 gpio_intstatus; /* 0x840 */
• u32 gpio_raw_intstatus;
• u32 _pad_0x848;
• u32 gpio_porta_eoi;
• u32 gpio_ext_porta; /* 0x850 */
• u32 _pad_0x854_0x85c[3];
• u32 gpio_1s_sync; /* 0x860 */
• u32 _pad_0x864_0x868[2];
• u32 gpio_ver_id_code;
• u32 gpio_config_reg2; /* 0x870 */
• u32 gpio_config_reg1;

+};

+#endif /* __ASSEMBLY__ */

+#endif /* _FPGA_MANAGER_GEN5_H_ */

On 05/11/2017 11:25 AM, tien.fong.chee@intel.com wrote:

From: Tien Fong Chee tien.fong.chee@intel.com

Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

drivers/fpga/Makefile | 1 + drivers/fpga/socfpga_arria10.c | 482 +++++++++++++++++++++++++++ include/intel_socfpga/fpga_manager.h | 2 + include/intel_socfpga/fpga_manager_arria10.h | 105 ++++++ 4 files changed, 590 insertions(+) create mode 100644 drivers/fpga/socfpga_arria10.c create mode 100644 include/intel_socfpga/fpga_manager_arria10.h

diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index b65e5ba..08c9ff8 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c new file mode 100644 index 0000000..daa7394 --- /dev/null +++ b/drivers/fpga/socfpga_arria10.c @@ -0,0 +1,482 @@ +/*

• • Copyright (C) 2017 Intel Corporation <www.intel.com>
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <asm/io.h> +#include <intel_socfpga/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/misc.h> +#include <altera.h> +#include <common.h> +#include <errno.h> +#include <wait_bit.h> +#include <watchdog.h>

+#define CFGWDTH_32 1 +#define MIN_BITSTREAM_SIZECHECK 230 +#define ENCRYPTION_OFFSET 69 +#define COMPRESSION_OFFSET 229

+DECLARE_GLOBAL_DATA_PTR;

+static const struct socfpga_fpga_manager *fpga_manager_base =

• (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  

+static const struct socfpga_system_manager *system_manager_base =

• (void *)SOCFPGA_SYSMGR_ADDRESS;
  

+static void fpgamgr_set_cd_ratio(unsigned long ratio);

+static uint32_t fpgamgr_get_msel(void) +{

• u32 reg;
• reg = readl(&fpga_manager_base->imgcfg_stat);
• reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>

• ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  

• return reg;

+}

+static void fpgamgr_set_cfgwdth(int width) +{

• if (width)

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  

• 	ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  

• else

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  

• 	ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  

+}

+/* Check whether FPGA Init_Done signal is high */ +int is_fpgamgr_initdone_high(void) +{

• return (readl(&fpga_manager_base->imgcfg_stat) &

• ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
  

+}

+int is_fpgamgr_user_mode(void) +{

• return (readl(&fpga_manager_base->imgcfg_stat) &

• ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  

+}

+static int wait_for_user_mode(void) +{

• return wait_for_bit(__func__,

• &fpga_manager_base->imgcfg_stat,
  

• ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  

• 1, FPGA_TIMEOUT_MSEC, false);
  

+}

+static int is_fpgamgr_early_user_mode(void) +{

• return (readl(&fpga_manager_base->imgcfg_stat) &

• ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  

+}

+int fpgamgr_wait_early_user_mode(void) +{

• u32 sync_data = 0xffffffff;
• u32 i = 0;
• unsigned start = get_timer(0);
• unsigned long cd_ratio;
• /* Getting existing CDRATIO */
• cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &

• ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  

• ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  

• /* Using CDRATIO_X1 for better compatibility */
• fpgamgr_set_cd_ratio(CDRATIO_x1);
• while (!(is_fpgamgr_early_user_mode())) {

• if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  

• 	return -ETIMEDOUT;
  

• fpgamgr_program_write((const long unsigned int *)&sync_data,
  

• 		sizeof(sync_data));
  

• udelay(FPGA_TIMEOUT_MSEC);
  

• i++;
  

• }
• debug("Additional %i sync word needed\n", i);
• /* restoring original CDRATIO */
• fpgamgr_set_cd_ratio(cd_ratio);
• return 0;

+}

+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */ +static int wait_for_nconfig_pin_and_nstatus_pin(void) +{

• unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |

• 		ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
  

• /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,

• * timeout at 1000ms
  

• */
  

• return wait_for_bit(__func__,

• 	    &fpga_manager_base->imgcfg_stat,
  

• 	    mask,
  

• 	    false, FPGA_TIMEOUT_MSEC, false);
  

+}

+static int wait_for_f2s_nstatus_pin(unsigned long value) +{

• /* Poll until f2s to specific value, timeout at 1000ms */
• return wait_for_bit(__func__,

• 	    &fpga_manager_base->imgcfg_stat,
  

• 	    ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
  

• 	    value, FPGA_TIMEOUT_MSEC, false);
  

+}

+/* set CD ratio */ +static void fpgamgr_set_cd_ratio(unsigned long ratio) +{

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

• ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

• (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
  

• ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  

+}

+/* get the MSEL value, verify we are set for FPP configuration mode */ +static int fpgamgr_verify_msel(void) +{

• unsigned int msel = fpgamgr_get_msel();

u32 I guess ?

• if ((msel != 0) && (msel != 1)) {

• printf("Fail: read msel=%d\n", msel);
  

• return -EPERM;
  

• }
• return 0;

+}

+/*

• • Write cdratio and cdwidth based on whether the bitstream is compressed
• • and/or encoded
• */

+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,

• 		       u32 rbf_size)
  

+{

• unsigned int cd_ratio;
• bool encrypt, compress;
• /*

•     * According to the bitstream specification,
  

• * both encryption and compression status are
  

•     * in location before offset 230 of the buffer.
  

•     */
  

• if (rbf_size < MIN_BITSTREAM_SIZECHECK)

• return -EINVAL;
  

• encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
• encrypt = encrypt != 0;
• compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
• compress = !compress;
• debug("header word %d = %08x\n", 69, rbf_data[69]);
• debug("header word %d = %08x\n", 229, rbf_data[229]);
• debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
• /*

• * from the register map description of cdratio in imgcfg_ctrl_02:
  

• *  Normal Configuration    : 32bit Passive Parallel
  

• *  Partial Reconfiguration : 16bit Passive Parallel
  

• */
  

• /*

• * cd ratio is dependent on cfg width and whether the bitstream
  

• * is encrypted and/or compressed.
  

• *
  

• * | width | encr. | compr. | cd ratio |
  

• * |  16   |   0   |   0    |     1    |
  

• * |  16   |   0   |   1    |     4    |
  

• * |  16   |   1   |   0    |     2    |
  

• * |  16   |   1   |   1    |     4    |
  

• * |  32   |   0   |   0    |     1    |
  

• * |  32   |   0   |   1    |     8    |
  

• * |  32   |   1   |   0    |     4    |
  

• * |  32   |   1   |   1    |     8    |
  

• */
  

• if (!compress && !encrypt) {

• cd_ratio = CDRATIO_x1;
  

• } else {

• if (compress)
  

• 	cd_ratio = CDRATIO_x4;
  

• else
  

• 	cd_ratio = CDRATIO_x2;
  

• /* if 32 bit, double the cd ratio (so register
  

•    field setting is incremented) */
  

• if (cfg_width == CFGWDTH_32)
  

• 	cd_ratio += 1;
  

• }
• fpgamgr_set_cfgwdth(cfg_width);
• fpgamgr_set_cd_ratio(cd_ratio);
• return 0;

+}

+static int fpgamgr_reset(void) +{

• unsigned long reg;
• /* S2F_NCONFIG = 0 */
• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  

• /* Wait for f2s_nstatus == 0 */
• if (wait_for_f2s_nstatus_pin(0))

• return -ETIME;
  

• /* S2F_NCONFIG = 1 */
• setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  

• /* Wait for f2s_nstatus == 1 */
• if (wait_for_f2s_nstatus_pin(1))

• return -ETIME;
  

• /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
• reg = readl(&fpga_manager_base->imgcfg_stat);
• if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)

• return -EPERM;
  

• if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)

• return -EPERM;
  

• return 0;

+}

+/* Start the FPGA programming by initialize the FPGA Manager */ +int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size) +{

• int ret;
• /* Step 1 */
• if (fpgamgr_verify_msel())

• return -EPERM;
  

• /* Step 2 */
• if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))

• return -EPERM;
  

• /*

• * Step 3:
  

• * Make sure no other external devices are trying to interfere with
  

• * programming:
  

• */
  

• if (wait_for_nconfig_pin_and_nstatus_pin())

• return -ETIME;
  

• /*

• * Step 4:
  

• * Deassert the signal drives from HPS
  

• *
  

• * S2F_NCE = 1
  

• * S2F_PR_REQUEST = 0
  

• * EN_CFG_CTRL = 0
  

• * EN_CFG_DATA = 0
  

• * S2F_NCONFIG = 1
  

• * S2F_NSTATUS_OE = 0
  

• * S2F_CONDONE_OE = 0
  

• */
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
  

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
  

• /*

• * Step 5:
  

• * Enable overrides
  

• * S2F_NENABLE_CONFIG = 0
  

• * S2F_NENABLE_NCONFIG = 0
  

• */
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  

• /*

• * Disable driving signals that HPS doesn't need to drive.
  

• * S2F_NENABLE_NSTATUS = 1
  

• * S2F_NENABLE_CONDONE = 1
  

• */
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
  

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
  

• /*

• * Step 6:
  

• * Drive chip select S2F_NCE = 0
  

• */
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  

• /* Step 7 */
• if (wait_for_nconfig_pin_and_nstatus_pin())

• return -ETIME;
  

• /* Step 8 */

• ret = fpgamgr_reset();
  

Indent ? Modern compiler would warn you about this ...

• if (ret)
  

• 	return ret;
  

• /*

• * Step 9:
  

• * EN_CFG_CTRL and EN_CFG_DATA = 1
  

• */
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  

• return 0;

+}

+/* Ensure the FPGA entering config done */ +static int fpgamgr_program_poll_cd(void) +{

• unsigned long reg, i;
• for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {

• reg = readl(&fpga_manager_base->imgcfg_stat);
  

• if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
  

• 	return 0;
  

• if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
  

• 	printf("nstatus == 0 while waiting for condone\n");
  

• 	return -EPERM;
  

• }
  

• }
• if (i == FPGA_TIMEOUT_CNT)

• return -ETIME;
  

• return 0;

+}

+/* Ensure the FPGA entering user mode */ +static int fpgamgr_program_poll_usermode(void) +{

• unsigned long reg;
• int ret = 0;
• if (fpgamgr_dclkcnt_set(0xf))

• return -ETIME;
  

• ret = wait_for_user_mode();
• if (ret < 0) {

• printf("%s: Failed to enter user mode with ", __func__);
  

• printf("error code %d\n", ret);
  

Use single printf() .

• return ret;
  

• }
• /*

• * Step 14:
  

• * Stop DATA path and Dclk
  

• * EN_CFG_CTRL and EN_CFG_DATA = 0
  

• */
  

• clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  

• ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  

• /*

• * Step 15:
  

• * Disable overrides
  

• * S2F_NENABLE_CONFIG = 1
  

• * S2F_NENABLE_NCONFIG = 1
  

• */
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  

• setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,

• ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  

• /* Disable chip select S2F_NCE = 1 */
• setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,

• ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  

• /*

• * Step 16:
  

• * Final check
  

• */
  

• reg = readl(&fpga_manager_base->imgcfg_stat);
• if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) == 0) ||

•    ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) == 0) ||
  

•    ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0))
  

Just define a mask here and do if reg & mask != mask ...

• return -EPERM;
  

• return 0;

+}

+int fpgamgr_program_fini(void) +{

• /* Ensure the FPGA entering config done */
• int status = fpgamgr_program_poll_cd();
• if (status) {

• printf("FPGA: Poll CD failed with error code %d\n", status);
  

• return -EPERM;
  

• }
• WATCHDOG_RESET();
• /* Ensure the FPGA entering user mode */
• status = fpgamgr_program_poll_usermode();
• if (status) {

• printf("FPGA: Poll usermode failed with error code %d\n",
  

• 	status);
  

• return -EPERM;
  

• }
• printf("Full Configuration Succeeded.\n");
• return 0;

+}

+/*

• • FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
• • Return 0 for sucess, non-zero for error.
• */

+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{

• unsigned long status;
• /* disable all signals from hps peripheral controller to fpga */
• writel(0, &system_manager_base->fpgaintf_en_global);
• /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
• socfpga_bridges_reset();
• /* Initialize the FPGA Manager */
• status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
• if (status)

• return status;
  

• /* Write the RBF data to FPGA Manager */
• fpgamgr_program_write(rbf_data, rbf_size);
• return fpgamgr_program_fini();

+} diff --git a/include/intel_socfpga/fpga_manager.h b/include/intel_socfpga/fpga_manager.h index e02e4be..db51a48 100644 --- a/include/intel_socfpga/fpga_manager.h +++ b/include/intel_socfpga/fpga_manager.h @@ -12,6 +12,8 @@

#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <intel_socfpga/fpga_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <intel_socfpga/fpga_manager_arria10.h> #endif

/* FPGA CD Ratio Value */ diff --git a/include/intel_socfpga/fpga_manager_arria10.h b/include/intel_socfpga/fpga_manager_arria10.h new file mode 100644 index 0000000..23439c2 --- /dev/null +++ b/include/intel_socfpga/fpga_manager_arria10.h @@ -0,0 +1,105 @@ +/*

• • Copyright (C) 2017 Intel Corporation <www.intel.com>
• • All rights reserved.
• • SPDX-License-Identifier: GPL-2.0
• */

+#ifndef _FPGA_MANAGER_ARRIA10_H_ +#define _FPGA_MANAGER_ARRIA10_H_

+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\

• ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
• ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
• ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)

+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16

+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)

+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)

+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16

+/* Timeout counter */ +#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */

Use get_timer() for timeouts instead. Remove this from header file.

+#ifndef __ASSEMBLY__

+struct socfpga_fpga_manager {

• u32 _pad_0x0_0x7[2];
• u32 dclkcnt;
• u32 dclkstat;
• u32 gpo;
• u32 gpi;
• u32 misci;
• u32 _pad_0x1c_0x2f[5];
• u32 emr_data0;
• u32 emr_data1;
• u32 emr_data2;
• u32 emr_data3;
• u32 emr_data4;
• u32 emr_data5;
• u32 emr_valid;
• u32 emr_en;
• u32 jtag_config;
• u32 jtag_status;
• u32 jtag_kick;
• u32 _pad_0x5c_0x5f;
• u32 jtag_data_w;
• u32 jtag_data_r;
• u32 _pad_0x68_0x6f[2];
• u32 imgcfg_ctrl_00;
• u32 imgcfg_ctrl_01;
• u32 imgcfg_ctrl_02;
• u32 _pad_0x7c_0x7f;
• u32 imgcfg_stat;
• u32 intr_masked_status;
• u32 intr_mask;
• u32 intr_polarity;
• u32 dma_config;
• u32 imgcfg_fifo_status;

+};

+/* Functions */ +void fpgamgr_axi_write(const unsigned long *rbf_data,

• const unsigned long fpgamgr_data_addr, unsigned long rbf_size);

size_t

+int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size); +int fpgamgr_program_fini(void); +int is_fpgamgr_user_mode(void); +int fpgamgr_wait_early_user_mode(void);

+#endif /* __ASSEMBLY__ */

+#endif /* _FPGA_MANAGER_ARRIA10_H_ */