Re: [U-Boot] [PATCH] sf: ensure flash device is in 3-byte address mode

Hi Jagan,
On Fri, Nov 10, 2017 08:04, Jagan Teki wrote:
I've similar change on my patchwork, since no-one tested Will CC you by re-
basing it please have test?
Yes, of course I'd like to test this. Where do I find your patch?
Will rebase and send to ML soon.
Any progress here? Any chance that this one and the other fixes needed for cadence_qspi to work correctly get included in 2018.01?
The following patches would be required for this in addition to the 3-byte mode switch you wanted to submit:
"spi: cadence_spi: Adopt Linux DT bindings": https://patchwork.ozlabs.org/project/uboot/list/?series=13864
Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" (this one goes on top of the above) https://patchwork.ozlabs.org/patch/838871/
BTW: the series "spi: cadence_spi_apb: fix using bouncebuf with writeback dcache" can be closed when the reverting patch above is applied.
I already sent reviewed-by and tested-by for the first series above but I can't see them in patchwork.
Please let me know if there's anything missing or anything I can do to get this pushed.
Thanks, Simon

On Thu, Nov 30, 2017 at 2:11 PM, Goldschmidt Simon sgoldschmidt@de.pepperl-fuchs.com wrote:
Hi Jagan,
On Fri, Nov 10, 2017 08:04, Jagan Teki wrote:
I've similar change on my patchwork, since no-one tested Will CC you by re-
basing it please have test?
Yes, of course I'd like to test this. Where do I find your patch?
Will rebase and send to ML soon.
This is the patch[1] for 4-byte addressing, but I would wonder how can proceed operations with 4-byte if we disable during probe.
[1] http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=fd0c22a90772379c4c11ba09...
thanks!
participants (2)
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Goldschmidt Simon
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Jagan Teki