From: york yorksun@freescale.com

For 85xx silicon which supports address hashing, it can be activated by hwconfig.

Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 2 ++ arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 ++++++++++ arch/powerpc/cpu/mpc8xxx/ddr/options.c | 7 +++++++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 2 ++ doc/README.fsl-ddr | 15 +++++++++++++-- 5 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 0691ca4..e46dcb7 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -33,6 +33,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, return; }

+ out_be32(&ddr->eor, regs->ddr_eor); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 6e73b1d..ff0ddd1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1161,6 +1161,14 @@ static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) ); }

+static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + if (popts->addr_hash) { + ddr->ddr_eor = 0x40000000; /* address hash enable */ + puts("Addess hashing enabled.\n"); + } +} + unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) { @@ -1392,6 +1400,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_csn_config_2(i, ddr); }

+ set_ddr_eor(ddr, popts); + #if !defined(CONFIG_FSL_DDR1) set_timing_cfg_0(ddr); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 1d5f3e2..e4805d3 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -341,6 +341,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } }

+ if (hwconfig_sub("fsl_ddr", "addr_hash")) { + if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null")) + popts->addr_hash = 0; + else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true")) + popts->addr_hash = 1; + } + if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1;

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 431327e..d576eb8 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -119,6 +119,7 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; + unsigned int ddr_eor; } fsl_ddr_cfg_regs_t;

typedef struct memctl_options_partial_s { @@ -156,6 +157,7 @@ typedef struct memctl_options_s { unsigned int memctl_interleaving; unsigned int memctl_interleaving_mode; unsigned int ba_intlv_ctl; + unsigned int addr_hash;

/* Operational mode parameters */ unsigned int ECC_mode; /* Use ECC? */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 8c37bbe..e108a0d 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"

- The above memory controller interleaving and bank interleaving can be mixed. The syntax is - setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" +Memory controller address hashing +================================== +If the DDR controller supports address hashing, it can be enabled by hwconfig. + +Syntax is: +hwconfig=fsl_ddr:addr_hash=true + +Combination of hwconfig +======================= +Hwconfig can be combined with multiple parameters, for example, on a supported +platform + +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3

From: york yorksun@freescale.com

Changes for P2020DS DDR applies to other 8xxx platform

Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 14 +++++++------- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 1 + 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index b2962d2..dccb7aa 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -199,7 +199,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) unsigned char act_pd_exit_mclk; /* Precharge powerdown exit timing (tXP). */ unsigned char pre_pd_exit_mclk; - /* Precharge powerdown exit timing (tAXPD). */ + /* ODT powerdown exit timing (tAXPD). */ unsigned char taxpd_mclk; /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; @@ -211,13 +211,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * we use the tXP instead of it. * tXP=max(3nCK, 7.5ns) for DDR3. * spec has not the tAXPD, we use - * tAXPD=8, need design to confirm. + * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ act_pd_exit_mclk = picos_to_mclk(tXP); /* Mode register MR0[A12] is '1' - fast exit */ pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 8; + taxpd_mclk = 1; tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; @@ -1031,9 +1031,9 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */

#if defined(CONFIG_FSL_DDR3) - rodt_on = 3; /* 2 clocks */ + rodt_on = 2; /* 2 clocks */ rodt_off = 4; /* 4 clocks */ - wodt_on = 2; /* 1 clocks */ + wodt_on = 1; /* 1 clocks */ wodt_off = 4; /* 4 clocks */ #endif

@@ -1106,9 +1106,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, /* * Write leveling repetition time * at least tWLO + 6 clocks clocks - * we set it 32 + * we set it 64 */ - wrlvl_wlr = 0x5; + wrlvl_wlr = 0x6; /* * Write leveling start time * The value use for the DQS_ADJUST for the first sample diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index e4805d3..774c0e4 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -204,6 +204,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->zq_en = 1; popts->wrlvl_override = 0; #endif

From: york yorksun@freescale.com

If enabled in config file and hwconfig, the memory test is performed after DDR initialization when U-boot stills runs in flash and cache. Whole memory is testable. However, only the low 2GB space is mapped for DDR. The testing is conducted in the 2GB window and uses TLBs to map the higher physical address into the 2GB window if the total memory is more than 2GB. After the testing, DDR is remapped with up to 2GB memory from the lowest address.

Memory testing has different patterns which may be improved later.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped. All zero values are omitted for better viewing.

A worker function __setup_ddr_tlbs() is introduced to implemente more control on physical address mapping.

Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/memtest.c | 369 ++++++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 16 +- doc/README.fsl-ddr | 39 ++++ 4 files changed, 420 insertions(+), 6 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/memtest.c

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4ee0e9a..c0fc9ba 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -60,6 +60,8 @@ COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o

+COBJS-${CONFIG_SYS_DRAM_TEST} += memtest.o + COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc85xx/memtest.c b/arch/powerpc/cpu/mpc85xx/memtest.c new file mode 100644 index 0000000..7ad3326 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/memtest.c @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * York Sun yorksun@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hwconfig.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Board-specific functions defined in each board's ddr.c */ +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn); +unsigned int __setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg); + +#define PATTERN(pattern, address) (pattern == 0x12345678 ? address : pattern) + +#define TOTAL_PROGRESS_DOTS 45 +#define TOTAL_PROGRESS_NUMBERS 9 +#define PROGRESS_DOTS_PER_NUMBER (TOTAL_PROGRESS_DOTS/TOTAL_PROGRESS_NUMBERS) +#define TEST_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ +{ \ + dots -= (dots_sub); \ + if ((scale > 0) && (dots <= 0)) { \ + if ((digit % PROGRESS_DOTS_PER_NUMBER) == 0) \ + printf("%d", digit / PROGRESS_DOTS_PER_NUMBER); \ + else \ + putc('.'); \ + digit--; \ + dots += (scale); \ + } \ +} + +#if defined(CONFIG_SYS_DRAM_TEST) +void dump_spd_ddr_reg(void) +{ + int i, j, k, m; + u8 *p_8; + u32 *p_32; + ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + generic_spd_eeprom_t + spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + fsl_ddr_get_spd(spd[i], i); + } + puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("Byte (hex) "); + k = 1; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) + printf("Dimm%d ", k++); + puts("\n"); + for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { + m = 0; + printf("%3d (0x%02x) ", k, k); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + p_8 = (u8 *) &spd[i][j]; + if (p_8[k]) { + printf("0x%02x ", p_8[k]); + m++; + } else + puts(" "); + } + } + if (m) + puts("\n"); + else + puts("\r"); + } + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + switch (i) { + case 0: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + break; +#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR + case 1: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + break; +#endif + default: + printf("%s unexpected controller number = %u\n", + __FUNCTION__, i); + return; + } + } + printf("DDR registers dump for all controllers " + "(zero vaule is omitted)...\n"); + puts("Offset (hex) "); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); + puts("\n"); + for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + m = 0; + printf("%6d (0x%04x)", k * 4, k * 4); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + p_32 = (u32 *) ddr[i]; + if (p_32[k]) { + printf(" 0x%08x", p_32[k]); + m++; + } else + puts(" "); + } + if (m) + puts("\n"); + else + puts("\r"); + } + puts("\n"); +} + +#define MODULOMASK 0x3F +#define MODULOX 16 +int pattern_test(u32 start_addr, u32 size, u32 pattern, u64 offset) +{ + const int MaxError = 10; + volatile u32 *p; + u32 ptr, buffer, end_addr = start_addr + size; + int error = 0; + int digit, dots; + int scale; + + puts("Pattern: Moving Inversions "); + if (pattern == 0x12345678) + puts("Address March\n"); + else + printf("0x%08x\n", pattern); + + scale = (int)(((size >> 20) + TOTAL_PROGRESS_DOTS - 1) / + TOTAL_PROGRESS_DOTS); + digit = TOTAL_PROGRESS_DOTS; + dots = 0; + for (p = (volatile u32 *)(start_addr & 0xfffffffc); + p < (volatile u32 *)(end_addr & 0xfffffffc); p++) { + *p = PATTERN(pattern, (u32)p); + if (((u32)p % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); + } + puts("Filled with pattern.\n"); + digit = TOTAL_PROGRESS_DOTS; + dots = 0; + for (ptr = (start_addr & 0xfffffffc); + ptr < (end_addr & 0xfffffffc); ptr += sizeof(u32)) { + p = (volatile u32 *) ptr; + buffer = *p; + if (buffer != PATTERN(pattern, ptr)) { + error++; + printf("\nAddress 0x%08llx, Write 0x%08x, Read 0x%08x", + offset + ptr, PATTERN(pattern, ptr), buffer); + if (error > MaxError) + break; + } + *p = ~PATTERN(pattern, ptr); + if ((ptr % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); + } + if (error == 0) + puts("Verified and written with complement.\n"); + else { + puts("\nFailed!\n\n"); + return error; + } + digit = TOTAL_PROGRESS_DOTS; + dots = 0; + for (ptr = ((end_addr - 1) & 0xfffffffc); + ptr > (start_addr & 0xfffffffc); ptr -= sizeof(u32)) { + p = (volatile u32 *) ptr; + buffer = *p; + if (buffer != ~PATTERN(pattern, ptr)) { + error++; + printf("\nAddress 0x%08llx, Write 0x%08x, Read 0x%08x", + offset + ptr, ~PATTERN(pattern, ptr), buffer); + if (error > MaxError) + break; + } + *p = PATTERN(pattern, ptr); + if ((ptr % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); + } + if (error == 0) + puts("Verified OK.\n\n"); + else { + puts("\nFailed!\n\n"); + return error; + } + + printf("Pattern: Modulo-%d ", MODULOX); + if (pattern == 0x12345678) + puts("Address March\n"); + else + printf(" 0x%08x\n", pattern); + digit = TOTAL_PROGRESS_DOTS; + dots = 0; + for (ptr = (start_addr & 0xfffffffc); + ptr < (end_addr & 0xfffffffc); ptr += sizeof(u32)) { + p = (volatile u32 *) ptr; + if (ptr & MODULOMASK) + *p = PATTERN(pattern, ptr); + else + *p = ~PATTERN(pattern, ptr); + if (ptr % (1 << 20) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); + } + puts("Filled with pattern.\n"); + scale = (int)(((size / MODULOX / sizeof(u32)) + TOTAL_PROGRESS_DOTS - 1) / + TOTAL_PROGRESS_DOTS); + digit = TOTAL_PROGRESS_DOTS; + dots = 0; + for (ptr = (start_addr & 0xfffffffc); + ptr < (end_addr & 0xfffffffc); ptr += sizeof(u32)) { + if (ptr & MODULOMASK) + break; + } + for (; ptr < (end_addr & 0xfffffffc); ptr += MODULOX * sizeof(u32)) { + p = (volatile u32 *) ptr; + buffer = *p; + if (buffer != PATTERN(pattern, ptr)) { + error++; + printf("\nAddress 0x%08llx, Write 0x%08x, Read 0x%08x", + ptr + offset, PATTERN(pattern, ptr), buffer); + if (error > MaxError) + break; + } + TEST_SHOW_PROGRESS(scale, dots, digit, 1); + } + if (error == 0) + puts("OK.\n\n"); + else + puts("\nFailed!\n\n"); + return error; +} + +/* + * This funciton is called before U-boot relocates itself to RAM + * The L1 cache should be locked and L2 cache is not enabled yet + */ +int __testdram(phys_addr_t p_addr, u32 size, int simple_test) +{ + + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vend = vstart + size; + int failed = 0; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + puts("DDR memory testing...\n"); + size = min(size, CONFIG_MAX_MEM_MAPPED); + ptr = vstart; + while (ptr < vend) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + /* Setup new tlb to cover the physical address */ + __setup_ddr_tlbs(p_addr, size>>20); + + ptr = vstart; + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + } else { + printf("TLB error in function %s\n", __FUNCTION__); + return -1; + } + + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)vstart + rpn, (u64)vstart + rpn + size - 1); + + failed = pattern_test(vstart, size, 0, rpn); + if (!simple_test) { + if (failed == 0) + failed = pattern_test(vstart, size, 0xaaaaaaaa, rpn); + if (failed == 0) + pattern_test(vstart, size, 0x55555555, rpn); + if (failed == 0) + failed = pattern_test(vstart, size, 0xffffffff, rpn); + if (failed == 0) + failed = pattern_test(vstart, size, 0x12345678, rpn); + } + if (failed != 0) + dump_spd_ddr_reg(); + + /* disable the TLBs for this testing */ + ptr = vstart; + while (ptr < vend) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + return failed; +} + +int testdram(void) +{ + int simple_test, failed = 0; + phys_addr_t test_cap, p_addr = CONFIG_SYS_DDR_SDRAM_BASE; + phys_size_t p_size; + if (hwconfig("memtest")) { + if (hwconfig_arg_cmp("memtest", "null") || \ + (!hwconfig_arg_cmp("memtest", "true") && \ + !hwconfig_arg_cmp("memtest", "simple"))) { + puts("memtest is not enabled in hwconfig, skipped.\n"); + return 0; + } + simple_test = hwconfig_arg_cmp("memtest", "simple"); + p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + puts("Cannot test more than "); + print_size(CONFIG_MAX_MEM_MAPPED, + " without proper 36BIT support.\n"); + } + test_cap = p_size; +#else + test_cap = gd->ram_size; +#endif + while (p_addr < test_cap - 1) { + if (__testdram(p_addr, (u32)p_size, simple_test) != 0) + failed++; + p_addr += p_size; + p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + } + if (failed) + printf("\nWarning: Memory test failed." + " Software may not run as expected.\n"); + puts("Remap DDR "); + setup_ddr_tlbs(gd->ram_size>>20); + puts("\n"); + } else + puts("memtest is not set in hwconfig, skipped.\n"); + return 0; +} +#endif diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index f2833a5..019fab7 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -245,7 +245,8 @@ void init_addr_map(void) } #endif

-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +unsigned int +__setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; @@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)

tlb_size = (camsize - 10) / 2;

- set_tlb(1, ram_tlb_address, ram_tlb_address, + set_tlb(1, ram_tlb_address, p_addr, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1);

size -= 1ULL << camsize; memsize -= 1ULL << camsize; ram_tlb_address += 1UL << camsize; + p_addr += 1UL << camsize; }

if (memsize) print_size(memsize, " left unmapped\n"); - - /* - * Confirm that the requested amount of memory was mapped. - */ return memsize_in_meg; } + +unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +{ + return + __setup_ddr_tlbs(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} #endif /* !CONFIG_NAND_SPL */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index e108a0d..f5deb4f 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,6 +78,45 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true

+ +Memory testing options for mpc85xx +================================== +1. Memory test can be done one U-boot prompt comes up using mtest, or +2. Memory test can be done with a built-in function, activated at compile time + and by hwconfig. + In order to enable the built-in memory test, CONFIG_SYS_DRAM_TEST needs to be + defined in board configuraiton header file. Hwconfig is also required. To test + memory bigger than 2GB, 36BIT support is needed. Memory is tested within a 2GB + window. TLBs are used to map the virtual 2GB window to physical address so that + all physical memory can be tested. + + Syntax of hwconfig + hwconfig=memtest:true or + hwconfig=memtest:simple + + The "simple" test uses one pattern and "true" uses more patterns. The testing + patterns include moving inversions and modulo-16. + +Moving inversions +================= +Moving inversions test takes a pattern (eg. 0x00000000) and fills the memory with +the pattern for the first round. The software then takes the second round to check +each address against the pattern, if matched the complement data is written back +and software moves on to next address, all the way to the end. In the third round, +software checks the complement of pattern of each address. + +Modulo-16 +========= +Modulo-16 is a test for selected address. In the first round, software fills the +memory with a pattern and the complement of the pattern every 16-sizeof(int). In +the second round, software checks the complement of the pattern at selected address. + +Patterns +======== +Built-in patterns are 0x00000000, 0xAAAAAAAA, 0x55555555, 0xFFFFFFFF and Address +Marching (i.e. the address of the cell). + + Combination of hwconfig ======================= Hwconfig can be combined with multiple parameters, for example, on a supported

Wolfgang,

On Thu, 2010-07-15 at 11:07 +0200, Wolfgang Denk wrote:

Dear Timur Tabi,

In message AANLkTim6yjF6ORogtqE0vqiVqZqxu-EkkUhDTmJMgPqu@mail.gmail.com you wrote:

...

...

NAK.

Please do not reinvent the wheel and add yet another meory test. Use one of the existing memory tests we already have - post/drivers/memory.c comes to mind.

That code is not capable of testing more than 2GB of RAM. It assumes that memory has already been initialized, but on PowerPC parts, we only ever map 2GB of DDR. We need a memory test that covers all of DDR, but that requries PowerPC-specific code to create sliding TLB windows during the memory test.

Then please extend the existing code and add the missing features.

We already have too many different implementations of a memory test in U-Boot, and I will not accept adding yet another one.

I can reuse your testing code but have to move the desired code out of memory.c file to avoid the need for CONFIG_POST and CONFIG_SYS_POST_MEMORY. I also add a progress indicator. My testing target is 2GB at a time, up to physically memory size which is easily over 8GB. Without progress indicator, it feels hung when it is actually running.

Please take a look at the patch below.

Regards,

York

From 58002b8f549ca114583b72f541032fb106b6bf66 Mon Sep 17 00:00:00 2001

From: York Sun yorksun@freescale.com Date: Wed, 23 Jun 2010 11:18:48 -0500 Subject: [PATCH] Add memory test feature for mpc85xx.

Reuse memory test code for POST. Move the actually pattern generator and testing out of POST.

If enabled in config file and hwconfig, the memory test is performed after DDR initialization when U-boot stills runs in flash and cache. Whole memory is testable. However, only the low 2GB space is mapped for DDR. The testing is conducted in the 2GB window and uses TLBs to map the higher physical address into the 2GB window if the total memory is more than 2GB. After the testing, DDR is remapped with up to 2GB memory from the lowest address.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped. All zero values are omitted for better viewing.

A worker function __setup_ddr_tlbs() is introduced to implemente more control on physical address mapping.

Signed-off-by: York Sun yorksun@freescale.com ---

This patch is for discussion where to put the memory test code.

arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/memtest.c | 220 +++++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 16 +- doc/README.fsl-ddr | 13 +- post/drivers/Makefile | 2 +- post/drivers/memory.c | 426 +------------------------- post/drivers/{memory.c => memtest_pattern.c} | 147 ++++++--- 7 files changed, 346 insertions(+), 480 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/memtest.c copy post/drivers/{memory.c => memtest_pattern.c} (79%)

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 2c12ef2..383de6a 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -62,6 +62,8 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o

+COBJS-${CONFIG_SYS_DRAM_TEST} += memtest.o $(TOPDIR)/post/drivers/memtest_pattern.o + COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o liodn_r1.o diff --git a/arch/powerpc/cpu/mpc85xx/memtest.c b/arch/powerpc/cpu/mpc85xx/memtest.c new file mode 100644 index 0000000..b873136 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/memtest.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * York Sun yorksun@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hwconfig.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Board-specific functions defined in each board's ddr.c */ +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn); +unsigned int __setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg); + +int memory_post_tests (unsigned long start, unsigned long size); + +#if defined(CONFIG_SYS_DRAM_TEST) +void dump_spd_ddr_reg(void) +{ + int i, j, k, m; + u8 *p_8; + u32 *p_32; + ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + generic_spd_eeprom_t + spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + fsl_ddr_get_spd(spd[i], i); + + puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("Byte (hex) "); + k = 1; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) + printf("Dimm%d ", k++); + puts("\n"); + for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { + m = 0; + printf("%3d (0x%02x) ", k, k); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + p_8 = (u8 *) &spd[i][j]; + if (p_8[k]) { + printf("0x%02x ", p_8[k]); + m++; + } else + puts(" "); + } + } + if (m) + puts("\n"); + else + puts("\r"); + } + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + switch (i) { + case 0: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + break; +#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR + case 1: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + break; +#endif + default: + printf("%s unexpected controller number = %u\n", + __func__, i); + return; + } + } + printf("DDR registers dump for all controllers " + "(zero vaule is omitted)...\n"); + puts("Offset (hex) "); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); + puts("\n"); + for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + m = 0; + printf("%6d (0x%04x)", k * 4, k * 4); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + p_32 = (u32 *) ddr[i]; + if (p_32[k]) { + printf(" 0x%08x", p_32[k]); + m++; + } else + puts(" "); + } + if (m) + puts("\n"); + else + puts("\r"); + } + puts("\n"); +} + +/* + * This funciton is called before U-boot relocates itself to RAM + * The L1 cache should be locked and L2 cache is not enabled yet + */ +int __testdram(phys_addr_t p_addr, u32 size) +{ + + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vend = vstart + size; + int failed = 0; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + puts("DDR memory testing...\n"); + size = min(size, CONFIG_MAX_MEM_MAPPED); + ptr = vstart; + while (ptr < vend) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + /* Setup new tlb to cover the physical address */ + __setup_ddr_tlbs(p_addr, size>>20); + + ptr = vstart; + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + } else { + printf("TLB error in function %s\n", __func__); + return -1; + } + + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)vstart + rpn, (u64)vstart + rpn + size - 1); + + failed = memory_post_tests(vstart, size); + if (failed != 0) + dump_spd_ddr_reg(); + + /* disable the TLBs for this testing */ + ptr = vstart; + while (ptr < vend) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + return failed; +} + +int testdram(void) +{ + int failed = 0; + phys_addr_t test_cap, p_addr = CONFIG_SYS_DDR_SDRAM_BASE; + phys_size_t p_size; + if (hwconfig("memtest")) { + if (hwconfig_arg_cmp("memtest", "null") || \ + (!hwconfig_arg_cmp("memtest", "true"))) { + puts("memtest is not enabled in hwconfig, skipped.\n"); + return 0; + } + p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + puts("Cannot test more than "); + print_size(CONFIG_MAX_MEM_MAPPED, + " without proper 36BIT support.\n"); + } + test_cap = p_size; +#else + test_cap = gd->ram_size; +#endif + while (p_addr < test_cap - 1) { + if (__testdram(p_addr, (u32)p_size) != 0) + failed++; + p_addr += p_size; + p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + } + if (failed) + printf("\nWarning: Memory test failed." + " Software may not run as expected.\n"); + puts("Remap DDR "); + setup_ddr_tlbs(gd->ram_size>>20); + puts("\n"); + } else + puts("memtest is not set in hwconfig, skipped.\n"); + return 0; +} +#endif diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index f2833a5..019fab7 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -245,7 +245,8 @@ void init_addr_map(void) } #endif

-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +unsigned int +__setup_ddr_tlbs(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; @@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)

tlb_size = (camsize - 10) / 2;

- set_tlb(1, ram_tlb_address, ram_tlb_address, + set_tlb(1, ram_tlb_address, p_addr, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1);

size -= 1ULL << camsize; memsize -= 1ULL << camsize; ram_tlb_address += 1UL << camsize; + p_addr += 1UL << camsize; }

if (memsize) print_size(memsize, " left unmapped\n"); - - /* - * Confirm that the requested amount of memory was mapped. - */ return memsize_in_meg; } + +unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +{ + return + __setup_ddr_tlbs(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} #endif /* !CONFIG_NAND_SPL */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index e108a0d..4c528ac 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,9 +78,20 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true

+ +Memory testing options for mpc85xx +================================== +1. Memory test can be done one U-boot prompt comes up using mtest, or +2. Memory test can be done with a built-in function, activated at compile time + and by hwconfig. + In order to enable the built-in memory test, CONFIG_SYS_DRAM_TEST needs to be + defined in board configuraiton header file. Hwconfig is also required. To test + memory bigger than 2GB, 36BIT support is needed. Memory is tested within a 2GB + Combination of hwconfig ======================= Hwconfig can be combined with multiple parameters, for example, on a supported platform

-hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,;memtest=true + diff --git a/post/drivers/Makefile b/post/drivers/Makefile index 0b6cdf5..6f67b9c 100644 --- a/post/drivers/Makefile +++ b/post/drivers/Makefile @@ -24,6 +24,6 @@ include $(TOPDIR)/config.mk

LIB = libpostdrivers.a

-COBJS-$(CONFIG_HAS_POST) += i2c.o memory.o rtc.o +COBJS-$(CONFIG_HAS_POST) += i2c.o memtest_pattern.o memory.o rtc.o

include $(TOPDIR)/post/rules.mk diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 0062360..ee11e4b 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -22,436 +22,12 @@ */

#include <common.h> - -/* Memory test - * - * General observations: - * o The recommended test sequence is to test the data lines: if they are - * broken, nothing else will work properly. Then test the address - * lines. Finally, test the cells in the memory now that the test - * program knows that the address and data lines work properly. - * This sequence also helps isolate and identify what is faulty. - * - * o For the address line test, it is a good idea to use the base - * address of the lowest memory location, which causes a '1' bit to - * walk through a field of zeros on the address lines and the highest - * memory location, which causes a '0' bit to walk through a field of - * '1's on the address line. - * - * o Floating buses can fool memory tests if the test routine writes - * a value and then reads it back immediately. The problem is, the - * write will charge the residual capacitance on the data bus so the - * bus retains its state briefely. When the test program reads the - * value back immediately, the capacitance of the bus can allow it - * to read back what was written, even though the memory circuitry - * is broken. To avoid this, the test program should write a test - * pattern to the target location, write a different pattern elsewhere - * to charge the residual capacitance in a differnt manner, then read - * the target location back. - * - * o Always read the target location EXACTLY ONCE and save it in a local - * variable. The problem with reading the target location more than - * once is that the second and subsequent reads may work properly, - * resulting in a failed test that tells the poor technician that - * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which - * doesn't help him one bit and causes puzzled phone calls. Been there, - * done that. - * - * Data line test: - * --------------- - * This tests data lines for shorts and opens by forcing adjacent data - * to opposite states. Because the data lines could be routed in an - * arbitrary manner the must ensure test patterns ensure that every case - * is tested. By using the following series of binary patterns every - * combination of adjacent bits is test regardless of routing. - * - * ...101010101010101010101010 - * ...110011001100110011001100 - * ...111100001111000011110000 - * ...111111110000000011111111 - * - * Carrying this out, gives us six hex patterns as follows: - * - * 0xaaaaaaaaaaaaaaaa - * 0xcccccccccccccccc - * 0xf0f0f0f0f0f0f0f0 - * 0xff00ff00ff00ff00 - * 0xffff0000ffff0000 - * 0xffffffff00000000 - * - * To test for short and opens to other signals on our boards, we - * simply test with the 1's complemnt of the paterns as well, resulting - * in twelve patterns total. - * - * After writing a test pattern. a special pattern 0x0123456789ABCDEF is - * written to a different address in case the data lines are floating. - * Thus, if a byte lane fails, you will see part of the special - * pattern in that byte lane when the test runs. For example, if the - * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa - * (for the 'a' test pattern). - * - * Address line test: - * ------------------ - * This function performs a test to verify that all the address lines - * hooked up to the RAM work properly. If there is an address line - * fault, it usually shows up as two different locations in the address - * map (related by the faulty address line) mapping to one physical - * memory storage location. The artifact that shows up is writing to - * the first location "changes" the second location. - * - * To test all address lines, we start with the given base address and - * xor the address with a '1' bit to flip one address line. For each - * test, we shift the '1' bit left to test the next address line. - * - * In the actual code, we start with address sizeof(ulong) since our - * test pattern we use is a ulong and thus, if we tried to test lower - * order address bits, it wouldn't work because our pattern would - * overwrite itself. - * - * Example for a 4 bit address space with the base at 0000: - * 0000 <- base - * 0001 <- test 1 - * 0010 <- test 2 - * 0100 <- test 3 - * 1000 <- test 4 - * Example for a 4 bit address space with the base at 0010: - * 0010 <- base - * 0011 <- test 1 - * 0000 <- (below the base address, skipped) - * 0110 <- test 2 - * 1010 <- test 3 - * - * The test locations are successively tested to make sure that they are - * not "mirrored" onto the base address due to a faulty address line. - * Note that the base and each test location are related by one address - * line flipped. Note that the base address need not be all zeros. - * - * Memory tests 1-4: - * ----------------- - * These tests verify RAM using sequential writes and reads - * to/from RAM. There are several test cases that use different patterns to - * verify RAM. Each test case fills a region of RAM with one pattern and - * then reads the region back and compares its contents with the pattern. - * The following patterns are used: - * - * 1a) zero pattern (0x00000000) - * 1b) negative pattern (0xffffffff) - * 1c) checkerboard pattern (0x55555555) - * 1d) checkerboard pattern (0xaaaaaaaa) - * 2) bit-flip pattern ((1 << (offset % 32)) - * 3) address pattern (offset) - * 4) address pattern (~offset) - * - * Being run in normal mode, the test verifies only small 4Kb - * regions of RAM around each 1Mb boundary. For example, for 64Mb - * RAM the following areas are verified: 0x00000000-0x00000800, - * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- - * 0x04000000. If the test is run in slow-test mode, it verifies - * the whole RAM. - */ - #include <post.h> -#include <watchdog.h>

-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if (CONFIG_POST & CONFIG_SYS_POST_MEMORY)

DECLARE_GLOBAL_DATA_PTR;

-/* - * Define INJECT_*_ERRORS for testing error detection in the presence of - * _good_ hardware. - */ -#undef INJECT_DATA_ERRORS -#undef INJECT_ADDRESS_ERRORS - -#ifdef INJECT_DATA_ERRORS -#warning "Injecting data line errors for testing purposes" -#endif - -#ifdef INJECT_ADDRESS_ERRORS -#warning "Injecting address line errors for testing purposes" -#endif - - -/* - * This function performs a double word move from the data at - * the source pointer to the location at the destination pointer. - * This is helpful for testing memory on processors which have a 64 bit - * wide data bus. - * - * On those PowerPC with FPU, use assembly and a floating point move: - * this does a 64 bit move. - * - * For other processors, let the compiler generate the best code it can. - */ -static void move64(const unsigned long long *src, unsigned long long *dest) -{ -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else - *dest = *src; -#endif -} - -/* - * This is 64 bit wide test patterns. Note that they reside in ROM - * (which presumably works) and the tests write them to RAM which may - * not work. - * - * The "otherpattern" is written to drive the data bus to values other - * than the test pattern. This is for detecting floating bus lines. - * - */ -const static unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL -}; -const unsigned long long otherpattern = 0x0123456789abcdefULL; - - -static int memory_post_dataline(unsigned long long * pmem) -{ - unsigned long long temp64 = 0; - int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); - int i; - unsigned int hi, lo, pathi, patlo; - int ret = 0; - - for ( i = 0; i < num_patterns; i++) { - move64(&(pattern[i]), pmem++); - /* - * Put a different pattern on the data lines: otherwise they - * may float long enough to read back what we wrote. - */ - move64(&otherpattern, pmem--); - move64(pmem, &temp64); - -#ifdef INJECT_DATA_ERRORS - temp64 ^= 0x00008000; -#endif - - if (temp64 != pattern[i]){ - pathi = (pattern[i]>>32) & 0xffffffff; - patlo = pattern[i] & 0xffffffff; - - hi = (temp64>>32) & 0xffffffff; - lo = temp64 & 0xffffffff; - - post_log ("Memory (date line) error at %08x, " - "wrote %08x%08x, read %08x%08x !\n", - pmem, pathi, patlo, hi, lo); - ret = -1; - } - } - return ret; -} - -static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) -{ - ulong *target; - ulong *end; - ulong readback; - ulong xor; - int ret = 0; - - end = (ulong *)((ulong)base + size); /* pointer arith! */ - xor = 0; - for(xor = sizeof(ulong); xor > 0; xor <<= 1) { - target = (ulong *)((ulong)testaddr ^ xor); - if((target >= base) && (target < end)) { - *testaddr = ~*target; - readback = *target; - -#ifdef INJECT_ADDRESS_ERRORS - if(xor == 0x00008000) { - readback = *testaddr; - } -#endif - if(readback == *testaddr) { - post_log ("Memory (address line) error at %08x<->%08x, " - "XOR value %08x !\n", - testaddr, target, xor); - ret = -1; - } - } - } - return ret; -} - -static int memory_post_test1 (unsigned long start, - unsigned long size, - unsigned long val) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = val; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != val) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, val, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test2 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = 1 << (i % 32); - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != (1 << (i % 32))) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, 1 << (i % 32), readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test3 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test4 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = ~i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != ~i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, ~i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_tests (unsigned long start, unsigned long size) -{ - int ret = 0; - - if (ret == 0) - ret = memory_post_dataline ((unsigned long long *)start); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)(start + size - 8), - (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x00000000); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xffffffff); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x55555555); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xaaaaaaaa); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test2 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test3 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test4 (start, size); - WATCHDOG_RESET (); - - return ret; -} - int memory_post_test (int flags) { int ret = 0; diff --git a/post/drivers/memory.c b/post/drivers/memtest_pattern.c similarity index 79% copy from post/drivers/memory.c copy to post/drivers/memtest_pattern.c index 0062360..713de29 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memtest_pattern.c @@ -22,7 +22,6 @@ */

#include <common.h> - /* Memory test * * General observations: @@ -150,12 +149,31 @@ * the whole RAM. */

-#include <post.h> #include <watchdog.h>

-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if (CONFIG_POST & CONFIG_SYS_POST_MEMORY) | defined(CONFIG_SYS_DRAM_TEST) +#ifdef CONFIG_POST +#define test_log(fmt, args...) test_log(fmt, ##args) +#else +#define test_log(fmt, args...) printf(fmt, ##args) +#endif

-DECLARE_GLOBAL_DATA_PTR; +/* The follow is progress indicator, borrowed from flash programming code */ +#define TOTAL_PROGRESS_DOTS 45 +#define TOTAL_PROGRESS_NUMBERS 9 +#define PROGRESS_DOTS_PER_NUMBER (TOTAL_PROGRESS_DOTS/TOTAL_PROGRESS_NUMBERS) +#define TEST_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ +{ \ + dots -= (dots_sub); \ + if ((scale > 0) && (dots <= 0)) { \ + if ((digit % PROGRESS_DOTS_PER_NUMBER) == 0) \ + printf("%d", digit / PROGRESS_DOTS_PER_NUMBER); \ + else \ + putc('.'); \ + digit--; \ + dots += (scale); \ + } \ +}

/* * Define INJECT_*_ERRORS for testing error detection in the presence of @@ -230,6 +248,7 @@ static int memory_post_dataline(unsigned long long * pmem) unsigned int hi, lo, pathi, patlo; int ret = 0;

+ test_log("Data line test "); for ( i = 0; i < num_patterns; i++) { move64(&(pattern[i]), pmem++); /* @@ -250,12 +269,16 @@ static int memory_post_dataline(unsigned long long * pmem) hi = (temp64>>32) & 0xffffffff; lo = temp64 & 0xffffffff;

- post_log ("Memory (date line) error at %08x, " + test_log("Memory (date line) error at %p, " "wrote %08x%08x, read %08x%08x !\n", pmem, pathi, patlo, hi, lo); ret = -1; } } + if (ret) + test_log("failed\n"); + else + test_log("passed\n"); return ret; }

@@ -267,6 +290,7 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) ulong xor; int ret = 0;

+ test_log("Address line test "); end = (ulong *)((ulong)base + size); /* pointer arith! */ xor = 0; for(xor = sizeof(ulong); xor > 0; xor <<= 1) { @@ -281,13 +305,17 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) } #endif if(readback == *testaddr) { - post_log ("Memory (address line) error at %08x<->%08x, " - "XOR value %08x !\n", + test_log("Memory (address line) error at %p<->%p, " + "XOR value %08lx !\n", testaddr, target, xor); ret = -1; } } } + if (ret) + test_log("failed\n"); + else + test_log("passed\n"); return ret; }

@@ -299,18 +327,27 @@ static int memory_post_test1 (unsigned long start, ulong *mem = (ulong *) start; ulong readback; int ret = 0; + int digit = TOTAL_PROGRESS_DOTS; + int dots = 0; + int scale = (int)(((size >> 20) / sizeof(ulong) + TOTAL_PROGRESS_DOTS - 1) / TOTAL_PROGRESS_DOTS);

+ test_log("Pattern test %08lx\n", val); for (i = 0; i < size / sizeof (ulong); i++) { mem[i] = val; if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + test_log("Filled with pattern\n"); + digit = TOTAL_PROGRESS_DOTS; + dots = 0;

for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { readback = mem[i]; if (readback != val) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", + test_log("Memory error at %p, " + "wrote %08lx, read %08lx !\n", mem + i, val, readback);

ret = -1; @@ -318,7 +355,11 @@ static int memory_post_test1 (unsigned long start, } if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + if (!ret) + test_log("Verifed\n");

return ret; } @@ -329,18 +370,28 @@ static int memory_post_test2 (unsigned long start, unsigned long size) ulong *mem = (ulong *) start; ulong readback; int ret = 0; + int digit = TOTAL_PROGRESS_DOTS; + int dots = 0; + int scale = (int)(((size >> 20) / sizeof(ulong) + TOTAL_PROGRESS_DOTS - 1) / TOTAL_PROGRESS_DOTS); + + test_log("Bit flip pattern test\n");

for (i = 0; i < size / sizeof (ulong); i++) { mem[i] = 1 << (i % 32); if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + test_log("Filled with pattern\n"); + digit = TOTAL_PROGRESS_DOTS; + dots = 0;

for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { readback = mem[i]; if (readback != (1 << (i % 32))) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", + test_log("Memory error at %p, " + "wrote %08x, read %08lx !\n", mem + i, 1 << (i % 32), readback);

ret = -1; @@ -348,7 +399,11 @@ static int memory_post_test2 (unsigned long start, unsigned long size) } if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + if (!ret) + test_log("Verifed\n");

return ret; } @@ -359,18 +414,28 @@ static int memory_post_test3 (unsigned long start, unsigned long size) ulong *mem = (ulong *) start; ulong readback; int ret = 0; + int digit = TOTAL_PROGRESS_DOTS; + int dots = 0; + int scale = (int)(((size >> 20) / sizeof(ulong) + TOTAL_PROGRESS_DOTS - 1) / TOTAL_PROGRESS_DOTS); + + test_log("Address pattern (offset)\n");

for (i = 0; i < size / sizeof (ulong); i++) { mem[i] = i; if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + test_log("Filled with pattern\n"); + digit = TOTAL_PROGRESS_DOTS; + dots = 0;

for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { readback = mem[i]; if (readback != i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", + test_log("Memory error at %p, " + "wrote %08lx, read %08lx !\n", mem + i, i, readback);

ret = -1; @@ -378,8 +443,11 @@ static int memory_post_test3 (unsigned long start, unsigned long size) } if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } - + if (!ret) + test_log("Verifed\n"); return ret; }

@@ -389,18 +457,28 @@ static int memory_post_test4 (unsigned long start, unsigned long size) ulong *mem = (ulong *) start; ulong readback; int ret = 0; + int digit = TOTAL_PROGRESS_DOTS; + int dots = 0; + int scale = (int)(((size >> 20) / sizeof(ulong) + TOTAL_PROGRESS_DOTS - 1) / TOTAL_PROGRESS_DOTS); + + test_log("Address pattern (!offset)\n");

for (i = 0; i < size / sizeof (ulong); i++) { mem[i] = ~i; if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + test_log("Filled with pattern\n"); + digit = TOTAL_PROGRESS_DOTS; + dots = 0;

for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { readback = mem[i]; if (readback != ~i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", + test_log("Memory error at %p, " + "wrote %08lx, read %08lx !\n", mem + i, ~i, readback);

ret = -1; @@ -408,12 +486,16 @@ static int memory_post_test4 (unsigned long start, unsigned long size) } if (i % 1024 == 0) WATCHDOG_RESET (); + if ((i % (1 << 20)) == 0) + TEST_SHOW_PROGRESS(scale, dots, digit, 1); } + if (!ret) + test_log("Verifed\n");

return ret; }

-static int memory_post_tests (unsigned long start, unsigned long size) +int memory_post_tests(unsigned long start, unsigned long size) { int ret = 0;

@@ -451,33 +533,4 @@ static int memory_post_tests (unsigned long start, unsigned long size)

return ret; } - -int memory_post_test (int flags) -{ - int ret = 0; - bd_t *bd = gd->bd; - unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? - 256 << 20 : bd->bi_memsize) - (1 << 20); - - /* Limit area to be tested with the board info struct */ - if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd) - memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE; - - if (flags & POST_SLOWTEST) { - ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize); - } else { /* POST_NORMAL */ - - unsigned long i; - - for (i = 0; i < (memsize >> 20) && ret == 0; i++) { - if (ret == 0) - ret = memory_post_tests (i << 20, 0x800); - if (ret == 0) - ret = memory_post_tests ((i << 20) + 0xff800, 0x800); - } - } - - return ret; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */ +#endif /* (CONFIG_POST & CONFIG_SYS_POST_MEMORY) | defined(CONFIG_SYS_DRAM_TEST) */