Some _CLKGATE_MASK and _FRAC_MASK macros were wrong for PFD_480 and the PFD_528 macros were missing.

Fortunately, the incorrect macros weren't being used.

Since both the PFD_480 and PFD_528 registers have the same structure, and the fields are identical for [0..3] in bytes [0..3], so a single set of macros will suffice.

Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com --- No changes in V2

arch/arm/include/asm/arch-mx6/imx-regs.h | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..5fea7f2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -629,29 +629,12 @@ struct anatop_regs { u32 digprog_sololite; /* 0x280 */ };

-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 -#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 -#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 -#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 -#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 -#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 -#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 -#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 -#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 -#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 -#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 -#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 +#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) +#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) +#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) +#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) +#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) +#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))

struct iomuxc_base_regs { u32 gpr[14]; /* 0x000 */

This clock isn't feeding anything under U-Boot, so there's no point in changing it from power-on default.

Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com --- Patch V1 changed the settings to use new macros V2 simply discards the code

board/boundary/nitrogen6x/nitrogen6x.c | 5 ----- 1 file changed, 5 deletions(-)

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 79ab449..3c24367 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -622,7 +622,6 @@ int board_video_skip(void) static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg;

@@ -633,10 +632,6 @@ static void setup_display(void) reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &mxc_ccm->CCGR3);

- /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); - writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); - /* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK