[PATCH v1 1/2] x86: sipi_vector: Append appropriate suffixes
Assembler is not happy:
arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/cpu/sipi_vector.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S index 40cc27f1e1d0..fa1e6cb19af4 100644 --- a/arch/x86/cpu/sipi_vector.S +++ b/arch/x86/cpu/sipi_vector.S @@ -131,12 +131,12 @@ ap_start: jnz microcode_done
/* Determine if parallel microcode loading is allowed */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je load_microcode
/* Protect microcode loading */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode
load_microcode: @@ -154,7 +154,7 @@ load_microcode: popa
/* Unconditionally unlock microcode loading */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je microcode_done
xor %eax, %eax
Assembler is not happy:
arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/cpu/call32.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/call32.S b/arch/x86/cpu/call32.S index e185b9a42b03..e641e781c04c 100644 --- a/arch/x86/cpu/call32.S +++ b/arch/x86/cpu/call32.S @@ -32,8 +32,7 @@ cpu_call32: push %rdi /* 32-bit code segment */ lea compat(%rip), %rax push %rax - .byte 0x48 /* REX prefix to force 64-bit far return */ - retf + retfq .code32 compat: /* @@ -60,4 +59,4 @@ compat: /* Jump to the required target */ pushl %edi /* 32-bit code segment */ pushl %esi /* 32-bit target address */ - retf + retfl
On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
Assembler is not happy:
arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/call32.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Sat, Aug 1, 2020 at 8:27 AM Bin Meng bmeng.cn@gmail.com wrote:
On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
Assembler is not happy:
arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/call32.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86, thanks!
On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
Assembler is not happy:
arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/sipi_vector.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Sat, Aug 1, 2020 at 8:26 AM Bin Meng bmeng.cn@gmail.com wrote:
On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
Assembler is not happy:
arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
Fix this by adding appropriate suffixes to the assembler commands.
Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/sipi_vector.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86, thanks!
participants (2)
-
Andy Shevchenko -
Bin Meng