[U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.
For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns
All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD).
Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9ac8027..1c24da8 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
-DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0030 0x005A0E21 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 1c24da8..73317b5 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
-DATA 4 0x021b0030 0x005A0E21 +DATA 4 0x021b0030 0x005A1021 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 73317b5..51f8c35 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
-DATA 4 0x021b0030 0x005A1021 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 51f8c35..d50858d 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 +DATA 4 0x021b001c 0x19408030 +DATA 4 0x021b001c 0x19408038
DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index d50858d..f4cae5e 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x33333333 DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19408030 -DATA 4 0x021b001c 0x19408038 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048
On 01/30/2013 02:19 PM, Benoît Thébaudeau wrote:
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
Hi Benoît,
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
I'll try to scare up a board we can place on an extended burn-in.
What prompted you to walk the list? Was there a specific failure that this addressed?
Please advise,
Eric
Hi Eric,
On Friday, February 1, 2013 12:14:53 AM, Eric Nelson wrote:
On 01/30/2013 02:19 PM, Benoît Thébaudeau wrote:
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
Hi Benoît,
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
Great.
I'll try to scare up a board we can place on an extended burn-in.
That'd be good.
What prompted you to walk the list? Was there a specific failure that this addressed?
No specific failure. The only issue that I get from time to time is errors in the Linux SD driver, but this is probably unrelated.
The only reason was that I was looking for possible better performance on the RAM side because I am working on very intensive RAM accessing applications. So I checked the init code to see if it was optimal, and I found these issues besides the small possible performance gain.
So far, the default mtest passed on my board. The alternate mtest and more Linux stress tests might be interesting too.
Best regards, Benoît
Hi Benoît,
On 01/31/2013 04:25 PM, Benoît Thébaudeau wrote:
On Friday, February 1, 2013 12:14:53 AM, Eric Nelson wrote:
On 01/30/2013 02:19 PM, Benoît Thébaudeau wrote:
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Hi Benoît,
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
Great.
I'll try to scare up a board we can place on an extended burn-in.
That'd be good.
I tested one board overnight running a Linux-based memory test and things worked perfectly.
I also tested using CONFIG_SYS_ALT_MEMTEST and measured the performance difference between
Nitrogen6x board (old memory timings): U-Boot > time mtest 10000000 10400000 0 10 Testing 10000000 ... 10400000: Tested 16 iteration(s) with 0 errors.
time: 1 minutes, 11.311 seconds, 71311 ticks
SABRE Lite board (new memory timings): MX6QSABRELITE U-Boot > dcache off MX6QSABRELITE U-Boot > time mtest 10000000 10400000 0 10 Testing 10000000 ... 10400000: Tested 16 iteration(s) with 0 errors.
time: 1 minutes, 10.143 seconds, 70143 ticks
I also tested with cache enabled and things worked perfectly.
What prompted you to walk the list? Was there a specific failure that this addressed?
No specific failure. The only issue that I get from time to time is errors in the Linux SD driver, but this is probably unrelated.
The only reason was that I was looking for possible better performance on the RAM side because I am working on very intensive RAM accessing applications. So I checked the init code to see if it was optimal, and I found these issues besides the small possible performance gain.
So far, the default mtest passed on my board. The alternate mtest and more Linux stress tests might be interesting too.
For the series:
Tested-by: Eric Nelson eric.nelson@boundarydevices.com
Hi Eric,
On Friday, February 1, 2013 7:28:05 PM, Eric Nelson wrote:
Hi Benoît,
On 01/31/2013 04:25 PM, Benoît Thébaudeau wrote:
On Friday, February 1, 2013 12:14:53 AM, Eric Nelson wrote:
On 01/30/2013 02:19 PM, Benoît Thébaudeau wrote:
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
Hi Benoît,
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
Great.
I'll try to scare up a board we can place on an extended burn-in.
That'd be good.
I tested one board overnight running a Linux-based memory test and things worked perfectly.
I also tested using CONFIG_SYS_ALT_MEMTEST and measured the performance difference between
Nitrogen6x board (old memory timings): U-Boot > time mtest 10000000 10400000 0 10 Testing 10000000 ... 10400000: Tested 16 iteration(s) with 0 errors.
time: 1 minutes, 11.311 seconds, 71311 ticks
SABRE Lite board (new memory timings): MX6QSABRELITE U-Boot > dcache off MX6QSABRELITE U-Boot > time mtest 10000000 10400000 0 10 Testing 10000000 ... 10400000: Tested 16 iteration(s) with 0 errors.
time: 1 minutes, 10.143 seconds, 70143 ticks
I also tested with cache enabled and things worked perfectly.
What prompted you to walk the list? Was there a specific failure that this addressed?
No specific failure. The only issue that I get from time to time is errors in the Linux SD driver, but this is probably unrelated.
The only reason was that I was looking for possible better performance on the RAM side because I am working on very intensive RAM accessing applications. So I checked the init code to see if it was optimal, and I found these issues besides the small possible performance gain.
So far, the default mtest passed on my board. The alternate mtest and more Linux stress tests might be interesting too.
For the series:
Tested-by: Eric Nelson eric.nelson@boundarydevices.com
Thank you very much for your thorough tests!
Best regards, Benoît
On 30/01/2013 22:19, Benoît Thébaudeau wrote:
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2
Applied (whole series) to u-boot-imx, thanks.
Best regards, Stefano Babic
participants (3)
-
Benoît Thébaudeau -
Eric Nelson -
Stefano Babic