[U-Boot] [PATCH v2 0/4] arm: am33xx: Add support for dynamic programming of PLL
As am33xx supports various sysclk frequencies, this series support PLL configuration for all supported sysclk frequencies.
Changes since v1: - Converted CONFIG_SYS_MPUCLK to Kconfig - Default to 720MHz on PG 1.0 - Fixed checlpatch warnings - made bone_not_connected_to_ac_power() as static
Lokesh Vutla (4): configs: convert CONFIG_SYS_MPUCLK to Kconfig arm: am33xx: Fix MPU opp selection board: am335x: Introduce scale_vcores arm: am33xx: Add support for mulitiple PLL input frequencies
README | 5 - arch/arm/include/asm/arch-am33xx/clock.h | 7 + arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 9 +- arch/arm/include/asm/arch-am33xx/cpu.h | 8 + arch/arm/include/asm/arch-am33xx/hardware.h | 13 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 13 - arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + arch/arm/mach-omap2/Kconfig | 5 + arch/arm/mach-omap2/am33xx/board.c | 2 - arch/arm/mach-omap2/am33xx/clock_am33xx.c | 91 +++++- arch/arm/mach-omap2/am33xx/sys_info.c | 49 +++- board/ti/am335x/board.c | 313 ++++++++++++--------- board/ti/am43xx/board.c | 21 -- configs/draco_defconfig | 1 + configs/etamin_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/thuban_defconfig | 1 + include/configs/draco.h | 1 - include/configs/etamin.h | 1 - include/configs/pxm2.h | 1 - include/configs/rastaban.h | 1 - include/configs/rut.h | 1 - include/configs/thuban.h | 1 - include/power/tps65910.h | 1 + scripts/config_whitelist.txt | 1 - 27 files changed, 348 insertions(+), 203 deletions(-)
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- README | 5 ----- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 5 ----- arch/arm/mach-omap2/Kconfig | 5 +++++ configs/draco_defconfig | 1 + configs/etamin_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/thuban_defconfig | 1 + include/configs/draco.h | 1 - include/configs/etamin.h | 1 - include/configs/pxm2.h | 1 - include/configs/rastaban.h | 1 - include/configs/rut.h | 1 - include/configs/thuban.h | 1 - scripts/config_whitelist.txt | 1 - 16 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/README b/README index 0ac01363f7..a02e890057 100644 --- a/README +++ b/README @@ -4507,11 +4507,6 @@ Low Level (hardware related) configuration options: If defined, the x86 reset vector code is included. This is not needed when U-Boot is running from Coreboot.
-- CONFIG_SYS_MPUCLK - Defines the MPU clock speed (in MHz). - - NOTE : currently only supported on AM335x platforms. - - CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC: Enables the RTC32K OSC on AM33xx based plattforms
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 4c9352a2ed..c06b01b842 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -19,11 +19,6 @@ #define MPUPLL_M_550 550 #define MPUPLL_M_300 300
-/* MAIN PLL Fdll = 550 MHz, by default */ -#ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK MPUPLL_M_550 -#endif - #define UART_RESET (0x1 << 1) #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fd45fefa7f..04bc2885e4 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -147,6 +147,11 @@ config TARGET_CM_T43
endchoice
+config SYS_MPUCLK + int "MPU CLK speed" + default 550 + help + Defines the MPU clock speed (in MHz).
config TI_SECURE_DEVICE bool "HS Device Type Support" diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 148d0f2075..2526c20b1d 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_DRACO=y +CONFIG_SYS_MPUCLK=300 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 9babc09343..6b3df0f3f1 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_ETAMIN=y +CONFIG_SYS_MPUCLK=300 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 33b666316e..31e48901e3 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_PXM2=y +CONFIG_SYS_MPUCLK=720 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index a2c82826a3..1e9b0e6016 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_RASTABAN=y +CONFIG_SYS_MPUCLK=300 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 4cf8538695..d6f5e75391 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_RUT=y +CONFIG_SYS_MPUCLK=600 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 7d9e63fe5e..f591bd9965 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_THUBAN=y +CONFIG_SYS_MPUCLK=300 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/include/configs/draco.h b/include/configs/draco.h index da77c451b0..896d14f99a 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -18,7 +18,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 3383f06bf7..40c57948cc 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -69,7 +69,6 @@ CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index c8bc8f3512..57f034f0df 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -19,7 +19,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 720 #define DDR_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 266
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 16ed1f0133..99fe1616e5 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -15,7 +15,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/include/configs/rut.h b/include/configs/rut.h index bd819f1aad..8cfb73d781 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -19,7 +19,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 600 #define RUT_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 303
diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 9b73828df6..8c37d7cace 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -15,7 +15,6 @@
#include "siemens-am33x-common.h"
-#define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ed349b9e6b..7e9cf48380 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4870,7 +4870,6 @@ CONFIG_SYS_MPTPR_1BK_8K CONFIG_SYS_MPTPR_2BK_2K CONFIG_SYS_MPTPR_2BK_4K CONFIG_SYS_MPTPR_2BK_8K -CONFIG_SYS_MPUCLK CONFIG_SYS_MRAM_BASE CONFIG_SYS_MRAM_SIZE CONFIG_SYS_MRS_OFFS
On Fri, May 05, 2017 at 12:59:07PM +0530, Lokesh Vutla wrote:
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Fri, May 05, 2017 at 12:59:07PM +0530, Lokesh Vutla wrote:
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data:
MPU values for PG 2.0 and later(Package ZCZ and ZCE):
------------------------------------------------------- | | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 | -------------------------------------------------------
There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages.
[1] http://www.ti.com/lit/ds/symlink/am3356.pdf
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 2 +- arch/arm/include/asm/arch-am33xx/cpu.h | 8 ++++++ arch/arm/mach-omap2/Kconfig | 2 +- arch/arm/mach-omap2/am33xx/sys_info.c | 31 +++++++++++++++--------- include/power/tps65910.h | 1 + 5 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index c06b01b842..dfdb6c7e1b 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -16,7 +16,7 @@ #define MPUPLL_M_800 800 #define MPUPLL_M_720 720 #define MPUPLL_M_600 600 -#define MPUPLL_M_550 550 +#define MPUPLL_M_500 500 #define MPUPLL_M_300 300
#define UART_RESET (0x1 << 1) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 54f449f6e6..8cae291ea0 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -49,6 +49,14 @@ #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) #define DEVICE_ID_MASK 0x1FFF +#define PACKAGE_TYPE_SHIFT 16 +#define PACKAGE_TYPE_MASK (3 << 16) + +/* Package Type */ +#define PACKAGE_TYPE_UNDEFINED 0x0 +#define PACKAGE_TYPE_ZCZ 0x1 +#define PACKAGE_TYPE_ZCE 0x2 +#define PACKAGE_TYPE_RESERVED 0x3
/* MPU max frequencies */ #define AM335X_ZCZ_300 0x1FEF diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 04bc2885e4..a55aa1b2c6 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -149,7 +149,7 @@ endchoice
config SYS_MPUCLK int "MPU CLK speed" - default 550 + default 500 help Defines the MPU clock speed (in MHz).
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index e4fc461bd8..58bfa5c3b4 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
sil_rev = readl(&cdev->deviceid) >> 28;
- if (sil_rev == 1) - /* PG 2.0, efuse may not be set. */ - return MPUPLL_M_800; - else if (sil_rev >= 2) { + if (sil_rev == 0) { + /* No efuse in PG 1.0. Use max speed */ + return MPUPLL_M_720; + } else if (sil_rev >= 1) { /* Check what the efuse says our max speed is. */ - int efuse_arm_mpu_max_freq; + int efuse_arm_mpu_max_freq, package_type; efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >> + PACKAGE_TYPE_SHIFT; + + /* PG 2.0, efuse may not be set. */ + if (package_type == PACKAGE_TYPE_UNDEFINED || package_type == + PACKAGE_TYPE_RESERVED) + return MPUPLL_M_800; + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { case AM335X_ZCZ_1000: return MPUPLL_M_1000; @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) } }
- /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + /* unknown, use the PG1.0 max */ return MPUPLL_M_720; }
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) { - /* For PG2.1 and later, we have one set of values. */ - if (sil_rev >= 2) { + /* For PG2.0 and later, we have one set of values. */ + if (sil_rev >= 1) { switch (frequency) { case MPUPLL_M_1000: return TPS65910_OP_REG_SEL_1_3_2_5; @@ -171,12 +179,13 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) case MPUPLL_M_720: return TPS65910_OP_REG_SEL_1_2_0; case MPUPLL_M_600: + case MPUPLL_M_500: case MPUPLL_M_300: - return TPS65910_OP_REG_SEL_1_1_3; + return TPS65910_OP_REG_SEL_1_1_0; } }
- /* Default to PG1.0/PG2.0 values. */ - return TPS65910_OP_REG_SEL_1_1_3; + /* Default to PG1.0 values. */ + return TPS65910_OP_REG_SEL_1_2_6; } #endif diff --git a/include/power/tps65910.h b/include/power/tps65910.h index ca8430145b..976130dc3e 100644 --- a/include/power/tps65910.h +++ b/include/power/tps65910.h @@ -62,6 +62,7 @@ enum {
#define TPS65910_OP_REG_SEL_MASK (0x7F) #define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ +#define TPS65910_OP_REG_SEL_1_1_0 (0x2B) /* 1.1000 V */ #define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ #define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ #define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
On Fri, May 05, 2017 at 12:59:08PM +0530, Lokesh Vutla wrote:
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data:
MPU values for PG 2.0 and later(Package ZCZ and ZCE):
| | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 |
There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages.
[1] http://www.ti.com/lit/ds/symlink/am3356.pdf
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Fri, May 05, 2017 at 12:59:08PM +0530, Lokesh Vutla wrote:
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data:
MPU values for PG 2.0 and later(Package ZCZ and ZCE):
| | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 |
There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages.
[1] http://www.ti.com/lit/ds/symlink/am3356.pdf
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Update voltages before programming plls.
Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am335x/board.c | 267 +++++++++++++++++++++++++++--------------------- 1 file changed, 148 insertions(+), 119 deletions(-)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 6786229680..45c96cecaa 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -264,155 +264,184 @@ const struct dpll_params dpll_ddr_evm_sk = { const struct dpll_params dpll_ddr_bone_black = { 400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void) +const struct dpll_params *get_dpll_ddr_params(void) { - int mpu_vdd; + if (board_is_evm_sk()) + return &dpll_ddr_evm_sk; + else if (board_is_bone_lt() || board_is_icev2()) + return &dpll_ddr_bone_black; + else if (board_is_evm_15_or_later()) + return &dpll_ddr_evm_sk; + else + return &dpll_ddr; +}
- /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); +static void scale_vcores_bone(int freq) +{ + int usb_cur_lim, mpu_vdd;
- if (board_is_bone() || board_is_bone_lt()) { - /* BeagleBone PMIC Code */ - int usb_cur_lim; + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) + return;
- /* - * Only perform PMIC configurations if board rev > A1 - * on Beaglebone White - */ - if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) - return; + if (i2c_probe(TPS65217_CHIP_PM)) + return;
- if (i2c_probe(TPS65217_CHIP_PM)) + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (board_is_bone()) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) return; - - /* - * On Beaglebone White we need to ensure we have AC power - * before increasing the frequency. - */ - if (board_is_bone()) { - uchar pmic_status_reg; - if (tps65217_reg_read(TPS65217_STATUS, - &pmic_status_reg)) - return; - if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { - puts("No AC power, disabling frequency switch\n"); - return; - } + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, switching to default OPP\n"); + freq = MPUPLL_M_600; } + }
- /* - * Override what we have detected since we know if we have - * a Beaglebone Black it supports 1GHz. - */ - if (board_is_bone_lt()) - dpll_mpu_opp100.m = MPUPLL_M_1000; - - /* - * Increase USB current limit to 1300mA or 1800mA and set - * the MPU voltage controller as needed. - */ - if (dpll_mpu_opp100.m == MPUPLL_M_1000) { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; - } else { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - } + /* + * Override what we have detected since we know if we have + * a Beaglebone Black it supports 1GHz. + */ + if (board_is_bone_lt()) + freq = MPUPLL_M_1000;
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_POWER_PATH, - usb_cur_lim, - TPS65217_USB_INPUT_CUR_LIMIT_MASK)) - puts("tps65217_reg_write failure\n"); + if (freq == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + }
- /* Set DCDC3 (CORE) voltage to 1.125V */ - if (tps65217_voltage_update(TPS65217_DEFDCDC3, - TPS65217_DCDC_VOLT_SEL_1125MV)) { - puts("tps65217_voltage_update failure\n"); - return; - } + switch (freq) { + case MPUPLL_M_1000: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_800: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_720: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_600: + case MPUPLL_M_500: + case MPUPLL_M_300: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + break; + }
- /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n");
- /* Set DCDC2 (MPU) voltage */ - if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { - puts("tps65217_voltage_update failure\n"); - return; - } + /* Set DCDC3 (CORE) voltage to 1.10V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1100MV)) { + puts("tps65217_voltage_update failure\n"); + return; + }
- /* - * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. - * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. - */ - if (board_is_bone()) { - if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS1, - TPS65217_LDO_VOLTAGE_OUT_3_3, - TPS65217_LDO_MASK)) - puts("tps65217_reg_write failure\n"); - } else { - if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS1, - TPS65217_LDO_VOLTAGE_OUT_1_8, - TPS65217_LDO_MASK)) - puts("tps65217_reg_write failure\n"); - } + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + }
+ /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (board_is_bone()) { if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS2, + TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); } else { - int sil_rev; + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + }
- /* - * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all - * MPU frequencies we support we use a CORE voltage of - * 1.1375V. For MPU voltage we need to switch based on - * the frequency we are running at. - */ - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) - return; + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); +}
- /* - * Depending on MPU clock and PG we will need a different - * VDD to drive at that speed. - */ - sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, - dpll_mpu_opp100.m); +void scale_vcores_generic(int freq) +{ + int sil_rev, mpu_vdd;
- /* Tell the TPS65910 to use i2c */ - tps65910_set_i2c_control(); + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.10V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return;
- /* First update MPU voltage. */ - if (tps65910_voltage_update(MPU, mpu_vdd)) - return; + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
- /* Second, update the CORE voltage. */ - if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) - return; + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control();
- /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - } + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) + return;
- /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
-const struct dpll_params *get_dpll_ddr_params(void) +void gpi2c_init(void) { - if (board_is_evm_sk()) - return &dpll_ddr_evm_sk; - else if (board_is_bone_lt() || board_is_icev2()) - return &dpll_ddr_bone_black; - else if (board_is_evm_15_or_later()) - return &dpll_ddr_evm_sk; + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (first_time) { + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + first_time = false; + } +} + +void scale_vcores(void) +{ + int freq; + + gpi2c_init(); + freq = am335x_get_efuse_mpu_max_freq(cdev); + + if (board_is_bone()) + scale_vcores_bone(freq); else - return &dpll_ddr; + scale_vcores_generic(freq); }
void set_uart_mux_conf(void)
On Fri, May 05, 2017 at 12:59:09PM +0530, Lokesh Vutla wrote:
Update voltages before programming plls.
Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot/master, thanks!
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-am33xx/clock.h | 7 ++ arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 2 + arch/arm/include/asm/arch-am33xx/hardware.h | 13 ++++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 13 ---- arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + arch/arm/mach-omap2/am33xx/board.c | 2 - arch/arm/mach-omap2/am33xx/clock_am33xx.c | 91 +++++++++++++++++++--- arch/arm/mach-omap2/am33xx/sys_info.c | 18 +++++ board/ti/am335x/board.c | 74 ++++++++++++------ board/ti/am43xx/board.c | 21 ----- 10 files changed, 173 insertions(+), 69 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index acf3fd55a8..19ccf5c8db 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -12,6 +12,7 @@ #define _CLOCKS_H_
#include <asm/arch/clocks_am33xx.h> +#include <asm/arch/hardware.h>
#ifdef CONFIG_TI81XX #include <asm/arch/clock_ti81xx.h> @@ -103,6 +104,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; +extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; +extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
extern struct cm_wkuppll *const cmwkup;
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index dfdb6c7e1b..653ec1b239 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -26,6 +26,8 @@ #define CM_DLL_CTRL_NO_OVERRIDE 0x0 #define CM_DLL_READYST 0x4
+#define NUM_OPPS 6 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index dd950e5ac4..3437e6116d 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -61,5 +61,18 @@ /* CPSW Config space */ #define CPSW_BASE 0x4A100000
+/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + int clk_get(int clk); #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index a7da6b5cfd..af69ac6f2c 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -85,19 +85,6 @@ #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
-/* Control status register */ -#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) -#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 -#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) -#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 -#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) -#define CTRL_SYSBOOT_15_14_SHIFT 22 - -#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 -#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 - -#define NUM_CRYSTAL_FREQ 0x4 - /* EDMA3 Base Address */ #define EDMA3_BASE 0x49000000
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 903398fe8f..4e78aafb0b 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -46,3 +46,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); void enable_usb_clocks(int index); void disable_usb_clocks(int index); void do_board_detect(void); +u32 get_sys_clk_index(void); diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 956fcc8b95..f674ab029c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -243,8 +243,6 @@ int board_early_init_f(void) */ __weak void am33xx_spl_board_init(void) { - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); }
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 7b841b2d55..1780bbdb6f 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -10,6 +10,7 @@
#include <common.h> #include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/io.h> @@ -55,26 +56,94 @@ struct dpll_params dpll_mpu_opp100 = { CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_core_opp100 = { 1000, OSC-1, -1, -1, 10, 8, 4}; -const struct dpll_params dpll_mpu = { - MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - 50, OSC-1, -1, -1, 1, 1, 1}; -const struct dpll_params dpll_per = { - 960, OSC-1, 5, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_mpu_params(void) + +const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */ + {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */ + {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */ + {125, 2, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */ + {144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */ + {32, 0, 1, -1, -1, -1, -1}, /* OPP TB */ + {40, 0, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */ + {360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */ + {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */ + {500, 12, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */ + {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */ + {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = { + {505, 15, 2, -1, -1, -1, -1}, /*19.2*/ + {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */ + {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = { + {125, 5, 1, -1, -1, -1, -1}, /*19.2*/ + {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */ + {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */ + {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, -1, -1, -1}, /*19.2*/ + {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +__weak const struct dpll_params *get_dpll_mpu_params(void) { - return &dpll_mpu; + return &dpll_mpu_opp100; }
const struct dpll_params *get_dpll_core_params(void) { - return &dpll_core; + int ind = get_sys_clk_index(); + + return &dpll_core_1000MHz[ind]; }
const struct dpll_params *get_dpll_per_params(void) { - return &dpll_per; + int ind = get_sys_clk_index(); + + return &dpll_per_192MHz[ind]; }
void setup_clocks_for_console(void) diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 58bfa5c3b4..564bae6793 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -68,6 +68,24 @@ u32 get_sysboot_value(void) return readl(&cstat->statusreg) & SYSBOOT_MASK; }
+u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg); + +#ifdef CONFIG_AM43XX + u32 src; + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ +#endif + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + + #ifdef CONFIG_DISPLAY_CPUINFO static char *cpu_revs[] = { "1.0", diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 45c96cecaa..3e81521399 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -256,24 +256,62 @@ int spl_start_uboot(void) } #endif
-#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = { - 266, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_evm_sk = { - 303, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_bone_black = { - 400, OSC-1, 1, -1, -1, -1, -1}; - const struct dpll_params *get_dpll_ddr_params(void) { + int ind = get_sys_clk_index(); + if (board_is_evm_sk()) - return &dpll_ddr_evm_sk; + return &dpll_ddr3_303MHz[ind]; else if (board_is_bone_lt() || board_is_icev2()) - return &dpll_ddr_bone_black; + return &dpll_ddr3_400MHz[ind]; else if (board_is_evm_15_or_later()) - return &dpll_ddr_evm_sk; + return &dpll_ddr3_303MHz[ind]; else - return &dpll_ddr; + return &dpll_ddr2_266MHz[ind]; +} + +static u8 bone_not_connected_to_ac_power(void) +{ + if (board_is_bone()) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) + return 1; + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, switching to default OPP\n"); + return 1; + } + } + return 0; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int ind = get_sys_clk_index(); + int freq = am335x_get_efuse_mpu_max_freq(cdev); + + if (bone_not_connected_to_ac_power()) + freq = MPUPLL_M_600; + + if (board_is_bone_lt()) + freq = MPUPLL_M_1000; + + switch (freq) { + case MPUPLL_M_1000: + return &dpll_mpu_opp[ind][5]; + case MPUPLL_M_800: + return &dpll_mpu_opp[ind][4]; + case MPUPLL_M_720: + return &dpll_mpu_opp[ind][3]; + case MPUPLL_M_600: + return &dpll_mpu_opp[ind][2]; + case MPUPLL_M_500: + return &dpll_mpu_opp100; + case MPUPLL_M_300: + return &dpll_mpu_opp[ind][0]; + } + + return &dpll_mpu_opp[ind][0]; }
static void scale_vcores_bone(int freq) @@ -294,16 +332,8 @@ static void scale_vcores_bone(int freq) * On Beaglebone White we need to ensure we have AC power * before increasing the frequency. */ - if (board_is_bone()) { - uchar pmic_status_reg; - if (tps65217_reg_read(TPS65217_STATUS, - &pmic_status_reg)) - return; - if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { - puts("No AC power, switching to default OPP\n"); - freq = MPUPLL_M_600; - } - } + if (bone_not_connected_to_ac_power()) + freq = MPUPLL_M_600;
/* * Override what we have detected since we know if we have diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 390cc168cd..299a72ad72 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -49,8 +49,6 @@ void do_board_detect(void)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define NUM_OPPS 6 - const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ @@ -317,25 +315,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) return; }
-/* - * get_sys_clk_index : returns the index of the sys_clk read from - * ctrl status register. This value is either - * read from efuse or sysboot pins. - */ -static u32 get_sys_clk_index(void) -{ - struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; - u32 ind = readl(&ctrl->statusreg), src; - - src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; - if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ - return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> - CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); - else /* Value read from SYS BOOT pins */ - return ((ind & CTRL_SYSBOOT_15_14_MASK) >> - CTRL_SYSBOOT_15_14_SHIFT); -} - const struct dpll_params *get_dpll_ddr_params(void) { int ind = get_sys_clk_index();
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
U-Boot SPL 2017.05-00344-gfbd6295da4 (Jun 07 2017 - 20:19:09) Trying to boot from MMC1 *** Warning - bad CRC, using default environment
reading u-boot.img reading u-boot.img
U-Boot 2017.05-00344-gfbd6295da4 (Jun 07 2017 - 20:19:09 +0200)
CPU : AM335X-GP rev 2.1 I2C: ready DRAM: 512 MiB No match for driver 'omap_hsmmc' No match for driver 'omap_hsmmc' Some drivers were not found MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 *** Warning - bad CRC, using default environment
<ethaddr> not set. Validating first E-fuse MAC Net: cpsw, usb_ether Press SPACE to abort autoboot in 2 seconds data abort pc : [<9ff61cae>] lr : [<9ff5c743>] reloc pc : [<80810cae>] lr : [<8080b743>] sp : 9df30bb8 ip : 9ff9e8f0 fp : 00000000 r10: 9df3b0b0 r9 : 9df30ed8 r8 : 9df3a1a8 r7 : 9df3b100 r6 : 9df3b0b8 r5 : 544c4e00 r4 : 9ff9e810 r3 : 9df3b0a8 r2 : 00000000 r1 : 00000020 r0 : 9ff9e820 Flags: nzCv IRQs off FIQs on Mode SVC_32 Resetting CPU ...
resetting ...
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
------------8<------------------8<--------------------------
From 519035c54cef3f9156303b70322c02f10ec69e00 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla lokeshvutla@ti.com Date: Thu, 8 Jun 2017 09:34:52 +0530 Subject: [PATCH] board: am335x: Do not harcode mpu freq for beagleboneblack
For all am335x boards the mpu frequency is determined by readin efuse. But for beagleboneblack it is hard coded to 1GHz irrespective of efuse settings. Due to which some boards fails to boot with not recommended frequency. Fix it to use efuse to determine mpu frequency.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am335x/board.c | 10 ---------- 1 file changed, 10 deletions(-)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 517965c0f0..4cf6617efb 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -294,9 +294,6 @@ const struct dpll_params *get_dpll_mpu_params(void) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
- if (board_is_bone_lt()) - freq = MPUPLL_M_1000; - switch (freq) { case MPUPLL_M_1000: return &dpll_mpu_opp[ind][5]; @@ -336,13 +333,6 @@ static void scale_vcores_bone(int freq) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
- /* - * Override what we have detected since we know if we have - * a Beaglebone Black it supports 1GHz. - */ - if (board_is_bone_lt()) - freq = MPUPLL_M_1000; - if (freq == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
On Thu, 8 Jun 2017 10:17:09 +0530 Lokesh Vutla lokeshvutla@ti.com wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
This doesn't fix the issues, I'm seeing the same behavior. Since we are in rc release maybe it's best to revert the commit and properly implement the changes after 2017.07 is out ?
Thanks,
------------8<------------------8<-------------------------- From 519035c54cef3f9156303b70322c02f10ec69e00 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla lokeshvutla@ti.com Date: Thu, 8 Jun 2017 09:34:52 +0530 Subject: [PATCH] board: am335x: Do not harcode mpu freq for beagleboneblack
For all am335x boards the mpu frequency is determined by readin efuse. But for beagleboneblack it is hard coded to 1GHz irrespective of efuse settings. Due to which some boards fails to boot with not recommended frequency. Fix it to use efuse to determine mpu frequency.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
board/ti/am335x/board.c | 10 ---------- 1 file changed, 10 deletions(-)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 517965c0f0..4cf6617efb 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -294,9 +294,6 @@ const struct dpll_params *get_dpll_mpu_params(void) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
- if (board_is_bone_lt())
freq = MPUPLL_M_1000;- switch (freq) { case MPUPLL_M_1000: return &dpll_mpu_opp[ind][5];
@@ -336,13 +333,6 @@ static void scale_vcores_bone(int freq) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
- /*
* Override what we have detected since we know if we have* a Beaglebone Black it supports 1GHz.*/- if (board_is_bone_lt())
freq = MPUPLL_M_1000;- if (freq == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
-- 2.11.0
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Last working U-Boot test, see [2]
Sorry, did not looked earlier at it ... I really need to find time again for my testsetup as at91 based boards also not running currently :-(
Ok, my BBB in the lab is running, also with current U-Boot, but I see
U-Boot 2017.07-rc1-00075-g156d64f (Jun 09 2017 - 05:48:18 +0200)
CPU : AM335X-GP rev 2.1 Model: TI AM335x BeagleBone Black DRAM: 512 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Unable to use mmc 0:1 for loading the env ** Using default environment
ERROR: No USB device found
at drivers/usb/gadget/ether.c:2709/usb_ether_init() <ethaddr> not set. Validating first E-fuse MAC Net: CACHE: Misaligned operation at range [9df31580, 9df31624] eth0: ethernet@4a100000
And my tbot tests breaking when using ethernet! For example:
=> print tbot_cmp_uboot tbot_cmp_uboot=run cmp_uboot => print cmp_uboot cmp_uboot=tftp ${cmp_addr_r} ${ubfile};cmp.b ${load_addr_r} ${cmp_addr_r} ${filesize} => => run tbot_upd_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x81000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) writing u-boot.img 654708 bytes written => run tbot_cmp_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x82000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) byte at 0x81000618 (0x33) != byte at 0x82000618 (0x74) Total of 1560 byte(s) were the same =>
So simply load file 'bbb/tbot/u-boot.img' twice with tftp and compare fails ... but the image boots ...
bye, Heiko
[1] http://xeidos.ddns.net/buildbot/tgrid bbb U-Boot Test = "bbb_ub"
[2] last working U-Boot test http://xeidos.ddns.net/tests/test_db_auslesen.php#319
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Thanks and regards, Lokesh
Last working U-Boot test, see [2]
Sorry, did not looked earlier at it ... I really need to find time again for my testsetup as at91 based boards also not running currently :-(
Ok, my BBB in the lab is running, also with current U-Boot, but I see
U-Boot 2017.07-rc1-00075-g156d64f (Jun 09 2017 - 05:48:18 +0200)
CPU : AM335X-GP rev 2.1 Model: TI AM335x BeagleBone Black DRAM: 512 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Unable to use mmc 0:1 for loading the env ** Using default environment
ERROR: No USB device found
at drivers/usb/gadget/ether.c:2709/usb_ether_init() <ethaddr> not set. Validating first E-fuse MAC Net: CACHE: Misaligned operation at range [9df31580, 9df31624] eth0: ethernet@4a100000
And my tbot tests breaking when using ethernet! For example:
=> print tbot_cmp_uboot tbot_cmp_uboot=run cmp_uboot => print cmp_uboot cmp_uboot=tftp ${cmp_addr_r} ${ubfile};cmp.b ${load_addr_r} ${cmp_addr_r} ${filesize} => => run tbot_upd_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x81000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) writing u-boot.img 654708 bytes written => run tbot_cmp_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x82000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) byte at 0x81000618 (0x33) != byte at 0x82000618 (0x74) Total of 1560 byte(s) were the same =>
So simply load file 'bbb/tbot/u-boot.img' twice with tftp and compare fails ... but the image boots ...
bye, Heiko
[1] http://xeidos.ddns.net/buildbot/tgrid bbb U-Boot Test = "bbb_ub"
[2] last working U-Boot test http://xeidos.ddns.net/tests/test_db_auslesen.php#319
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
> am335x supports various sysclk frequencies which can be determined > using sysboot pins. PLLs should be configures based on this > sysclk frequency. Add PLL configurations for all supported > frequencies. > > Signed-off-by: Lokesh Vutla lokeshvutla@ti.com > Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
bye, Heiko
Thanks and regards, Lokesh
Last working U-Boot test, see [2]
Sorry, did not looked earlier at it ... I really need to find time again for my testsetup as at91 based boards also not running currently :-(
Ok, my BBB in the lab is running, also with current U-Boot, but I see
U-Boot 2017.07-rc1-00075-g156d64f (Jun 09 2017 - 05:48:18 +0200)
CPU : AM335X-GP rev 2.1 Model: TI AM335x BeagleBone Black DRAM: 512 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Unable to use mmc 0:1 for loading the env ** Using default environment
ERROR: No USB device found
at drivers/usb/gadget/ether.c:2709/usb_ether_init() <ethaddr> not set. Validating first E-fuse MAC Net: CACHE: Misaligned operation at range [9df31580, 9df31624] eth0: ethernet@4a100000
And my tbot tests breaking when using ethernet! For example:
=> print tbot_cmp_uboot tbot_cmp_uboot=run cmp_uboot => print cmp_uboot cmp_uboot=tftp ${cmp_addr_r} ${ubfile};cmp.b ${load_addr_r} ${cmp_addr_r} ${filesize} => => run tbot_upd_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x81000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) writing u-boot.img 654708 bytes written => run tbot_cmp_uboot link up on port 0, speed 100, full duplex Using ethernet@4a100000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.95 Filename 'bbb/tbot/u-boot.img'. Load address: 0x82000000 Loading: ############################################# 3.2 MiB/s done Bytes transferred = 654708 (9fd74 hex) byte at 0x81000618 (0x33) != byte at 0x82000618 (0x74) Total of 1560 byte(s) were the same =>
So simply load file 'bbb/tbot/u-boot.img' twice with tftp and compare fails ... but the image boots ...
bye, Heiko
[1] http://xeidos.ddns.net/buildbot/tgrid bbb U-Boot Test = "bbb_ub"
[2] last working U-Boot test http://xeidos.ddns.net/tests/test_db_auslesen.php#319
On Fri, Jun 09, 2017 at 12:22:44PM +0200, Heiko Schocher wrote:
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
>On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote: > >>am335x supports various sysclk frequencies which can be determined >>using sysboot pins. PLLs should be configures based on this >>sysclk frequency. Add PLL configurations for all supported >>frequencies. >> >>Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>Reviewed-by: Tom Rini trini@konsulko.com > >Applied to u-boot/master, thanks! > >-- >Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
How do you have the BBB configured such that you can recover it from a bad U-Boot, automatically? Thanks!
Hello Tom,
Am 09.06.2017 um 13:20 schrieb Tom Rini:
On Fri, Jun 09, 2017 at 12:22:44PM +0200, Heiko Schocher wrote:
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote: > On Fri, 12 May 2017 13:20:50 -0400 > Tom Rini trini@konsulko.com wrote: > >> On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote: >> >>> am335x supports various sysclk frequencies which can be determined >>> using sysboot pins. PLLs should be configures based on this >>> sysclk frequency. Add PLL configurations for all supported >>> frequencies. >>> >>> Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>> Reviewed-by: Tom Rini trini@konsulko.com >> >> Applied to u-boot/master, thanks! >> >> -- >> Tom > > Hello, > > This appears to break beaglebone black support, reverting this commit > make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
How do you have the BBB configured such that you can recover it from a bad U-Boot, automatically? Thanks!
That;s exactly the reason, why I did not started a "git bisect", as this is not solved for the BBB in our lab. Wolfgang bought such a Airflash card, but we did not found time to try it.
bye, Heiko
On Fri, Jun 09, 2017 at 05:55:10PM +0200, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 13:20 schrieb Tom Rini:
On Fri, Jun 09, 2017 at 12:22:44PM +0200, Heiko Schocher wrote:
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote: > > >On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote: >>On Fri, 12 May 2017 13:20:50 -0400 >>Tom Rini trini@konsulko.com wrote: >> >>>On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote: >>> >>>>am335x supports various sysclk frequencies which can be determined >>>>using sysboot pins. PLLs should be configures based on this >>>>sysclk frequency. Add PLL configurations for all supported >>>>frequencies. >>>> >>>>Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>>>Reviewed-by: Tom Rini trini@konsulko.com >>> >>>Applied to u-boot/master, thanks! >>> >>>-- >>>Tom >> >> Hello, >> >> This appears to break beaglebone black support, reverting this commit >>make u-boot works again. > >hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even >efuse say it is not supported(I am not sure why this is being done, may >be Tom can give more details). Even in kernel I see that cpufreq is >reading efuse to determine mpu frequency. Now that we have jitter >optimized pll configurations, looks like unsupported freq is causing an >issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
How do you have the BBB configured such that you can recover it from a bad U-Boot, automatically? Thanks!
That;s exactly the reason, why I did not started a "git bisect", as this is not solved for the BBB in our lab. Wolfgang bought such a Airflash card, but we did not found time to try it.
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
The button is routed to the expansion header..
I've got a few hot-wired..
GND: P8_43
Regards,
On Fri, Jun 09, 2017 at 02:45:32PM -0500, Robert Nelson wrote:
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
The button is routed to the expansion header..
I've got a few hot-wired..
GND: P8_43
Ah, so if I wire P8_43 to ground, the button will always be pressed? Neat, I need to go try that..
On Fri, Jun 9, 2017 at 3:00 PM, Tom Rini trini@konsulko.com wrote:
On Fri, Jun 09, 2017 at 02:45:32PM -0500, Robert Nelson wrote:
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
The button is routed to the expansion header..
I've got a few hot-wired..
GND: P8_43
Ah, so if I wire P8_43 to ground, the button will always be pressed? Neat, I need to go try that..
Correct!
Then eMMC won't be even looked at:
<normal> mmc1 mmc0 usart0 usb0
<push/button, P8_43/GND> SPI0 mmc0 usb0 uart0
Regards,
Hello Robert,
Am 09.06.2017 um 22:00 schrieb Tom Rini:
On Fri, Jun 09, 2017 at 02:45:32PM -0500, Robert Nelson wrote:
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
The button is routed to the expansion header..
I've got a few hot-wired..
GND: P8_43
Ah, so if I wire P8_43 to ground, the button will always be pressed? Neat, I need to go try that..
So I can switch between eMMC and SD card bootmode if I connect a relais?
That would be great. So I can in case I see a problem switch to other bootmode and can automate git bisect. Also it would be possible to verify both bootmodes.
I have to wait to try this, until Wolfgang is back from vacation, as I have no physical access to the bbb.
Thanks for this hint!
bye, Heiko
On Fri, 9 Jun 2017 15:13:05 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, Jun 09, 2017 at 05:55:10PM +0200, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 13:20 schrieb Tom Rini:
On Fri, Jun 09, 2017 at 12:22:44PM +0200, Heiko Schocher wrote:
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 02:45 schrieb Tom Rini: >On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote: >> >> >>On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote: >>>On Fri, 12 May 2017 13:20:50 -0400 >>>Tom Rini trini@konsulko.com wrote: >>> >>>>On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote: >>>> >>>>>am335x supports various sysclk frequencies which can be determined >>>>>using sysboot pins. PLLs should be configures based on this >>>>>sysclk frequency. Add PLL configurations for all supported >>>>>frequencies. >>>>> >>>>>Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>>>>Reviewed-by: Tom Rini trini@konsulko.com >>>> >>>>Applied to u-boot/master, thanks! >>>> >>>>-- >>>>Tom >>> >>> Hello, >>> >>> This appears to break beaglebone black support, reverting this commit >>>make u-boot works again. >> >>hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even >>efuse say it is not supported(I am not sure why this is being done, may >>be Tom can give more details). Even in kernel I see that cpufreq is >>reading efuse to determine mpu frequency. Now that we have jitter >>optimized pll configurations, looks like unsupported freq is causing an >>issue. Can you see if the below patch helps? > >Well, in the kernel, did anyone poke the Beagleboard folks about this, >before pushing the change? There's BBB shipping with chips that did not >have their efuses set, hence the way things were structured in U-Boot.
I have runnint tbot tests on a BBB [1] ... and yes, currently test is red = bad ... :-(
Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
How do you have the BBB configured such that you can recover it from a bad U-Boot, automatically? Thanks!
That;s exactly the reason, why I did not started a "git bisect", as this is not solved for the BBB in our lab. Wolfgang bought such a Airflash card, but we did not found time to try it.
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
-- Tom
BBB can directly boot from SD if you leave the eMMC blank, that's what I do on all my BBB.
On Fri, Jun 09, 2017 at 09:53:14PM +0200, Emmanuel Vadot wrote:
On Fri, 9 Jun 2017 15:13:05 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, Jun 09, 2017 at 05:55:10PM +0200, Heiko Schocher wrote:
Hello Tom,
Am 09.06.2017 um 13:20 schrieb Tom Rini:
On Fri, Jun 09, 2017 at 12:22:44PM +0200, Heiko Schocher wrote:
Hello Lokesh,
Am 09.06.2017 um 11:25 schrieb Lokesh Vutla:
On Friday 09 June 2017 09:30 AM, Heiko Schocher wrote: >Hello Tom, > >Am 09.06.2017 um 02:45 schrieb Tom Rini: >>On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote: >>> >>> >>>On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote: >>>>On Fri, 12 May 2017 13:20:50 -0400 >>>>Tom Rini trini@konsulko.com wrote: >>>> >>>>>On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote: >>>>> >>>>>>am335x supports various sysclk frequencies which can be determined >>>>>>using sysboot pins. PLLs should be configures based on this >>>>>>sysclk frequency. Add PLL configurations for all supported >>>>>>frequencies. >>>>>> >>>>>>Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>>>>>Reviewed-by: Tom Rini trini@konsulko.com >>>>> >>>>>Applied to u-boot/master, thanks! >>>>> >>>>>-- >>>>>Tom >>>> >>>> Hello, >>>> >>>> This appears to break beaglebone black support, reverting this commit >>>>make u-boot works again. >>> >>>hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even >>>efuse say it is not supported(I am not sure why this is being done, may >>>be Tom can give more details). Even in kernel I see that cpufreq is >>>reading efuse to determine mpu frequency. Now that we have jitter >>>optimized pll configurations, looks like unsupported freq is causing an >>>issue. Can you see if the below patch helps? >> >>Well, in the kernel, did anyone poke the Beagleboard folks about this, >>before pushing the change? There's BBB shipping with chips that did not >>have their efuses set, hence the way things were structured in U-Boot. > >I have runnint tbot tests on a BBB [1] ... and yes, currently test >is red = bad ... :-( > >Not sure, if it is this patch ...
Yeah, I don't think this is the patch causing the issue. AM335x-evm boots fine for me. There are similar boot failures reported[1] on NVIDIA platforms as well. Not sure if we are hitting the same issue. Ill did more into this and update you guys.
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg252698.html
Time for using tbot and automated git bisect testcase ;-)
How do you have the BBB configured such that you can recover it from a bad U-Boot, automatically? Thanks!
That;s exactly the reason, why I did not started a "git bisect", as this is not solved for the BBB in our lab. Wolfgang bought such a Airflash card, but we did not found time to try it.
Ah, the problem with BBB is that it wants to boot from eMMC, not SD, unless the button is pressed. It's possible, and I'd have to look at the TRM and maybe the schematic, to see about changing the order, or being able to remote boot it with a blank eMMC.
BBB can directly boot from SD if you leave the eMMC blank, that's what I do on all my BBB.
I think I knew that, and forgot. Thanks! Time to order up more WiFi SD cards I suspect...
On Thu, Jun 8, 2017 at 7:45 PM, Tom Rini trini@konsulko.com wrote:
On Thu, Jun 08, 2017 at 10:17:09AM +0530, Lokesh Vutla wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
Well, in the kernel, did anyone poke the Beagleboard folks about this, before pushing the change? There's BBB shipping with chips that did not have their efuses set, hence the way things were structured in U-Boot.
Part of the fun, most shipping BeagleBone and Varients have the proper efuse'ed silicon nowadays..
I think all my Rev B's (2GB eMMC which all 100% have the non-efused silicon) are in my up-time test farm at home. I might have an old one somewhere here at work.
But yes, all BeagleBone am335x's where pinned at TI for 1Ghz support before TI started efuse'ing
Regards,
On Wed, Jun 7, 2017 at 11:47 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
In the kernel, we are re-enabling the 1GHz option in the BoneBlack's device tree blob:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/ar...
Regards,
On Wed, Jun 7, 2017 at 11:47 PM, Lokesh Vutla lokeshvutla@ti.com wrote:
On Thursday 08 June 2017 12:20 AM, Emmanuel Vadot wrote:
On Fri, 12 May 2017 13:20:50 -0400 Tom Rini trini@konsulko.com wrote:
On Fri, May 05, 2017 at 12:59:10PM +0530, Lokesh Vutla wrote:
am335x supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configures based on this sysclk frequency. Add PLL configurations for all supported frequencies.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
-- Tom
Hello,
This appears to break beaglebone black support, reverting this commit make u-boot works again.
hmm..I see the problem. Here we are hard coding MPU freq to 1GHz even efuse say it is not supported(I am not sure why this is being done, may be Tom can give more details). Even in kernel I see that cpufreq is reading efuse to determine mpu frequency. Now that we have jitter optimized pll configurations, looks like unsupported freq is causing an issue. Can you see if the below patch helps?
------------8<------------------8<-------------------------- From 519035c54cef3f9156303b70322c02f10ec69e00 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla lokeshvutla@ti.com Date: Thu, 8 Jun 2017 09:34:52 +0530 Subject: [PATCH] board: am335x: Do not harcode mpu freq for beagleboneblack
For all am335x boards the mpu frequency is determined by readin efuse. But for beagleboneblack it is hard coded to 1GHz irrespective of efuse settings. Due to which some boards fails to boot with not recommended frequency. Fix it to use efuse to determine mpu frequency.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
board/ti/am335x/board.c | 10 ---------- 1 file changed, 10 deletions(-)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 517965c0f0..4cf6617efb 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -294,9 +294,6 @@ const struct dpll_params *get_dpll_mpu_params(void) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
if (board_is_bone_lt())freq = MPUPLL_M_1000;switch (freq) { case MPUPLL_M_1000: return &dpll_mpu_opp[ind][5];@@ -336,13 +333,6 @@ static void scale_vcores_bone(int freq) if (bone_not_connected_to_ac_power()) freq = MPUPLL_M_600;
/** Override what we have detected since we know if we have* a Beaglebone Black it supports 1GHz.*/if (board_is_bone_lt())freq = MPUPLL_M_1000;if (freq == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;-- 2.11.0
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Tested-by: Robert Nelson robertcnelson@gmail.com
On my BBB A5A (2GB), PG 2.0 non-efused silicon..
***************************
U-Boot SPL 2017.07-rc1-00075-g156d64fa55-dirty (Jun 09 2017 - 12:31:11) Trying to boot from MMC1
** Unable to use mmc 0:1 for loading the env ** Using default environment
U-Boot 2017.07-rc1-00075-g156d64fa55-dirty (Jun 09 2017 - 12:31:11 -0500)
CPU : AM335X-GP rev 2.0 Model: TI AM335x BeagleBone Black DRAM: 512 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
** Unable to use mmc 0:1 for loading the env ** Using default environment
ERROR: No USB device found
at drivers/usb/gadget/ether.c:2709/usb_ether_init() <ethaddr> not set. Validating first E-fuse MAC Net: CACHE: Misaligned operation at range [9df32580, 9df32624] eth0: ethernet@4a100000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 ** File not found boot.scr ** ** Unrecognized filesystem type ** switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... switch to partitions #0, OK
***************************
Regards,
participants (5)
-
Emmanuel Vadot -
Heiko Schocher -
Lokesh Vutla -
Robert Nelson -
Tom Rini