From: Kautuk Consul kconsul@ventanamicro.com Sent: Friday, September 23, 2022 3:03 PM To: Rayagonda Kokatanur rayagonda.kokatanur@broadcom.com; Sean Anderson sean.anderson@seco.com; Rick Jian-Zhi Chen(陳建志) rick@andestech.com; Leo Yu-Chi Liang(梁育齊) ycliang@andestech.com; Bin Meng bmeng.cn@gmail.com; Simon Glass sjg@chromium.org; Ilias Apalodimas ilias.apalodimas@linaro.org; Alexandru Gagniuc mr.nuke.me@gmail.com; Philippe Reynes philippe.reynes@softathome.com; Heinrich Schuchardt xypron.glpk@gmx.de; Rasmus Villemoes rasmus.villemoes@prevas.dk; Eugen Hristev eugen.hristev@microchip.com; Stefan Roese sr@denx.de; Loic Poulain loic.poulain@linaro.org; Peng Fan peng.fan@nxp.com; Michal Simek michal.simek@amd.com Cc: u-boot@lists.denx.de; Kautuk Consul kconsul@ventanamicro.com; Anup Patel apatel@ventanamicro.com Subject: [PATCH v5 2/3] arch/riscv: add semihosting support for RISC-V

We add RISC-V semihosting based serial console for JTAG based early debugging.

The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-...

Signed-off-by: Anup Patel apatel@ventanamicro.com Signed-off-by: Kautuk Consul kconsul@ventanamicro.com

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arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 ++ arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++ arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++ lib/Kconfig | 10 +++++----- 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c

Reviewed-by: Rick Chen rick@andestech.com