[U-Boot] [PATCH 1/2] sunxi: axp152: Keep DRAM / Vddr at bootloader set value
Some fex files contain wrong values, causing stability issues.
Signed-off-by: Hans de Goede hdegoede@redhat.com --- drivers/power/axp152.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index 77132e1..3b8e68f 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -541,15 +541,17 @@ static struct regulator_init_data regl_init_data[AXP152_REGULATOR_COUNT] = { .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, } }, - [axp152_dcdc3] = { /* Vddr, power on 1.5V, Android from fex */ + [axp152_dcdc3] = { /* Vddr, power on 1.5V, use u-boot value */ .num_consumer_supplies = 1, .consumer_supplies = &axp152_dcdc3_supply, .constraints = { - .min_uV = 1500 * 1000, - .max_uV = 1500 * 1000, + .min_uV = 1000 * 1000, + .max_uV = 1600 * 1000, .always_on = 1, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + /* + * We do not allow changing the DRAM voltage, because + * of stability, so no REGULATOR_CHANGE_VOLTAGE. + */ } }, [axp152_dcdc4] = { /* Vcpu, power on 1.25V, Android from fex */ @@ -622,11 +624,11 @@ static int __init axp_board_init(void)
/* Note we ignore the dcdc2_vol key as dcdc2 is set by the dvfs code */
- ret = script_parser_fetch("target", "dcdc3_vol", &val, sizeof(int)); - if (ret == 0) { - regl_init_data[axp152_dcdc3].constraints.min_uV = val * 1000; - regl_init_data[axp152_dcdc3].constraints.max_uV = val * 1000; - } + /* + * Note we ignore the dcdc3_vol key as that sometimes contains wrong + * values make the dram unstable, instead we stick with the bootloader + * set voltage. + */
ret = script_parser_fetch("target", "dcdc4_vol", &val, sizeof(int)); if (ret == 0) {
Before the u-boot dram cleanup u-boot would always set PLL5 factor m to 2 (reg value 1) and div p to 1, and get_cmu_clk in the nand code would calculate the pll5p clk like this:
clk = 24 * factor_n * factor_k / div_p / factor_m;
aka:
clk = 24 * factor_n * factor_k / (div_p * factor_m);
This is wrong however, factor_m is not used to calculate pll5p, and div_p is not a straight divider, but it divides by 2 ^ div_p. Since with the m == 2 and p == 1 settings used before the dram cleanup, this happend to do the right thing in the form of dividing by 2. But with the new dram code div_p is 0, and then the old get_cmu_clk code fails with a divide by 0 error.
This commit fixes this, by changing the clk calculation to the correct form of:
clk = (24 * factor_n * factor_k) >> div_p;
Signed-off-by: Hans de Goede hdegoede@redhat.com --- drivers/block/sunxi_nand/nfd/nand_blk.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/block/sunxi_nand/nfd/nand_blk.c b/drivers/block/sunxi_nand/nfd/nand_blk.c index a632453..2169301 100644 --- a/drivers/block/sunxi_nand/nfd/nand_blk.c +++ b/drivers/block/sunxi_nand/nfd/nand_blk.c @@ -1095,16 +1095,15 @@ __u32 get_cmu_clk(void) { __u32 reg_val; __u32 div_p, factor_n; - __u32 factor_k, factor_m; + __u32 factor_k; __u32 clock;
reg_val = *(volatile unsigned int *)(0xf1c20000 + 0x20); div_p = (reg_val >> 16) & 0x3; factor_n = (reg_val >> 8) & 0x1f; factor_k = ((reg_val >> 4) & 0x3) + 1; - factor_m = ((reg_val >> 0) & 0x3) + 1;
- clock = 24 * factor_n * factor_k/div_p/factor_m; + clock = (24 * factor_n * factor_k) >> div_p;
return clock; }
Hi,
Ugh, this series is for the linux-sunxi 3.4 kernels and should have gone to a different list. Please ignore, I'll remove it from patchwork right away.
Regards,
Hans
On 10/15/2014 11:56 AM, Hans de Goede wrote:
Some fex files contain wrong values, causing stability issues.
Signed-off-by: Hans de Goede hdegoede@redhat.com
drivers/power/axp152.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index 77132e1..3b8e68f 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -541,15 +541,17 @@ static struct regulator_init_data regl_init_data[AXP152_REGULATOR_COUNT] = { .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, } },
- [axp152_dcdc3] = { /* Vddr, power on 1.5V, Android from fex */
- [axp152_dcdc3] = { /* Vddr, power on 1.5V, use u-boot value */ .num_consumer_supplies = 1, .consumer_supplies = &axp152_dcdc3_supply, .constraints = {
.min_uV = 1500 * 1000,.max_uV = 1500 * 1000,
.min_uV = 1000 * 1000,.max_uV = 1600 * 1000, .always_on = 1,
.apply_uV = 1,.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
/** We do not allow changing the DRAM voltage, because* of stability, so no REGULATOR_CHANGE_VOLTAGE.*/@@ -622,11 +624,11 @@ static int __init axp_board_init(void)
/* Note we ignore the dcdc2_vol key as dcdc2 is set by the dvfs code */
- ret = script_parser_fetch("target", "dcdc3_vol", &val, sizeof(int));
- if (ret == 0) {
regl_init_data[axp152_dcdc3].constraints.min_uV = val * 1000;regl_init_data[axp152_dcdc3].constraints.max_uV = val * 1000;- }
/*
* Note we ignore the dcdc3_vol key as that sometimes contains wrong* values make the dram unstable, instead we stick with the bootloader* set voltage.*/ret = script_parser_fetch("target", "dcdc4_vol", &val, sizeof(int)); if (ret == 0) {
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Hans de Goede