[U-Boot] [PATCH 1/6] tsec: Move tsec.h to include/

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Andy Fleming

31 Aug 2008 31 Aug '08

11:33 p.m.

This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming afleming@freescale.com --- drivers/net/tsec.c | 8 +------- {drivers/net => include}/tsec.h | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) rename {drivers/net => include}/tsec.h (99%)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 6e0f2c6..06558b9 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -16,8 +16,8 @@ #include <malloc.h> #include <net.h> #include <command.h> +#include <tsec.h>

-#include "tsec.h" #include "miiphy.h"

DECLARE_GLOBAL_DATA_PTR; @@ -32,12 +32,6 @@ typedef volatile struct rtxbd { rxbd8_t rxbd[PKTBUFSRX]; } RTXBD;

-struct tsec_info_struct { - unsigned int phyaddr; - u32 flags; - unsigned int phyregidx; -}; - /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet * device. The information needed is: diff --git a/drivers/net/tsec.h b/include/tsec.h similarity index 99% rename from drivers/net/tsec.h rename to include/tsec.h index 6a2338b..6d38ddb 100644 --- a/drivers/net/tsec.h +++ b/include/tsec.h @@ -576,4 +576,10 @@ struct phy_info { struct phy_cmd *shutdown; };

+struct tsec_info_struct { + unsigned int phyaddr; + u32 flags; + unsigned int phyregidx; +}; + #endif /* __TSEC_H */

-- 1.5.4.GIT

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Andy Fleming

31 Aug 31 Aug

11:33 p.m.

New subject: [U-Boot] [PATCH 2/6] Pass in tsec_info struct through tsec_initialize

From: Ben Warren biggerbadderben@gmail.com

The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter.

Signed-off-by: Andy Fleming afleming@freescale.com --- cpu/mpc83xx/cpu.c | 20 +++------ cpu/mpc85xx/cpu.c | 33 +++++----------- cpu/mpc86xx/cpu.c | 26 +++--------- drivers/net/tsec.c | 113 +++++++++++++++++++++++----------------------------- include/tsec.h | 32 +++++++++++++-- 5 files changed, 102 insertions(+), 122 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 52e4476..5862acd 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -32,6 +32,7 @@ #include <mpc83xx.h> #include <asm/processor.h> #include <libfdt.h> +#include <tsec.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -358,22 +359,15 @@ int dma_xfer(void *dest, u32 count, void *src) } #endif /*CONFIG_DDR_ECC*/

-#ifdef CONFIG_TSEC_ENET -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname); - int cpu_eth_init(bd_t *bis) { -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#if defined(CONFIG_TSEC_ENET) + tsec_standard_init(bis); #endif + return 0; } -#endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe3cea..7976cac 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -25,9 +25,11 @@ * MA 02111-1307 USA */

+#include <config.h> #include <common.h> #include <watchdog.h> #include <command.h> +#include <tsec.h> #include <asm/cache.h> #include <asm/io.h>

@@ -294,6 +296,7 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif + /* * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) * are hardcoded as "1"."size" is the number or entries, not a sizeof. @@ -360,32 +363,16 @@ void upmconfig (uint upm, uint * table, uint size) out_be32(mxmr, loopval); /* OP_NORMAL */ }

-#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC) -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname);

+/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ int cpu_eth_init(bd_t *bis) { -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif -#if defined(CONFIG_MPC85XX_FEC) - tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); -#else -#if defined(CONFIG_TSEC3) - tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); -#endif -#if defined(CONFIG_TSEC4) - tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); -#endif +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC) + tsec_standard_init(bis); #endif + return 0; } -#endif diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index ecea5b0..3a75af7 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -28,6 +28,7 @@ #include <asm/cache.h> #include <asm/mmu.h> #include <mpc86xx.h> +#include <tsec.h> #include <asm/fsl_law.h>

@@ -305,28 +306,15 @@ void mpc86xx_reginfo(void)

}

-#ifdef CONFIG_TSEC_ENET -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname); - int cpu_eth_init(bd_t *bis) { -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif -#if defined(CONFIG_TSEC3) - tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); -#endif -#if defined(CONFIG_TSEC4) - tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#if defined(CONFIG_TSEC_ENET) + tsec_standard_init(bis); #endif + return 0; } -#endif /* CONFIG_TSEC_ENET */ diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 06558b9..d723b74 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -32,63 +32,12 @@ typedef volatile struct rtxbd { rxbd8_t rxbd[PKTBUFSRX]; } RTXBD;

-/* The tsec_info structure contains 3 values which the - * driver uses to determine how to operate a given ethernet - * device. The information needed is: - * phyaddr - The address of the PHY which is attached to - * the given device. - * - * flags - This variable indicates whether the device - * supports gigabit speed ethernet, and whether it should be - * in reduced mode. - * - * phyregidx - This variable specifies which ethernet device - * controls the MII Management registers which are connected - * to the PHY. For now, only TSEC1 (index 0) has - * access to the PHYs, so all of the entries have "0". - * - * The values specified in the table are taken from the board's - * config file in include/configs/. When implementing a new - * board with ethernet capability, it is necessary to define: - * TSECn_PHY_ADDR - * TSECn_PHYIDX - * - * for n = 1,2,3, etc. And for FEC: - * FEC_PHY_ADDR - * FEC_PHYIDX - */ -static struct tsec_info_struct tsec_info[] = { -#ifdef CONFIG_TSEC1 - {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, -#else - {0, 0, 0}, -#endif -#ifdef CONFIG_TSEC2 - {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, -#else - {0, 0, 0}, -#endif -#ifdef CONFIG_MPC85XX_FEC - {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, -#else -#ifdef CONFIG_TSEC3 - {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, -#else - {0, 0, 0}, -#endif -#ifdef CONFIG_TSEC4 - {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, -#else - {0, 0, 0}, -#endif /* CONFIG_TSEC4 */ -#endif /* CONFIG_MPC85XX_FEC */ -}; - -#define MAXCONTROLLERS (4) +#define MAXCONTROLLERS (8)

static int relocated = 0;

static struct tsec_private *privlist[MAXCONTROLLERS]; +static int num_tsecs = 0;

#ifdef __GNUC__ static RTXBD rtx __attribute__ ((aligned(8))); @@ -121,10 +70,51 @@ static int tsec_miiphy_read(char *devname, unsigned char addr, static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); #endif

+/* Default initializations for TSEC controllers. */ + +static struct tsec_info_struct tsec_info[] = { +#ifdef CONFIG_TSEC1 + STD_TSEC_INFO(1), /* TSEC1 */ +#endif +#ifdef CONFIG_TSEC2 + STD_TSEC_INFO(2), /* TSEC2 */ +#endif +#ifdef CONFIG_MPC85XX_FEC + { + .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), + .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .devname = CONFIG_MPC85XX_FEC_NAME, + .phyaddr = FEC_PHY_ADDR, + .flags = FEC_FLAGS + }, /* FEC */ +#endif +#ifdef CONFIG_TSEC3 + STD_TSEC_INFO(3), /* TSEC3 */ +#endif +#ifdef CONFIG_TSEC4 + STD_TSEC_INFO(4), /* TSEC4 */ +#endif +}; + +int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) +{ + int i; + + for (i = 0; i < num; i++) + tsec_initialize(bis, &tsecs[i]); + + return 0; +} + +int tsec_standard_init(bd_t *bis) +{ + return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); +} + /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ -int tsec_initialize(bd_t * bis, int index, char *devname) +int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) { struct eth_device *dev; int i; @@ -142,16 +132,14 @@ int tsec_initialize(bd_t * bis, int index, char *devname) if (NULL == priv) return 0;

- privlist[index] = priv; - priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); - priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + - tsec_info[index].phyregidx * - TSEC_SIZE); + privlist[num_tsecs++] = priv; + priv->regs = tsec_info->regs; + priv->phyregs = tsec_info->miiregs;

- priv->phyaddr = tsec_info[index].phyaddr; - priv->flags = tsec_info[index].flags; + priv->phyaddr = tsec_info->phyaddr; + priv->flags = tsec_info->flags;

- sprintf(dev->name, devname); + sprintf(dev->name, tsec_info->devname); dev->iobase = 0; dev->priv = priv; dev->init = tsec_init; @@ -226,7 +214,6 @@ int tsec_init(struct eth_device *dev, bd_t * bd)

/* If there's no link, fail */ return (priv->link ? 0 : -1); - }

/* Write value to the device's PHY through the registers diff --git a/include/tsec.h b/include/tsec.h index 6d38ddb..fece074 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -27,12 +27,30 @@ #define TSEC_SIZE 0x01000

/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) -#elif defined(CONFIG_MPC83XX) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ + || defined(CONFIG_MPC83XX) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #endif

+#define STD_TSEC_INFO(num) \ +{ \ + .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ + .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .devname = CONFIG_TSEC##num##_NAME, \ + .phyaddr = TSEC##num##_PHY_ADDR, \ + .flags = TSEC##num##_FLAGS \ +} + +#define SET_STD_TSEC_INFO(x, num) \ +{ \ + x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ + x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.devname = CONFIG_TSEC##num##_NAME; \ + x.phyaddr = TSEC##num##_PHY_ADDR; \ + x.flags = TSEC##num##_FLAGS;\ +} + +

#define MAC_ADDR_LEN 6

@@ -577,9 +595,15 @@ struct phy_info { };

struct tsec_info_struct { + tsec_t *regs; + tsec_t *miiregs; + char *devname; unsigned int phyaddr; u32 flags; - unsigned int phyregidx; };

+int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); +int tsec_standard_init(bd_t *bis); +int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); + #endif /* __TSEC_H */

-- 1.5.4.GIT

Andy Fleming

11:33 p.m.

New subject: [U-Boot] [PATCH 3/6] Add SGMII support to the tsec

Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming afleming@freescale.com --- drivers/net/tsec.c | 74 +++++++++++++++++++++++++++++++++------------------ include/tsec.h | 25 +++++++++++++++++- 2 files changed, 72 insertions(+), 27 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d723b74..d5c1da2 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -216,61 +216,80 @@ int tsec_init(struct eth_device *dev, bd_t * bd) return (priv->link ? 0 : -1); }

-/* Write value to the device's PHY through the registers - * specified in priv, modifying the register specified in regnum. - * It will wait for the write to be done (or for a timeout to - * expire) before exiting - */ -void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) +/* Writes the given phy's reg with value, using the specified MDIO regs */ +static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, + uint reg, uint value) { - volatile tsec_t *regbase = priv->phyregs; int timeout = 1000000;

- regbase->miimadd = (phyid << 8) | regnum; - regbase->miimcon = value; + phyregs->miimadd = (addr << 8) | reg; + phyregs->miimcon = value; asm("sync");

timeout = 1000000; - while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; + while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; }

-/* #define to provide old write_phy_reg functionality without duplicating code */ -#define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) + +/* Provide the default behavior of writing the PHY of this ethernet device */ +#define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)

/* Reads register regnum on the device's PHY through the - * registers specified in priv. It lowers and raises the read + * specified registers. It lowers and raises the read * command, and waits for the data to become valid (miimind * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) { uint value; - volatile tsec_t *regbase = priv->phyregs;

/* Put the address of the phy, and the register * number into MIIMADD */ - regbase->miimadd = (phyid << 8) | regnum; + phyregs->miimadd = (phyid << 8) | regnum;

/* Clear the command register, and wait */ - regbase->miimcom = 0; + phyregs->miimcom = 0; asm("sync");

/* Initiate a read command, and wait */ - regbase->miimcom = MIIM_READ_COMMAND; + phyregs->miimcom = MIIM_READ_COMMAND; asm("sync");

/* Wait for the the indication that the read is done */ - while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; + while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;

/* Grab the value read from the PHY */ - value = regbase->miimstat; + value = phyregs->miimstat;

return value; }

/* #define to provide old read_phy_reg functionality without duplicating code */ -#define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) +#define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) + +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) +/* Configure the TBI for SGMII operation */ +static void tsec_configure_serdes(struct tsec_private *priv) +{ + tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA, + TBIANA_SETTINGS); + tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON, + TBICON_CLK_SELECT); + tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR, + TBICR_SETTINGS); +}

/* Discover which PHY is attached to the device, and configure it * properly. If the PHY is not recognized, then return 0 @@ -280,12 +299,12 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); + volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_t *regs = priv->regs;

/* Assign a Physical address to the TBI */ regs->tbipa = CFG_TBIPA_VALUE; - regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); - regs->tbipa = CFG_TBIPA_VALUE; + phyregs->tbipa = CFG_TBIPA_VALUE; asm("sync");

/* Reset MII (due to new addresses) */ @@ -309,6 +328,9 @@ static int init_phy(struct eth_device *dev) return 0; }

+ if (regs->ecntrl & ECNTRL_SGMII_MODE) + tsec_configure_serdes(priv); + priv->phyinfo = curphy;

phy_run_commands(priv, priv->phyinfo->config); @@ -1651,7 +1673,7 @@ static int tsec_miiphy_read(char *devname, unsigned char addr, return -1; }

- ret = (unsigned short)read_any_phy_reg(priv, addr, reg); + ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); *value = ret;

return 0; @@ -1673,7 +1695,7 @@ static int tsec_miiphy_write(char *devname, unsigned char addr, return -1; }

- write_any_phy_reg(priv, addr, reg, value); + tsec_local_mdio_write(priv->phyregs, addr, reg, value);

return 0; } diff --git a/include/tsec.h b/include/tsec.h index fece074..4959bdb 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -60,6 +60,27 @@

#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */

+/* TBI register addresses */ +#define TBI_CR 0x00 +#define TBI_SR 0x01 +#define TBI_ANA 0x04 +#define TBI_ANLPBPA 0x05 +#define TBI_ANEX 0x06 +#define TBI_TBICON 0x11 + +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + + /* MAC register bits */ #define MACCFG1_SOFT_RESET 0x80000000 #define MACCFG1_RESET_RX_MC 0x00080000 @@ -533,7 +554,9 @@ typedef struct tsec

/* This flag currently only has * meaning if we're using the eTSEC */ -#define TSEC_REDUCED (1 << 1) +#define TSEC_REDUCED (1 << 1) + +#define TSEC_SGMII (1 << 2)

struct tsec_private { volatile tsec_t *regs;

-- 1.5.4.GIT

Andy Fleming

11:33 p.m.

New subject: [U-Boot] [PATCH 4/6] Add support for Freescale SGMII Riser Card

The 8544DS and 8572DS systems have an optional SGMII riser card which exposes new ethernet ports which are connected to the eTSECs via an SGMII interface. The SGMII PHYs for this board are offset from the standard PHY addresses, so this code modifies the passed in tsec_info structure to use the SGMII PHYs on the card, instead.

Signed-off-by: Andy Fleming afleming@freescale.com --- board/freescale/common/Makefile | 1 + board/freescale/common/sgmii_riser.c | 26 ++++++++++++++++++++++++++ board/freescale/common/sgmii_riser.h | 15 +++++++++++++++ include/configs/MPC8544DS.h | 3 +++ 4 files changed, 45 insertions(+), 0 deletions(-) create mode 100644 board/freescale/common/sgmii_riser.c create mode 100644 board/freescale/common/sgmii_riser.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 508e3b5..8584374 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -36,6 +36,7 @@ COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o +COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o

COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c new file mode 100644 index 0000000..5ccd6bc --- /dev/null +++ b/board/freescale/common/sgmii_riser.c @@ -0,0 +1,26 @@ +/* + * Freescale SGMII Riser Card + * + * This driver supports the SGMII Riser card found on the + * "DS" style of development board from Freescale. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + */ + +#include <config.h> +#include <common.h> +#include <tsec.h> + +void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) +{ + int i; + + for (i = 0; i < num; i++) + if (tsec_info[i].flags & TSEC_SGMII) + tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; +} diff --git a/board/freescale/common/sgmii_riser.h b/board/freescale/common/sgmii_riser.h new file mode 100644 index 0000000..8d56a1f --- /dev/null +++ b/board/freescale/common/sgmii_riser.h @@ -0,0 +1,15 @@ +/* + * Freescale SGMII Riser Card + * + * This driver supports the SGMII Riser card found on the + * "DS" style of development board from Freescale. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + */ + +void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num); diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 5738192..a428e88 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -369,6 +369,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3"

+#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1c + #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1

-- 1.5.4.GIT

Andy Fleming

11:33 p.m.

New subject: [U-Boot] [PATCH 5/6] Add SGMII support for the 8544 DS

The 8544 DS has an optional SGMII Riser card, which uses different PHY addresses. Check if we are in SGMII mode, and invoke the SGMII Riser setup code if so.

Signed-off-by: Andy Fleming afleming@freescale.com --- board/freescale/mpc8544ds/mpc8544ds.c | 39 +++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4e976b7..1e29773 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -32,8 +32,10 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h>

#include "../common/pixis.h" +#include "../common/sgmii_riser.h"

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -463,6 +465,43 @@ get_board_sys_clk(ulong dummy) return val; }

+#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[2]; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + if (io_sel & 1) + fsl_sgmii_riser_init(tsec_info, num); + + + tsec_eth_init(bis, tsec_info, num); + + return 0; +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP)

void

-- 1.5.4.GIT

Andy Fleming

11:33 p.m.

New subject: [U-Boot] [PATCH 6/6] Add pixis_set_sgmii command

The 8544DS and 8572DS platforms support an optional SGMII riser card to expose ethernet over an SGMII interface. Once the card is in, it is also necessary to configure the board such that it uses the card, rather than the on-board ethernet ports. This can either be done by flipping dip switches on the motherboard, or by modifying registers in the pixis. Either way requires a reboot.

This adds a command to allow users to choose which ports are routed through the SGMII card, and which through the onboard ports. It also allows users to revert to the current switch settings.

This code does not work on the 8572, as the PIXIS is different.

Signed-off-by: Andy Fleming afleming@freescale.com --- board/freescale/common/pixis.c | 55 ++++++++++++++++++++++++++++++++++++++++ include/configs/MPC8544DS.h | 5 +++ 2 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 64e2e08..b5a0e84 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -26,6 +26,7 @@ #include <command.h> #include <watchdog.h> #include <asm/cache.h> +#include <asm/io.h>

#include "pixis.h"

@@ -282,6 +283,60 @@ U_BOOT_CMD( "diswd - Disable watchdog timer \n", NULL);

+#ifdef CONFIG_FSL_SGMII_RISER +int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int which_tsec = -1; + uchar mask; + uchar switch_mask; + + if (argc > 2) + if (strcmp(argv[1], "all") != 0) + which_tsec = simple_strtoul(argv[1], NULL, 0); + + switch (which_tsec) { + case 1: + mask = PIXIS_VSPEED2_TSEC1SER; + switch_mask = PIXIS_VCFGEN1_TSEC1SER; + break; + case 3: + mask = PIXIS_VSPEED2_TSEC3SER; + switch_mask = PIXIS_VCFGEN1_TSEC3SER; + break; + default: + mask = PIXIS_VSPEED2_TSEC1SER | PIXIS_VSPEED2_TSEC3SER; + switch_mask = PIXIS_VCFGEN1_TSEC1SER | PIXIS_VCFGEN1_TSEC3SER; + break; + } + + /* Toggle whether the switches or FPGA control the settings */ + if (!strcmp(argv[argc - 1], "switch")) + clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, + switch_mask); + else + setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, + switch_mask); + + /* If it's not the switches, enable or disable SGMII, as specified */ + if (!strcmp(argv[argc - 1], "on")) + clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + else if (!strcmp(argv[argc - 1], "off")) + setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + + return 0; +} + +U_BOOT_CMD( + pixis_set_sgmii, CFG_MAXARGS, 1, pixis_set_sgmii, + "pixis_set_sgmii" + " - Enable or disable SGMII mode for a given TSEC \n", + "\npixis_set_sgmii [TSEC num] <on|off|switch>\n" + " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n" + " on - enables SGMII\n" + " off - disables SGMII\n" + " switch - use switch settings\n"); +#endif + /* * This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a428e88..612e8f2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -196,7 +196,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ +#define PIXIS_VSPEED2_TSEC1SER 0x2 +#define PIXIS_VSPEED2_TSEC3SER 0x1 +#define PIXIS_VCFGEN1_TSEC1SER 0x20 +#define PIXIS_VCFGEN1_TSEC3SER 0x40

/* define to use L1 as initial stack */

-- 1.5.4.GIT

Ben Warren

1 Sep 1 Sep

5:51 a.m.

Andy Fleming wrote:

...

This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming afleming@freescale.com

Thanks Andy. Nice work! Patches 1-6 applied to the net tree.

regards, Ben

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