Signed-off-by: Vipin vipin.kumar@st.com --- drivers/mtd/Makefile | 1 + drivers/mtd/spr_smi.c | 548 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_smi.h | 112 +++++++ 3 files changed, 661 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/mtd/Makefile create mode 100755 drivers/mtd/spr_smi.c create mode 100755 include/asm-arm/arch-spear/spr_smi.h

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile old mode 100644 new mode 100755 index 754d648..cbf6f15 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o +COBJS-$(CONFIG_SPEARSMI) += spr_smi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c new file mode 100755 index 0000000..bc17c9d --- /dev/null +++ b/drivers/mtd/spr_smi.c @@ -0,0 +1,548 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <flash.h> +#include <linux/err.h> + +#include <asm/io.h> +#include <asm/arch/spr_smi.h> + +#if !defined(CONFIG_SYS_NO_FLASH) + +static struct smi_regs *const smicntl = + (struct smi_regs *const)CONFIG_SYS_SMI_BASE; +static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_ADDR_BASE; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +#define ST_M25Pxx_ID 0x00002020 + +/** + * smi_wait_xfer_finish - Wait until TFF is set in status register + * @timeout: timeout in milliseconds + * + * Wait until TFF is set in status register + */ +static inline void smi_wait_xfer_finish(int timeout) +{ + while (timeout--) { + if (readl(&smicntl->smi_sr) & TFF) + break; + udelay(1000); + } +} + +/** + * smi_read_id - Read flash id + * @info: flash_info structure pointer + * @banknum: bank number + * + * Read the flash id present at bank #banknum + */ +static unsigned int smi_read_id(flash_info_t *info, int banknum) +{ + unsigned int value; + + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + writel(READ_ID, &smicntl->smi_tr); + writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); + + writel(readl(&smicntl->smi_sr) & ~(TFF), &smicntl->smi_sr); + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), &smicntl->smi_cr1); + + return value; +} + +/** + * flash_get_size - Detect the SMI flash by reading the ID. + * @base: Base address of the flash area bank #banknum + * @banknum: Bank number + * + * Detect the SMI flash by reading the ID. Initializes the flash_info structure + * with size, sector count etc. + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + unsigned int value = 0; + unsigned int density = 0; + int i; + + value = smi_read_id(info, banknum); + density = (value >> 16) & 0xff; + + switch (density) { + case 0x10: + info->size = 64 * 1024; + info->sector_count = 2; + break; + case 0x11: + info->size = 128 * 1024; + info->sector_count = 4; + break; + case 0x12: + info->size = 256 * 1024; + info->sector_count = 4; + break; + case 0x13: + info->size = 512 * 1024; + info->sector_count = 8; + break; + case 0x14: + info->size = 1 * 1024 * 1024; + info->sector_count = 16; + break; + case 0x15: + info->size = 2 * 1024 * 1024; + info->sector_count = 32; + break; + case 0x16: + info->size = 4 * 1024 * 1024; + info->sector_count = 64; + break; + case 0x17: + info->size = 8 * 1024 * 1024; + info->sector_count = 128; + break; + case 0x18: + info->size = 16 * 1024 * 1024; + info->sector_count = 64; + break; + default: + return 0x0; + } + + info->flash_id = value & 0xffff; + + info->start[0] = base; + + /* Assume that all sectors are unprotected by default */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) + info->protect[i] = 0; + + return info->size; +} + +/** + * smi_read_sr - Read status register of SMI + * @bank: bank number + * + * This routine will get the status register of the flash chip present at the + * given bank + */ +static int smi_read_sr(int bank) +{ + u32 ctrlreg1; + + /* store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in HW Mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), + &smicntl->smi_cr1); + + /* Performing a RSR instruction in HW mode */ + writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + return readl(&smicntl->smi_sr); +} + +/** + * smi_wait_till_ready - Wait till last operation is over. + * @bank: bank number shifted. + * @timeout: timeout in milliseconds. + * + * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) + * The routine checks for #timeout loops, each at interval of 1 milli-second. + * If successful the routine returns 0. + */ +static int smi_wait_till_ready(int bank, int timeout) +{ + int count; + int sr; + + /* One chip guarantees max 5 msec wait here after page writes, + but potentially three seconds (!) after page erase. */ + for (count = 0; count < timeout; count++) { + sr = smi_read_sr(bank); + if (sr < 0) + break; + else if (!(sr & WIP_BIT)) + return 0; + /*Try again after 1m-sec */ + udelay(1000); + } + printf("SMI controller is still in wait, timeout=%d\n", timeout); + return -EIO; +} + +/** + * smi_write_enable - Enable the flash to do write operation + * @bank: bank number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static inline int smi_write_enable(int bank) +{ + u32 ctrlreg1; + int timeout = WMODE_TOUT; + + /* Store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in H/W Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + /* Give the Flash, Write Enable command */ + writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + while (timeout--) { + if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + break; + udelay(1000); + } + + return 0; +} + +/** + * smi_init - SMI initialization routine + * + * SMI initialization routine. Sets SMI control register1. + */ +static void smi_init(void) +{ + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +/** + * smi_sector_erase - Erase flash sector + * @info: flash_info structure pointer + * @sector: sector number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_sector_erase(flash_info_t *info, unsigned int sector) +{ + int bank; + unsigned int sect_add; + unsigned int instruction; + + switch (info->start[0]) { + case SMIBANK0_BASE: + bank = BANK0; + break; + case SMIBANK1_BASE: + bank = BANK1; + break; + case SMIBANK2_BASE: + bank = BANK2; + break; + case SMIBANK3_BASE: + bank = BANK3; + break; + default: + return -1; + } + + sect_add = sector * (info->size / info->sector_count); + instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; + + writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); + + if (info->flash_id == ST_M25Pxx_ID) { + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; + + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, + &smicntl->smi_cr1); + + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), + &smicntl->smi_cr1); + + return 0; + } else { + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), + &smicntl->smi_cr1); + return -EINVAL; + } +} + +/** + * smi_write - Write to SMI flash + * @src_addr: source buffer + * @dst_addr: destination buffer + * @length: length to write in words + * @bank: bank base address + * + * Write to SMI flash + */ +static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, + unsigned int length, ulong bank_addr) +{ + int banknum; + unsigned int WM; + + switch (bank_addr) { + case SMIBANK0_BASE: + banknum = BANK0; + WM = WM0; + break; + case SMIBANK1_BASE: + banknum = BANK1; + WM = WM1; + break; + case SMIBANK2_BASE: + banknum = BANK2; + WM = WM2; + break; + case SMIBANK3_BASE: + banknum = BANK3; + WM = WM3; + break; + default: + return -1; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + /* Set SMI in Hardware Mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), &smicntl->smi_cr1); + + if (smi_write_enable(banknum)) + return -EIO; + + /* Perform the write command */ + while (length--) { + if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { + if (smi_wait_till_ready(banknum, + CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + if (smi_write_enable(banknum)) + return -EIO; + } + + *dst_addr++ = *src_addr++; + + if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) + return -EIO; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); + + return 0; +} + +/** + * write_buff - Write to SMI flash + * @info: flash info structure + * @src: source buffer + * @dest_addr: destination buffer + * @length: length to write in words + * + * Write to SMI flash + */ +int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) +{ + smi_write((unsigned int *)src, (unsigned int *)dest_addr, + (length + 3) / 4, info->start[0]); + return 0; +} + +/** + * flash_init - SMI flash initialization + * + * SMI flash initialization + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i, j; + + smi_init(); + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(bank_base[i], i); + } + + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { + for (i = 1; i < flash_info[j].sector_count; i++) + flash_info[j].start[i] = + flash_info[j].start[i - 1] + + flash_info->size / flash_info->sector_count; + + } + + return size; +} + +/** + * flash_print_info - Print SMI flash information + * + * Print SMI flash information + */ +void flash_print_info(flash_info_t *info) +{ + int i; + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); + return; + } + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO + int size; + int erased; + u32 *flash; + + /* + * Check if whole sector is erased + */ + size = (info->size) / (info->sector_count); + flash = (u32 *) info->start[i]; + size = size / sizeof(int); + + while ((size--) && (*flash++ == ~0)) + ; + + size++; + if (size) + erased = 0; + else + erased = 1; + + if ((i % 5) == 0) + printf("\n"); + + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO) " : " "); +#endif + } + putc('\n'); + return; +} + +/** + * flash_erase - Erase SMI flash + * + * Erase SMI flash + */ +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot = 0; + flash_sect_t sect; + + if (info->flash_id == FLASH_UNKNOWN) { + puts("Can't erase unknown flash type - aborted\n"); + return 1; + } + + if ((s_first < 0) || (s_first > s_last)) { + puts("- no sectors to erase\n"); + return 1; + } + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + putc('\n'); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { + switch (info->flash_id) { + case ST_M25Pxx_ID: + if (smi_sector_erase(info, sect)) + rcode = 1; + else + putc('.'); + + break; + + default: + printf("Unkown flash vendor 0x%x\n", + (u32) info->flash_id); + break; + } + } + } + puts(" done\n"); + return rcode; +} +#endif diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h new file mode 100755 index 0000000..abc0dc2 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_smi.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef SPR_SMI_H +#define SPR_SMI_H + +/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ +/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ + +#define SMI_BASE CONFIG_SYS_SMI_BASE + +#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE +#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE + +#define SMIBANK0_BASE (FLASH_START_ADDRESS) +#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) +#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) +#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) + +#define BANK0 0 +#define BANK1 1 +#define BANK2 2 +#define BANK3 3 + +struct smi_regs { + u32 smi_cr1; + u32 smi_cr2; + u32 smi_sr; + u32 smi_tr; + u32 smi_rr; +}; + +/* CONTROL REG 1 */ +#define BANK_EN 0x0000000F /* enables all banks */ +#define DSEL_TIME 0x00000060 /* Deselect time 6+1 SMI_CK periods */ +#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ +#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ +#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ +#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ +#define SW_MODE 0x10000000 /* enables SW Mode */ +#define WB_MODE 0x20000000 /* Write Burst Mode */ +#define FAST_MODE 0x00008000 /* Fast Mode */ +#define HOLD1 0x00010000 + +/* CONTROL REG 2 */ +#define RD_STATUS_REG 0x00000400 /* reads status reg */ +#define WE 0x00000800 /* Write Enable */ +#define BANK0_SEL 0x00000000 /* Select Banck0 */ +#define BANK1_SEL 0x00001000 /* Select Banck1 */ +#define BANK2_SEL 0x00002000 /* Select Banck2 */ +#define BANK3_SEL 0x00003000 /* Select Banck3 */ +#define BANKSEL_SHIFT 12 +#define SEND 0x00000080 /* Send data */ +#define TX_LEN_1 0x00000001 /* data length = 1 byte */ +#define TX_LEN_2 0x00000002 /* data length = 2 byte */ +#define TX_LEN_3 0x00000003 /* data length = 3 byte */ +#define TX_LEN_4 0x00000004 /* data length = 4 byte */ +#define RX_LEN_1 0x00000010 /* data length = 1 byte */ +#define RX_LEN_2 0x00000020 /* data length = 2 byte */ +#define RX_LEN_3 0x00000030 /* data length = 3 byte */ +#define RX_LEN_4 0x00000040 /* data length = 4 byte */ +#define TFIE 0x00000100 /* Transmission Flag Interrupt Enable */ +#define WCIE 0x00000200 /* Write Complete Interrupt Enable */ + +/* STATUS_REG */ +#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ +#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ +#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR on SMI SR */ +#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR on SMI SR */ +#define RSR 0x00000005 /* Read Status regiser */ +#define TFF 0x00000100 /* Transfer Finished FLag */ +#define WCF 0x00000200 /* Transfer Finished FLag */ +#define ERF1 0x00000400 /* Error Flag 1 */ +#define ERF2 0x00000800 /* Error Flag 2 */ +#define WM0 0x00001000 /* WM Bank 0 */ +#define WM1 0x00002000 /* WM Bank 1 */ +#define WM2 0x00004000 /* WM Bank 2 */ +#define WM3 0x00008000 /* WM Bank 3 */ +#define WM_SHIFT 12 + +/* TR REG */ +#define READ_ID 0x0000009F /* Read Identification */ +#define BULK_ERASE 0x000000C7 /* BULK erase */ +#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ +#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ + +#define SFLASH_PAGE_SIZE 0x100 +#define XFER_FINISH_TOUT 2 +#define WMODE_TOUT 2 + +#endif +

Signed-off-by: Vipin vipin.kumar@st.com --- common/main.c | 2 + drivers/serial/usbtty.h | 2 + drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/spr_udc.c | 996 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_misc.h | 126 +++++ include/usb/spr_udc.h | 227 ++++++++ 6 files changed, 1354 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/serial/usbtty.h mode change 100644 => 100755 drivers/usb/gadget/Makefile create mode 100755 drivers/usb/gadget/spr_udc.c create mode 100644 include/asm-arm/arch-spear/spr_misc.h create mode 100755 include/usb/spr_udc.h

diff --git a/common/main.c b/common/main.c index 10d8904..79f3018 100644 --- a/common/main.c +++ b/common/main.c @@ -397,6 +397,7 @@ void main_loop (void)

debug ("### main_loop: bootcmd="%s"\n", s ? s : "<UNDEFINED>");

+#if !defined(CONFIG_SPEAR_USBTTY) if (bootdelay >= 0 && s && !abortboot (bootdelay)) { # ifdef CONFIG_AUTOBOOT_KEYED int prev = disable_ctrlc(1); /* disable Control C checking */ @@ -413,6 +414,7 @@ void main_loop (void) disable_ctrlc(prev); /* restore Control C checking */ # endif } +# endif

# ifdef CONFIG_MENUKEY if (menukey == CONFIG_MENUKEY) { diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h old mode 100644 new mode 100755 index f746d63..c96b93e --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -31,6 +31,8 @@ #include <usb/omap1510_udc.h> #elif defined(CONFIG_PXA27X) #include <usb/pxa27x_udc.h> +#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) +#include <usb/spr_udc.h> #endif

#include <version_autogenerated.h> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile old mode 100644 new mode 100755 index 2a19b1e..1d7362d --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o +COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif

COBJS := $(COBJS-y) diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/spr_udc.c new file mode 100755 index 0000000..5b135c7 --- /dev/null +++ b/drivers/usb/gadget/spr_udc.c @@ -0,0 +1,996 @@ +/* + * Based on drivers/usb/gadget/omap1510_udc.c + * TI OMAP1510 USB bus interface driver + * + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +#include <usbdevice.h> +#include "ep0.h" +#include <usb/spr_udc.h> +#include <asm/arch/spr_misc.h> + +#define UDC_INIT_MDELAY 80 /* Device settle delay */ + +/* Some kind of debugging output... */ +#if 1 +#define UDCDBG(str) +#define UDCDBGA(fmt, args...) +#else +#define UDCDBG(str) serial_printf(str "\n") +#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) +#endif + +static struct urb *ep0_urb; +static struct usb_device_instance *udc_device; + +static struct plug_regs *const plug_regs_p = + (struct plug_regs *const)CONFIG_SYS_PLUG_BASE; +static struct udc_regs *const udc_regs_p = + (struct udc_regs *const)CONFIG_SYS_USBD_BASE; +static struct udc_endp_regs *const outep_regs_p = + &((struct udc_regs *const)CONFIG_SYS_USBD_BASE)->out_regs[0]; +static struct udc_endp_regs *const inep_regs_p = + &((struct udc_regs *const)CONFIG_SYS_USBD_BASE)->in_regs[0]; + +/* + * udc_state_transition - Write the next packet to TxFIFO. + * @initial: Initial state. + * @final: Final state. + * + * Helper function to implement device state changes. The device states and + * the events that transition between them are: + * + * STATE_ATTACHED + * || /\ + * / || + * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET + * || /\ + * / || + * STATE_POWERED + * || /\ + * / || + * DEVICE_RESET DEVICE_POWER_INTERRUPTION + * || /\ + * / || + * STATE_DEFAULT + * || /\ + * / || + * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET + * || /\ + * / || + * STATE_ADDRESSED + * || /\ + * / || + * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED + * || /\ + * / || + * STATE_CONFIGURED + * + * udc_state_transition transitions up (in the direction from STATE_ATTACHED + * to STATE_CONFIGURED) from the specified initial state to the specified final + * state, passing through each intermediate state on the way. If the initial + * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then + * no state transitions will take place. + * + * udc_state_transition also transitions down (in the direction from + * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the + * specified final state, passing through each intermediate state on the way. + * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final + * state, then no state transitions will take place. + * + * This function must only be called with interrupts disabled. + */ +static void udc_state_transition(usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial < final) { + switch (initial) { + case STATE_ATTACHED: + usbd_device_event_irq(udc_device, + DEVICE_HUB_CONFIGURED, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_ADDRESS_ASSIGNED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + case STATE_CONFIGURED: + break; + default: + break; + } + } else if (initial > final) { + switch (initial) { + case STATE_CONFIGURED: + usbd_device_event_irq(udc_device, + DEVICE_DE_CONFIGURED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq(udc_device, + DEVICE_POWER_INTERRUPTION, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + case STATE_ATTACHED: + break; + default: + break; + } + } +} + +/* Stall endpoint */ +static void udc_stall_ep(u32 ep_num) +{ + writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &inep_regs_p[ep_num].endp_cntl); + + writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, + &outep_regs_p[ep_num].endp_cntl); +} + +static void *get_fifo(int ep_num, int in) +{ + u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE; + + switch (ep_num) { + case 3: + fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); + /* break intentionally left out */ + + case 1: + fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); + /* break intentionally left out */ + + case 0: + default: + if (in) { + fifo_ptr += + readl(&outep_regs_p[2].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } else { + break; + } + + case 2: + fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; + /* break intentionally left out */ + } + + return (void *)fifo_ptr; +} + +static short usbgetpckfromfifo(int epNum, u8 *bufp, u32 len) +{ + u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0); + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + + if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) + return -1; + + nw = len / sizeof(u32); + nb = len % sizeof(u32); + + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(readl(fifo_ptr), wrdp); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(readb(fifo_ptr), bytp); + fifo_ptr++; + bytp++; + } + readl(&outep_regs_p[epNum].write_done); + + return 0; +} + +static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) +{ + u32 i, nw, nb; + u32 *wrdp; + u8 *bytp; + u8 *fifo_ptr = get_fifo(epNum, 1); + + nw = len / sizeof(int); + nb = len % sizeof(int); + wrdp = (u32 *)bufp; + for (i = 0; i < nw; i++) { + writel(*wrdp, fifo_ptr); + wrdp++; + } + + bytp = (u8 *)wrdp; + for (i = 0; i < nb; i++) { + writeb(*bytp, fifo_ptr); + fifo_ptr++; + bytp++; + } +} + +/* + * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO. + * @endpoint: Endpoint pointer. + * + * If the endpoint has an active tx_urb, then the next packet of data from the + * URB is written to the tx FIFO. The total amount of data in the urb is given + * by urb->actual_length. The maximum amount of data that can be sent in any + * one packet is given by endpoint->tx_packetSize. The number of data bytes + * from this URB that have already been transmitted is given by endpoint->sent. + * endpoint->last is updated by this routine with the number of data bytes + * transmitted in this packet. + * + */ +static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->tx_urb; + int align; + + if (urb) { + u32 last; + + UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d", + urb->buffer, urb->buffer_length, urb->actual_length); + + last = MIN(urb->actual_length - endpoint->sent, + endpoint->tx_packetSize); + + if (last) { + u8 *cp = urb->buffer + endpoint->sent; + + /* This ensures that USBD packet fifo is accessed + :- through word aligned pointer or + :- through non word aligned pointer but only with a + max length to make the next packet word aligned */ + + align = ((ulong)cp % sizeof(int)); + if (align) + last = MIN(last, sizeof(int) - align); + + UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d", + endpoint->sent, endpoint->tx_packetSize, last); + + usbputpcktofifo(endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK, cp, last); + } + endpoint->last = last; + } +} + +/* Handle SETUP USB interrupt. + * This function implements TRM Figure 14-14. + */ +static void spear_udc_setup(struct usb_endpoint_instance *endpoint) +{ + u8 *datap = (u8 *)&ep0_urb->device_request; + int ep_addr = endpoint->endpoint_address; + + UDCDBG("-> Entering device setup"); + usbgetpckfromfifo(ep_addr, datap, 8); + + /* Try to process setup packet */ + if (ep0_recv_setup(ep0_urb)) { + /* Not a setup packet, stall next EP0 transaction */ + udc_stall_ep(0); + UDCDBG("can't parse setup packet, still waiting for setup"); + return; + } + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) + == USB_REQ_HOST2DEVICE) { + UDCDBG("control write on EP0"); + if (le16_to_cpu(ep0_urb->device_request.wLength)) { + /* Stall this request */ + UDCDBG("Stalling unsupported EP0 control write data " + "stage."); + udc_stall_ep(0); + } + } else { + + UDCDBG("control read on EP0"); + /* The ep0_recv_setup function has already placed our response + * packet data in ep0_urb->buffer and the packet length in + * ep0_urb->actual_length. + */ + endpoint->tx_urb = ep0_urb; + endpoint->sent = 0; + /* Write packet data to the FIFO. spear_write_noniso_tx_fifo + * will update endpoint->last with the number of bytes written + * to the FIFO. + */ + spear_write_noniso_tx_fifo(endpoint); + + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + + udc_unset_nak(endpoint->endpoint_address); + + UDCDBG("<- Leaving device setup"); +} + +/* + * Handle endpoint 0 RX interrupt + */ +static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint) +{ + u8 dummy[64]; + + UDCDBG("RX on EP0"); + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType + & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { + /* This rx interrupt must be for a control write data + * stage packet. + * + * We don't support control write data stages. + * We should never end up here. + */ + + UDCDBG("Stalling unexpected EP0 control write " + "data stage packet"); + udc_stall_ep(0); + } else { + /* This rx interrupt must be for a control read status + * stage packet. + */ + UDCDBG("ACK on EP0 control read status stage packet"); + u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; + usbgetpckfromfifo(0, dummy, len); + } +} + +/* + * Handle endpoint 0 TX interrupt + */ +static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) +{ + struct usb_device_request *request = &ep0_urb->device_request; + int ep_addr; + + UDCDBG("TX on EP0"); + + /* Check direction */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == + USB_REQ_HOST2DEVICE) { + /* This tx interrupt must be for a control write status + * stage packet. + */ + UDCDBG("ACK on EP0 control write status stage packet"); + } else { + /* This tx interrupt must be for a control read data + * stage packet. + */ + int wLength = le16_to_cpu(request->wLength); + + /* Update our count of bytes sent so far in this + * transfer. + */ + endpoint->sent += endpoint->last; + + /* We are finished with this transfer if we have sent + * all of the bytes in our tx urb (urb->actual_length) + * unless we need a zero-length terminating packet. We + * need a zero-length terminating packet if we returned + * fewer bytes than were requested (wLength) by the host, + * and the number of bytes we returned is an exact + * multiple of the packet size endpoint->tx_packetSize. + */ + if ((endpoint->sent == ep0_urb->actual_length) && + ((ep0_urb->actual_length == wLength) || + (endpoint->last != endpoint->tx_packetSize))) { + /* Done with control read data stage. */ + UDCDBG("control read data stage complete"); + } else { + /* We still have another packet of data to send + * in this control read data stage or else we + * need a zero-length terminating packet. + */ + UDCDBG("ACK control read data stage packet"); + spear_write_noniso_tx_fifo(endpoint); + + ep_addr = endpoint->endpoint_address; + writel(0x0, &inep_regs_p[ep_addr].write_done); + } + } +} + +static struct usb_endpoint_instance *spear_find_ep(int ep) +{ + int i; + + for (i = 0; i < udc_device->bus->max_endpoints; i++) { + if ((udc_device->bus->endpoint_array[i].endpoint_address & + USB_ENDPOINT_NUMBER_MASK) == ep) + return &udc_device->bus->endpoint_array[i]; + } + return NULL; +} + +/* + * Handle RX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 1 to 15. + */ +static void spear_udc_epn_rx(int ep) +{ + int nbytes = 0; + struct urb *urb; + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + if (endpoint) { + urb = endpoint->rcv_urb; + + if (urb) { + u8 *cp = urb->buffer + urb->actual_length; + + nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) & + 0xfff; + usbgetpckfromfifo(ep, cp, nbytes); + usbd_rcv_complete(endpoint, nbytes, 0); + } + } +} + +/* + * Handle TX transaction on non-ISO endpoint. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 16 to 30. + */ +static void spear_udc_epn_tx(int ep) +{ + struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + + /* We need to transmit a terminating zero-length packet now if + * we have sent all of the data in this URB and the transfer + * size was an exact multiple of the packet size. + */ + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { + if (endpoint->last == endpoint->tx_packetSize) { + /* handle zero length packet here */ + writel(0x0, &inep_regs_p[ep].write_done); + } + /* retire the data that was just sent */ + usbd_tx_complete(endpoint); + /* Check to see if we have more data ready to transmit + * now. + */ + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { + /* write data to FIFO */ + spear_write_noniso_tx_fifo(endpoint); + writel(0x0, &inep_regs_p[ep].write_done); + + } else if (endpoint->tx_urb + && (endpoint->tx_urb->actual_length == 0)) { + /* udc_set_nak(ep); */ + } + } +} + +/* + * Start of public functions. + */ + +/* Called to start packet transmission. */ +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + /* + spear_write_noniso_tx_fifo (endpoint); + spear_udc_epn_tx (endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK); + */ + udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK); + return 0; +} + +/* Start to initialize h/w stuff */ +int udc_init(void) +{ + int i; + u32 plug_st; + + udc_device = NULL; + + UDCDBG("starting"); + + readl(&plug_regs_p->plug_pending); + + udc_disconnect(); + + for (i = 0; i < UDC_INIT_MDELAY; i++) + udelay(1000); + + plug_st = readl(&plug_regs_p->plug_state); + writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state); + + writel(~0x0, &udc_regs_p->endp_int); + writel(~0x0, &udc_regs_p->dev_int_mask); + writel(~0x0, &udc_regs_p->endp_int_mask); + + writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | + DEV_CONF_SELFPOW | /* Dev_Conf_SYNCFRAME | */ + DEV_CONF_PHYINT_16, + &udc_regs_p->dev_conf); + + writel(0x0, &udc_regs_p->dev_cntl); + + /* Clear all interrupts pending */ + writel(DEV_INT_MSK, &udc_regs_p->dev_int); + + return 0; +} + +/* + * udc_setup_ep - setup endpoint + * Associate a physical endpoint with endpoint_instance + */ +void udc_setup_ep(struct usb_device_instance *device, + u32 ep, struct usb_endpoint_instance *endpoint) +{ + UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address); + int ep_addr; + int ep_num, ep_type; + int packet_size; + int buffer_size; + int attributes; + char *tt; + u32 endp_intmask; + + tt = getenv("usbtty"); + if (!tt) + tt = "generic"; + + ep_addr = endpoint->endpoint_address; + ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + packet_size = endpoint->tx_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->tx_attributes; + } else { + /* OUT endpoint */ + packet_size = endpoint->rcv_packetSize; + buffer_size = packet_size * 2; + attributes = endpoint->rcv_attributes; + } + + switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { + case USB_ENDPOINT_XFER_CONTROL: + ep_type = ENDP_EPTYPE_CNTL; + break; + case USB_ENDPOINT_XFER_BULK: + default: + ep_type = ENDP_EPTYPE_BULK; + break; + case USB_ENDPOINT_XFER_INT: + ep_type = ENDP_EPTYPE_INT; + break; + case USB_ENDPOINT_XFER_ISOC: + ep_type = ENDP_EPTYPE_ISO; + break; + } + + struct udc_endp_regs *out_p = &outep_regs_p[ep_num]; + struct udc_endp_regs *in_p = &inep_regs_p[ep_num]; + + if (!ep_addr) { + /* Setup endpoint 0 */ + buffer_size = packet_size; + + writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK, + &in_p->endp_cntl); + + writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK, + &out_p->endp_cntl); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl); + + writel(buffer_size/sizeof(int), &in_p->endp_bsorfn); + + writel(packet_size, &in_p->endp_maxpacksize); + + writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl); + + writel(packet_size | ((buffer_size/sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + writel((packet_size << 19) | ENDP_EPTYPE_CNTL, + &udc_regs_p->udc_endp_reg[ep_num]); + + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* Setup the IN endpoint */ + writel(0x0, &in_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl); + writel(buffer_size/sizeof(int), &in_p->endp_bsorfn); + writel(packet_size, &in_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + if (ep_type == ENDP_EPTYPE_INT) { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + /* Conf no. 1 Interface no. 1 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + } else { + /* Conf no. 1 Interface no. 0 */ + writel((packet_size << 19) | + ENDP_EPDIR_IN | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } else { + /* Setup the OUT endpoint */ + writel(0x0, &out_p->endp_status); + writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl); + writel(packet_size | ((buffer_size/sizeof(int)) << 16), + &out_p->endp_maxpacksize); + + if (!strcmp(tt, "cdc_acm")) { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (1 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } else { + writel((packet_size << 19) | + ENDP_EPDIR_OUT | (1 << 7) | + (0 << 11) | (ep_type << 5) | ep_num, + &udc_regs_p->udc_endp_reg[ep_num]); + } + + } + + endp_intmask = readl(&udc_regs_p->endp_int_mask); + endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num); + writel(endp_intmask, &udc_regs_p->endp_int_mask); +} + +/* Turn on the USB connection by enabling the pullup resistor */ +void udc_connect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Turn off the USB connection by disabling the pullup resistor */ +void udc_disconnect(void) +{ + u32 plug_st; + + plug_st = readl(&plug_regs_p->plug_state); + plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); + writel(plug_st, &plug_regs_p->plug_state); +} + +/* Switch on the UDC */ +void udc_enable(struct usb_device_instance *device) +{ + UDCDBGA("enable device %p, status %d", device, device->status); + + /* Save the device structure pointer */ + udc_device = device; + + /* Setup ep0 urb */ + if (!ep0_urb) { + ep0_urb = + usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array); + } else { + serial_printf("udc_enable: ep0_urb already allocated %p\n", + ep0_urb); + } + + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); +} + +/** + * udc_startup - allow udc code to do any additional startup + */ +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* Some USB controller driver implementations signal + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. + * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, + * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. + * The SPEAr USB client controller has the capability to detect when the + * USB cable is connected to a powered USB bus, so we will defer the + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. + */ + + udc_enable(device); +} + +/* + * Plug detection interrupt handling + */ +void spear_udc_plug_irq(void) +{ + if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { + /* USB cable attached + * Turn off PHY reset bit (PLUG detect). + * Switch PHY opmode to normal operation (PLUG detect). + */ + udc_connect(); + writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask); + + UDCDBG("device attached and powered"); + udc_state_transition(udc_device->device_state, STATE_POWERED); + } else { + /* USB cable detached + * Reset the PHY and switch the mode. + */ + udc_disconnect(); + writel(~0x0, &udc_regs_p->dev_int_mask); + + UDCDBG("device detached or unpowered"); + udc_state_transition(udc_device->device_state, STATE_ATTACHED); + } +} + +/* + * Device interrupt handling + */ +void spear_udc_dev_irq(void) +{ + u32 plug_st; + + if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { + writel(~0x0, &udc_regs_p->endp_int_mask); + + udc_connect(); + + writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, + &inep_regs_p[0].endp_cntl); + + writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); + + UDCDBG("device reset in progess"); + udc_state_transition(udc_device->device_state, STATE_DEFAULT); + } + + /* Device Enumeration completed */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) { + writel(DEV_INT_ENUM, &udc_regs_p->dev_int); + + /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */ + writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001, + &udc_regs_p->endp_int_mask); + + UDCDBG("default -> addressed"); + udc_state_transition(udc_device->device_state, STATE_ADDRESSED); + } + + /* The USB will be in SUSPEND in 3 ms */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) { + writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int); + + UDCDBG("entering inactive state"); + /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */ + } + + /* SetConfiguration command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) { + writel(DEV_INT_SETCFG, &udc_regs_p->dev_int); + + UDCDBG("entering configured state"); + udc_state_transition(udc_device->device_state, + STATE_CONFIGURED); + } + + /* SetInterface command received */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) { + writel(DEV_INT_SETINTF, &udc_regs_p->dev_int); + } + + /* USB Suspend detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) { + writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int); + + UDCDBG("entering suspended state"); + usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); + } + + /* USB Start-Of-Frame detected on cable */ + if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) { + writel(DEV_INT_SOF, &udc_regs_p->dev_int); + } +} + +/* + * Endpoint interrupt handling + */ +void spear_udc_endpoint_irq(void) +{ + while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { + + writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) + == ENDP_STATUS_OUT_SETUP) { + spear_udc_setup(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_SETUP, + &outep_regs_p[0].endp_status); + + } else + if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) + == ENDP_STATUS_OUT_DATA) { + spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[0].endp_status); + + } else + if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) + == ENDP_STATUS_OUT_NONE) { + /* NONE received */ + } + + writel(0x0, &outep_regs_p[0].endp_status); + } + + if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { + spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0); + + writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); + writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); + } + + while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOOUT_MSK; + + ep_int >>= 16; + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + writel((1 << 16) << epnum, &udc_regs_p->endp_int); + + if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { + + spear_udc_epn_rx(epnum); + writel(ENDP_STATUS_OUT_DATA, + &outep_regs_p[epnum].endp_status); + } else + if ((readl(&outep_regs_p[epnum].endp_status) & + ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) { + writel(0x0, &outep_regs_p[epnum].endp_status); + } + } + + if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) { + u32 epnum = 0; + u32 ep_int = readl(&udc_regs_p->endp_int) & + ENDP_INT_NONISOIN_MSK; + + while (0x0 == (ep_int & 0x1)) { + ep_int >>= 1; + epnum++; + } + + if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + spear_udc_epn_tx(epnum); + + writel(ENDP_STATUS_IN, + &outep_regs_p[epnum].endp_status); + } + + writel((1 << epnum), &udc_regs_p->endp_int); + } +} + +/* + * UDC interrupts + */ +void udc_irq(void) +{ + /* Loop while we have interrupts. + * If we don't do this, the input chain + * polling delay is likely to miss + * host requests. + */ + while (readl(&plug_regs_p->plug_pending)) + spear_udc_plug_irq(); + + while (readl(&udc_regs_p->dev_int)) + spear_udc_dev_irq(); + + if (readl(&udc_regs_p->endp_int)) + spear_udc_endpoint_irq(); +} + +/* Flow control */ +void udc_set_nak(int epid) +{ + writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &inep_regs_p[epid].endp_cntl); + + writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK, + &outep_regs_p[epid].endp_cntl); +} + +void udc_unset_nak(int epid) +{ + u32 val; + + val = readl(&inep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &inep_regs_p[epid].endp_cntl); + + val = readl(&outep_regs_p[epid].endp_cntl); + val &= ~ENDP_CNTL_SNAK; + val |= ENDP_CNTL_CNAK; + writel(val, &outep_regs_p[epid].endp_cntl); +} + +/******************************************************************* + * SLAVE MODE :: + * Routines to acces RX/TX FIFOs directly. + *******************************************************************/ + diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h new file mode 100644 index 0000000..15cb712 --- /dev/null +++ b/include/asm-arm/arch-spear/spr_misc.h @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_MISC_H +#define _SPR_MISC_H + +struct misc_regs { + u32 auto_cfg_reg; /* 0x0 */ + u32 armdbg_ctr_reg; /* 0x4 */ + u32 pll1_cntl; /* 0x8 */ + u32 pll1_frq; /* 0xc */ + u32 pll1_mod; /* 0x10 */ + u32 pll2_cntl; /* 0x14 */ + u32 pll2_frq; /* 0x18 */ + u32 pll2_mod; /* 0x1C */ + u32 pll_ctr_reg; /* 0x20 */ + u32 amba_clk_cfg; /* 0x24 */ + u32 periph_clk_cfg; /* 0x28 */ + u32 periph1_clken; /* 0x2C */ + u32 periph2_clken; /* 0x30 */ + u32 ras_clken; /* 0x34 */ + u32 periph1_rst; /* 0x38 */ + u32 periph2_rst; /* 0x3C */ + u32 ras_rst; /* 0x40 */ + u32 prsc1_clk_cfg; /* 0x44 */ + u32 prsc2_clk_cfg; /* 0x48 */ + u32 prsc3_clk_cfg; /* 0x4C */ + u32 amem_cfg_ctrl; /* 0x50 */ + u32 port_cfg_ctrl; /* 0x54 */ + u32 reserved_1; /* 0x58 */ + u32 clcd_synth_clk; /* 0x5C */ + u32 irda_synth_clk; /* 0x60 */ + u32 uart_synth_clk; /* 0x64 */ + u32 gmac_synth_clk; /* 0x68 */ + u32 ras_synth1_clk; /* 0x6C */ + u32 ras_synth2_clk; /* 0x70 */ + u32 ras_synth3_clk; /* 0x74 */ + u32 ras_synth4_clk; /* 0x78 */ + u32 arb_icm_ml1; /* 0x7C */ + u32 arb_icm_ml2; /* 0x80 */ + u32 arb_icm_ml3; /* 0x84 */ + u32 arb_icm_ml4; /* 0x88 */ + u32 arb_icm_ml5; /* 0x8C */ + u32 arb_icm_ml6; /* 0x90 */ + u32 arb_icm_ml7; /* 0x94 */ + u32 arb_icm_ml8; /* 0x98 */ + u32 arb_icm_ml9; /* 0x9C */ + u32 dma_src_sel; /* 0xA0 */ + u32 uphy_ctr_reg; /* 0xA4 */ + u32 gmac_ctr_reg; /* 0xA8 */ + u32 port_bridge_ctrl; /* 0xAC */ + u32 reserved_2[4]; /* 0xB0--0xBC */ + u32 prc1_ilck_ctrl_reg; /* 0xC0 */ + u32 prc2_ilck_ctrl_reg; /* 0xC4 */ + u32 prc3_ilck_ctrl_reg; /* 0xC8 */ + u32 prc4_ilck_ctrl_reg; /* 0xCC */ + u32 prc1_intr_ctrl_reg; /* 0xD0 */ + u32 prc2_intr_ctrl_reg; /* 0xD4 */ + u32 prc3_intr_ctrl_reg; /* 0xD8 */ + u32 prc4_intr_ctrl_reg; /* 0xDC */ + u32 powerdown_cfg_reg; /* 0xE0 */ + u32 ddr_1v8_compensation; /* 0xE4 */ + u32 ddr_2v5_compensation; /* 0xE8 */ + u32 core_3v3_compensation; /* 0xEC */ + u32 ddr_pad; /* 0xF0 */ + u32 bist1_ctr_reg; /* 0xF4 */ + u32 bist2_ctr_reg; /* 0xF8 */ + u32 bist3_ctr_reg; /* 0xFC */ + u32 bist4_ctr_reg; /* 0x100 */ + u32 bist5_ctr_reg; /* 0x104 */ + u32 bist1_rslt_reg; /* 0x108 */ + u32 bist2_rslt_reg; /* 0x10C */ + u32 bist3_rslt_reg; /* 0x110 */ + u32 bist4_rslt_reg; /* 0x114 */ + u32 BIST5_RSLT_REG; /* 0x118 */ + u32 SYST_ERROR_REG; /* 0x11C */ + u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ + u32 RAS_GPP1_IN; /* 0x8000 */ + u32 ras_gpp2_in; /* 0x8004 */ + u32 ras_gpp1_out; /* 0x8008 */ + u32 ras_gpp2_out; /* 0x800C */ +}; + +/* AUTO_CFG_REG value */ +#define MISC_SOCCFGMSK 0x0000003F +#define MISC_SOCCFG30 0x0000000C +#define MISC_SOCCFG31 0x0000000D +#define MISC_NANDDIS 0x00020000 + +/* PERIPH_CLK_CFG value */ +#define MISC_GPT3SYNTH 0x00000400 +#define MISC_GPT4SYNTH 0x00000800 + +/* PRSC_CLK_CFG value */ +/* + * Fout = Fin / (2^(N+1) * (M + 1)) + */ +#define MISC_PRSC_N_4 0x00004000 +#define MISC_PRSC_M_399 0x0000018F +#define MISC_PRSC_CFG (MISC_PRSC_N_4 | MISC_PRSC_M_399) + +/* PERIPH1_CLKEN, PERIPH1_RST value */ +#define MISC_USBDENB 0x01000000 + +#endif + diff --git a/include/usb/spr_udc.h b/include/usb/spr_udc.h new file mode 100755 index 0000000..9779b33 --- /dev/null +++ b/include/usb/spr_udc.h @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR_UDC_H +#define __SPR_UDC_H + +/***************************************************************************** + * Defines for USBD + * + * The udc_ahb controller has three AHB slaves: + * + * 1. THe UDC registers + * 2. The plug detect + * 3. The RX/TX FIFO + *****************************************************************************/ + +#define MAX_ENDPOINTS 16 + +struct udc_endp_regs { + u32 endp_cntl; + u32 endp_status; + u32 endp_bsorfn; + u32 endp_maxpacksize; + u32 reserved_1; + u32 endp_desc_point; + u32 reserved_2; + u32 write_done; +}; + +/* Endpoint Control Register definitions */ + +#define ENDP_CNTL_STALL 0x00000001 +#define ENDP_CNTL_FLUSH 0x00000002 +#define ENDP_CNTL_SNOOP 0x00000004 +#define ENDP_CNTL_POLL 0x00000008 +#define ENDP_CNTL_CONTROL 0x00000000 +#define ENDP_CNTL_ISO 0x00000010 +#define ENDP_CNTL_BULK 0x00000020 +#define ENDP_CNTL_INT 0x00000030 +#define ENDP_CNTL_NAK 0x00000040 +#define ENDP_CNTL_SNAK 0x00000080 +#define ENDP_CNTL_CNAK 0x00000100 +#define ENDP_CNTL_RRDY 0x00000200 + +/* Endpoint Satus Register definitions */ + +#define ENDP_STATUS_PIDMSK 0x0000000f +#define ENDP_STATUS_OUTMSK 0x00000030 +#define ENDP_STATUS_OUT_NONE 0x00000000 +#define ENDP_STATUS_OUT_DATA 0x00000010 +#define ENDP_STATUS_OUT_SETUP 0x00000020 +#define ENDP_STATUS_IN 0x00000040 +#define ENDP_STATUS_BUFFNAV 0x00000080 +#define ENDP_STATUS_FATERR 0x00000100 +#define ENDP_STATUS_HOSTBUSERR 0x00000200 +#define ENDP_STATUS_TDC 0x00000400 +#define ENDP_STATUS_RXPKTMSK 0x003ff800 + +struct udc_regs { + struct udc_endp_regs in_regs[MAX_ENDPOINTS]; + struct udc_endp_regs out_regs[MAX_ENDPOINTS]; + u32 dev_conf; + u32 dev_cntl; + u32 dev_stat; + u32 dev_int; + u32 dev_int_mask; + u32 endp_int; + u32 endp_int_mask; + u32 reserved_3[0x39]; + u32 reserved_4; /* offset 0x500 */ + u32 udc_endp_reg[MAX_ENDPOINTS]; +}; + +/* Device Configuration Register definitions */ + +#define DEV_CONF_HS_SPEED 0x00000000 +#define DEV_CONF_LS_SPEED 0x00000002 +#define DEV_CONF_FS_SPEED 0x00000003 +#define DEV_CONF_REMWAKEUP 0x00000004 +#define DEV_CONF_SELFPOW 0x00000008 +#define DEV_CONF_SYNCFRAME 0x00000010 +#define DEV_CONF_PHYINT_8 0x00000020 +#define DEV_CONF_PHYINT_16 0x00000000 +#define DEV_CONF_UTMI_BIDIR 0x00000040 +#define DEV_CONF_STATUS_STALL 0x00000080 + +/* Device Control Register definitions */ + +#define DEV_CNTL_RESUME 0x00000001 +#define DEV_CNTL_TFFLUSH 0x00000002 +#define DEV_CNTL_RXDMAEN 0x00000004 +#define DEV_CNTL_TXDMAEN 0x00000008 +#define DEV_CNTL_DESCRUPD 0x00000010 +#define DEV_CNTL_BIGEND 0x00000020 +#define DEV_CNTL_BUFFILL 0x00000040 +#define DEV_CNTL_TSHLDEN 0x00000080 +#define DEV_CNTL_BURSTEN 0x00000100 +#define DEV_CNTL_DMAMODE 0x00000200 +#define DEV_CNTL_SOFTDISCONNECT 0x00000400 +#define DEV_CNTL_SCALEDOWN 0x00000800 +#define DEV_CNTL_BURSTLENU 0x00010000 +#define DEV_CNTL_BURSTLENMSK 0x00ff0000 +#define DEV_CNTL_TSHLDLENU 0x01000000 +#define DEV_CNTL_TSHLDLENMSK 0xff000000 + +/* Device Status Register definitions */ + +#define DEV_STAT_CFG 0x0000000f +#define DEV_STAT_INTF 0x000000f0 +#define DEV_STAT_ALT 0x00000f00 +#define DEV_STAT_SUSP 0x00001000 +#define DEV_STAT_ENUM 0x00006000 +#define DEV_STAT_ENUM_SPEED_HS 0x00000000 +#define DEV_STAT_ENUM_SPEED_FS 0x00002000 +#define DEV_STAT_ENUM_SPEED_LS 0x00004000 +#define DEV_STAT_RXFIFO_EMPTY 0x00008000 +#define DEV_STAT_PHY_ERR 0x00010000 +#define DEV_STAT_TS 0xf0000000 + +/* Device Interrupt Register definitions */ + +#define DEV_INT_MSK 0x0000007f +#define DEV_INT_SETCFG 0x00000001 +#define DEV_INT_SETINTF 0x00000002 +#define DEV_INT_INACTIVE 0x00000004 +#define DEV_INT_USBRESET 0x00000008 +#define DEV_INT_SUSPUSB 0x00000010 +#define DEV_INT_SOF 0x00000020 +#define DEV_INT_ENUM 0x00000040 + +/* Endpoint Interrupt Register definitions */ + +#define ENDP0_INT_CTRLIN 0x00000001 +#define ENDP1_INT_BULKIN 0x00000002 +#define ENDP_INT_NONISOIN_MSK 0x0000AAAA +#define ENDP2_INT_BULKIN 0x00000004 +#define ENDP0_INT_CTRLOUT 0x00010000 +#define ENDP1_INT_BULKOUT 0x00020000 +#define ENDP2_INT_BULKOUT 0x00040000 +#define ENDP_INT_NONISOOUT_MSK 0x55540000 + +/* Endpoint Register definitions */ +#define ENDP_EPDIR_OUT 0x00000000 +#define ENDP_EPDIR_IN 0x00000010 +#define ENDP_EPTYPE_CNTL 0x0 +#define ENDP_EPTYPE_ISO 0x1 +#define ENDP_EPTYPE_BULK 0x2 +#define ENDP_EPTYPE_INT 0x3 + +/* + * Defines for Plug Detect + */ + +struct plug_regs { + u32 plug_state; + u32 plug_pending; +}; + +/* Plug State Register definitions */ +#define PLUG_STATUS_EN 0x1 +#define PLUG_STATUS_ATTACHED 0x2 +#define PLUG_STATUS_PHY_RESET 0x4 +#define PLUG_STATUS_PHY_MODE 0x8 + +/* + * Defines for UDC FIFO (Slave Mode) + */ +struct udcfifo_regs { + u32 *fifo_p; +}; + +/* + * USBTTY definitions + */ +#define EP0_MAX_PACKET_SIZE 64 +#define UDC_INT_ENDPOINT 1 +#define UDC_INT_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_BULK_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 3 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_PACKET_SIZE 64 + +/* + * Function declarations + */ + +void udc_irq(void); + +void udc_set_nak(int epid); +void udc_unset_nak(int epid); + +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); + +int udc_init(void); + +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); + +void udc_connect(void); +void udc_disconnect(void); + +void udc_startup_events(struct usb_device_instance *device); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, + struct usb_endpoint_instance *endpoint); + +#endif /* __SPR_UDC_H */

Signed-off-by: Vipin vipin.kumar@st.com --- MAKEALL | 1 + Makefile | 3 + board/spear/spear300/Makefile | 52 +++++++ board/spear/spear300/config.mk | 39 +++++ board/spear/spear300/spr300_board.c | 57 ++++++++ include/configs/spear300.h | 260 +++++++++++++++++++++++++++++++++++ 6 files changed, 412 insertions(+), 0 deletions(-) create mode 100755 board/spear/spear300/Makefile create mode 100755 board/spear/spear300/config.mk create mode 100755 board/spear/spear300/spr300_board.c create mode 100755 include/configs/spear300.h

diff --git a/MAKEALL b/MAKEALL index ab1bb6f..e280e37 100755 --- a/MAKEALL +++ b/MAKEALL @@ -572,6 +572,7 @@ LIST_ARM9=" \ sheevaplug \ smdk2400 \ smdk2410 \ + spear300 \ trab \ VCMA9 \ versatile \ diff --git a/Makefile b/Makefile index 536ccb3..4489167 100644 --- a/Makefile +++ b/Makefile @@ -3056,6 +3056,9 @@ smdk2400_config : unconfig smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

+spear300_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs spear300 spear spear + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile new file mode 100755 index 0000000..247c302 --- /dev/null +++ b/board/spear/spear300/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spr300_board.o \ + ../common/spr_misc.o +SOBJS := ../common/spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk new file mode 100755 index 0000000..90a6cf9 --- /dev/null +++ b/board/spear/spear300/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DENV_IN_NAND +endif + +# Compile uboot as USB boot firmware +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif + diff --git a/board/spear/spear300/spr300_board.c b/board/spear/spear300/spr300_board.c new file mode 100755 index 0000000..97de0be --- /dev/null +++ b/board/spear/spear300/spr300_board.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_nand.h> + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/** + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } else { + return -1; + } +} diff --git a/include/configs/spear300.h b/include/configs/spear300.h new file mode 100755 index 0000000..59b1f45 --- /dev/null +++ b/include/configs/spear300.h @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR300 1 + +/* + * Ethernet MAC driver configuration + */ +/* #define CONFIG_SPEARMAC */ +/* #define CONFIG_ETHAUTONEG */ +/* #define CONFIG_ETHDEBUG */ + +/* + * USBD driver configuration + */ +#define CONFIG_SPEARUDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm" + +/* + * I2C driver configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_SPEARI2C +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 + +/* #define CONFIG_SYS_I2C_MULTI_EEPROMS */ +/* #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 */ + +/* + * SMI driver configuration + */ +#define CONFIG_SPEARSMI +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_SMI_BASE 0xFC000000 + +/* + * Serial Configuration (PL011) + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0 } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_SERIAL0 0xD0000000 + +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Platform specific defines (SPEAr) + */ +#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) +#define CONFIG_SPEAR_TIMERBASE (0xFC800000) +#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_HZ (26000) + +/* + * Board Specific Defines (SPEAr300) + */ + +/* + * FLASH Configuration + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xF8000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {0xF8000000, 0xF9000000} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* + * NAND FLASH Configuration + */ +#define CONFIG_NAND_SPEAR 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x80000000 +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 + +/* + * FSMC NAND driver configuration + */ +#define CONFIG_SPEAR_FSMCBASE (0x94000000) + +/* + * Command support defines + */ +/* #define CONFIG_CMD_CACHE */ +/* #define CONFIG_CMD_CDP */ +/* #define CONFIG_CMD_DHCP */ +#define CONFIG_CMD_I2C +/* #define CONFIG_CMD_ELF */ +/* #define CONFIG_CMD_PING */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_ENV +/* #define CONFIG_CMD_JFFS2 */ +/* #define CONFIG_CMD_YAFFS2 */ +#define CONFIG_CMD_MEMORY +/* #define CONFIG_CMD_MII */ +/* #define CONFIG_MII */ +/* #define CONFIG_NET_MULTI */ +/* #define CONFIG_CMD_NET */ +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SETFREQ +/* #define CONFIG_CMD_EEPROM */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Default Environment Varible definitions + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyS0 init=/bin/sh" + +/* #define CONFIG_ETHADDR 00:11:22:33:44:55 */ + +/* #define CONFIG_NETMASK 255.255.255.0 */ +/* #define CONFIG_IPADDR 192.168.1.10 */ +/* #define CONFIG_SERVERIP 192.168.1.1 */ +/* #define CONFIG_GATEWAYIP 192.168.1.1 */ +#define CONFIG_ENV_OVERWRITE + +/* + * U-Boot Environment placing definitions. + */ +#ifdef ENV_IN_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock3 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" + +#else +#ifdef CONFIG_ENV_IS_IN_NAND + +#define CONFIG_ENV_OFFSET 0x50000 +#define CONFIG_ENV_SIZE 0x04000 +/* #define CONFIG_ENV_OFFSET_REDUND 0x58000 */ +#define CONFIG_ENV_RANGE 0x10000 + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock8 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x60000 0x4C0000; " \ + "bootm 0x1600000" + +#endif +#endif + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_IDENT_STRING "-SPEAr300" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif /* __CONFIG_H */ +

Signed-off-by: Vipin vipin.kumar@st.com --- MAKEALL | 1 + Makefile | 3 + board/spear/spear320/Makefile | 52 ++++++ board/spear/spear320/config.mk | 42 +++++ board/spear/spear320/spr320_board.c | 58 ++++++ include/configs/spear320.h | 336 +++++++++++++++++++++++++++++++++++ 6 files changed, 492 insertions(+), 0 deletions(-) create mode 100755 board/spear/spear320/Makefile create mode 100755 board/spear/spear320/config.mk create mode 100755 board/spear/spear320/spr320_board.c create mode 100755 include/configs/spear320.h

diff --git a/MAKEALL b/MAKEALL index 3abb4f0..0672ba0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -574,6 +574,7 @@ LIST_ARM9=" \ smdk2410 \ spear300 \ spear310 \ + spear320 \ trab \ VCMA9 \ versatile \ diff --git a/Makefile b/Makefile index 44f1d8b..1f60204 100644 --- a/Makefile +++ b/Makefile @@ -3062,6 +3062,9 @@ spear300_config : unconfig spear310_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs spear310 spear spear

+spear320_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs spear320 spear spear + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile new file mode 100755 index 0000000..1ddd1c2 --- /dev/null +++ b/board/spear/spear320/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spr320_board.o \ + ../common/spr_misc.o +SOBJS := ../common/spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk new file mode 100755 index 0000000..8b7aa05 --- /dev/null +++ b/board/spear/spear320/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2009 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img + +# Environment variables in NAND +ifeq ($(ENV),NAND) +PLATFORM_RELFLAGS += -DENV_IN_NAND +endif + +ifeq ($(FLASH),PNOR) +PLATFORM_RELFLAGS += -DPNOR_FLASH +endif + +ifeq ($(CONSOLE),USB) +PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY +endif + diff --git a/board/spear/spear320/spr320_board.c b/board/spear/spear320/spr320_board.c new file mode 100755 index 0000000..750e303 --- /dev/null +++ b/board/spear/spear320/spr320_board.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 + * Ryan Chen, ST Micoelectronics, ryan.chen@st.com. + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_nand.h> + +int board_init(void) +{ + return spear_board_init(MACH_TYPE_SPEAR300); +} + +/** + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG30) || + ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == + MISC_SOCCFG31)) { + + return spear_nand_init(nand); + } else { + return -1; + } +} diff --git a/include/configs/spear320.h b/include/configs/spear320.h new file mode 100755 index 0000000..1fb0474 --- /dev/null +++ b/include/configs/spear320.h @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR320 1 + +/* + * Ethernet MAC driver configuration + */ +/* #define CONFIG_SPEAR_SMII */ +/* #define CONFIG_SPEARMAC */ +/* #define CONFIG_ETHAUTONEG */ +/* #define CONFIG_ETHDEBUG */ + +/* + * SMII driver configuratin + */ +#ifdef CONFIG_SPEAR_SMII +#define SPR320_SMII0_BASE 0xAA000000 +#define SPR320_SMII0_PHY 0x01 +#endif + + +/* + * USBD driver configuration + */ +#define CONFIG_SPEARUDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm" + +/* + * I2C driver configuration + */ +#define CONFIG_HARD_I2C +#define CONFIG_SPEARI2C +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 + +/* #define CONFIG_SYS_I2C_MULTI_EEPROMS */ +/* #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 */ + +/* + * SMI driver configuration + */ +#if defined(PNOR_FLASH) +#define CONFIG_SPEAR_EMI 1 +#else +#define CONFIG_SPEARSMI 1 +#endif + +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_SMI_BASE 0xFC000000 + +/* + * Serial Configuration (PL011) + */ +#define CONFIG_SPEAR320_CUST_UART 1 + +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_SERIAL0 0xD0000000 + +#ifdef CONFIG_SPEAR320_CUST_UART + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xA3000000 +#define CONFIG_SYS_SERIAL2 0xA4000000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2} +#else +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0 } +#endif + +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Platform specific defines (SPEAr) + */ +#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) +#define CONFIG_SPEAR_TIMERBASE (0xFC800000) +#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_HZ (26000) +#define CONFIG_SPEAR_EMIBASE (0x40000000) +#define CONFIG_SPEAR_RASBASE (0xB3000000) + +/* + * Board Specific Defines (SPEAr320) + */ + +/* + * FLASH Configuration + */ +#if defined(CONFIG_SPEARSMI) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xF8000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {0xF8000000, 0xF9000000} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +#elif defined(CONFIG_SPEAR_EMI) + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +/* #define CONFIG_SYS_FLASH_PROTECTION */ +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 +#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) + +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +/* For Intel/ST legacy flash */ +/* #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes" */ + +#endif +/* + * NAND FLASH Configuration + */ +#define CONFIG_NAND_SPEAR 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x50000000 +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 + +/* + * FSMC NAND driver configuration + */ +#define CONFIG_SPEAR_FSMCBASE (0x4C000000) + +/* + * Command support defines + */ +/* #define CONFIG_CMD_CACHE */ +/* #define CONFIG_CMD_CDP */ +/* #define CONFIG_CMD_DHCP */ +#define CONFIG_CMD_I2C +/* #define CONFIG_CMD_ELF */ +/* #define CONFIG_CMD_PING */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_ENV +/* #define CONFIG_CMD_JFFS2 */ +/* #define CONFIG_CMD_YAFFS2 */ +#define CONFIG_CMD_MEMORY +/* #define CONFIG_CMD_MII */ +/* #define CONFIG_MII */ +/* #define CONFIG_NET_MULTI */ +/* #define CONFIG_CMD_NET */ +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SETFREQ +/* #define CONFIG_CMD_EEPROM */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +/* + * Default Environment Varible definitions + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyS0 init=/bin/sh" + +/* #define CONFIG_ETHADDR 00:11:22:33:44:55 */ + +/* #define CONFIG_NETMASK 255.255.255.0 */ +/* #define CONFIG_IPADDR 192.168.1.10 */ +/* #define CONFIG_SERVERIP 192.168.1.1 */ +/* #define CONFIG_GATEWAYIP 192.168.1.1 */ +#define CONFIG_ENV_OVERWRITE + +/* + * U-Boot Environment placing definitions. + */ +#ifdef ENV_IN_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif + +#if defined(CONFIG_ENV_IS_IN_FLASH) +#ifdef CONFIG_SPEARSMI +/* + * Environment is in serial NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock3 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" + +#elif defined(CONFIG_SPEAR_EMI) +/* + * Environment is in parallel NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00060000 +#define CONFIG_ENV_SECT_SIZE 0x00020000 + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock8 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 "\ + "0x4C0000; bootm 0x1600000" + +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) + +#elif defined(CONFIG_ENV_IS_IN_NAND) + +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_SIZE 0x04000 +/* #define CONFIG_ENV_OFFSET_REDUND 0x58000 */ +#define CONFIG_ENV_RANGE 0x10000 + +#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ + "root=/dev/mtdblock12 " \ + "rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 "\ + "0x60000 0x4C0000; " \ + "bootm 0x1600000" + +#endif + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_IDENT_STRING "-SPEAr320" +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif /* __CONFIG_H */ +

Dear Wolfgang,

In message 1260955110-5656-6-git-send-email-vipin.kumar@st.com you wrote:

...

Signed-off-by: Vipin vipin.kumar@st.com

...

...

+int misc_init_r(void) +{ +#if defined(CONFIG_CMD_NET)

• uchar mac_id[6];
• if (!i2c_read_mac(mac_id))
• eth_setenv_enetaddr("ethaddr", mac_id);

+#endif

• setenv("verify", "n");

NAK.

Please do not enforce such a policy on all your users.  Let them decide if they want this, or not.

...

Source modified to if (ethaddr from environment fails) read mac from i2c memory This should be ok. Right

...

+int do_setfreq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{

• void (*sram_setfreq) (unsigned int, unsigned int);
• unsigned int frequency;
• if (argc != 3) {
• printf("Usage:\n%s\n", cmdtp->usage);
• return 1;
• }
• frequency = simple_strtoul(argv[2], NULL, 0);
• if (frequency > 333) {
• printf("Frequency is limited to 333MHz\n");
• return 1;
• }
• sram_setfreq = memcpy((void *)0xD2801000, setfreq, setfreq_sz);
• if (!strcmp(argv[1], "ddr")) {
• sram_setfreq(DDR, frequency);
• printf("DDR frequency changed to %u\n", frequency);
• } else if (!strcmp(argv[1], "cpu")) {
• sram_setfreq(CPU, frequency);
• printf("CPU frequency changed to %u\n", frequency);
• } else {
• printf("Usage:\n%s\n", cmdtp->usage);
• return 1;
• }
• return 0;

+}

+U_BOOT_CMD(setfreq, 3, 1, do_setfreq,

• "change ddr/cpu frequency", "device[ddr/cpu] frequency");

+#endif

Do we need a new custom command for this? Either allow setting by environment variable only ("cpuclk" is already used by a number of systems), or use a common command name ("chip_config" was chosen for this after some discussion a while ago).

Code modified to use chip_config. this command is implemented in board specific file. I guess that should be ok since there is no standard interface for the command

Also, is no further checking needed? Can I set arbitrary frequencies, like 307 for CPU and 277 for DDR?

Yes, all values below 333 are acceptable. This command is added for testing purposes only so no further checking is required

...

• if ((buf[0] == 0x55) && (buf[1] == 0xAA)) {
• /* Valid MAC address is saved in I2C EEPROM,
• read the MAC address from the
• EEPROM & update the buffer */

Incorrect multiline comment once more.

Corrected multiline comments globally

...

• buf[0] = 0x55;
• buf[1] = 0xAA;
• i2c_write(0x50,         /* Chip address */
• 0x0,          /* Offset */
• 1,            /* Address length */
• buf,          /* buffer */
• 2);           /* Length */

Argh. Please do not do this.

Ok, modified to single line function call

...

• buf[0] = 0x44;
• buf[1] = 0x66;
• i2c_read(0x50,          /* Chip address */
• 0x0,           /* Offset */
• 1,             /* Address length */
• buf,           /* buffer */
• 2);            /* Length */

Ok, modified to single line function call

...

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 11c1547..412cad6 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -27,6 +27,10 @@  #include <common.h>  #include <command.h>

+#if defined(CONFIG_SPEAR600) || defined(CONFIG_SPEAR3XX) +#include <asm/arch/spr_xloader_table.h> +#endif

DECLARE_GLOBAL_DATA_PTR;

static void print_num(const char *, ulong); @@ -339,6 +343,22 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])  #endif       printf ("baudrate    = %d bps\n", bd->bi_baudrate);

+#if defined(CONFIG_SPEAR600) || defined(CONFIG_SPEAR3XX)

• if (bd->dramfreq == -1)
• printf("DDR Freq    = Not Known\n");
• else
• printf("DDR Freq    = %d\n", bd->dramfreq);
• if (bd->dramtype == DDRMOBILE)
• printf("DDR Type    = MOBILE\n");
• else if (bd->dramtype == DDR2)
• printf("DDR Type    = DDR2\n");
• else
• printf("DDR Type    = Not Known\n");
• printf("Xloader Rev = %s\n", bd->version);

+#endif

return 0;  }

I don't like such board-specific code in this common file.

Ok. But then bdinfo should ideally contain a generic callback to be implemented by board specific code.

...

diff --git a/include/configs/spear600.h b/include/configs/spear600.h new file mode 100755 index 0000000..755114d

...

...

+/* #define CONFIG_ETHADDR                    00:11:22:33:44:55 */

+/* #define CONFIG_NETMASK                    255.255.255.0 */ +/* #define CONFIG_IPADDR                     192.168.1.10 */ +/* #define CONFIG_SERVERIP                   192.168.1.1 */ +/* #define CONFIG_GATEWAYIP                  192.168.1.1 */

Please remove.

Ok.removed commented code

Regards Vipin

Dear Wolfgang,

...

Signed-off-by: Vipin vipin.kumar@st.com

common/main.c                         |    2 +  drivers/serial/usbtty.h               |    2 +  drivers/usb/gadget/Makefile           |    1 +  drivers/usb/gadget/spr_udc.c          |  996 +++++++++++++++++++++++++++++++++  include/asm-arm/arch-spear/spr_misc.h |  126 +++++  include/usb/spr_udc.h                 |  227 ++++++++  6 files changed, 1354 insertions(+), 0 deletions(-)  mode change 100644 => 100755 drivers/serial/usbtty.h  mode change 100644 => 100755 drivers/usb/gadget/Makefile  create mode 100755 drivers/usb/gadget/spr_udc.c  create mode 100644 include/asm-arm/arch-spear/spr_misc.h  create mode 100755 include/usb/spr_udc.h

Please split into two patches: one with generic usbd driver, and the second adding support for SPEAr.

Ok. Accepted. patch-set v2 would contain the changes

...

diff --git a/common/main.c b/common/main.c index 10d8904..79f3018 100644 --- a/common/main.c +++ b/common/main.c @@ -397,6 +397,7 @@ void main_loop (void)

debug ("### main_loop: bootcmd="%s"\n", s ? s : "<UNDEFINED>");

+#if !defined(CONFIG_SPEAR_USBTTY)       if (bootdelay >= 0 && s && !abortboot (bootdelay)) {  # ifdef CONFIG_AUTOBOOT_KEYED               int prev = disable_ctrlc(1);    /* disable Control C checking */ @@ -413,6 +414,7 @@ void main_loop (void)               disable_ctrlc(prev);    /* restore Control C checking */  # endif       } +# endif

Why would this be needed?

We also use u-boot as a firmware which runs on the board in a special mode in which the firmware fetches and burns images into NOR/NAND flashes. Under this mode, we would like to always jump to u-boot prompt. Also, the bootdelay variable should remain unchanged as we save default environment variables as well.

...

diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/spr_udc.c new file mode 100755 index 0000000..5b135c7 --- /dev/null +++ b/drivers/usb/gadget/spr_udc.c

...

...

+/* Some kind of debugging output... */ +#if 1 +#define UDCDBG(str) +#define UDCDBGA(fmt, args...) +#else +#define UDCDBG(str) serial_printf(str "\n") +#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args) +#endif

This looks wrong. Should that be a "#ifndef DEBUG" instead of "#if 1"?

And cannot we use standard debug facilities?

Ok, changed to #ifndef DEBUG The standard debug facilities use printf and we also test and use this for usbtty feature. So, a serial_printf is required

...

+static struct udc_endp_regs *const outep_regs_p =

• &((struct udc_regs *const)CONFIG_SYS_USBD_BASE)->out_regs[0];

+static struct udc_endp_regs *const inep_regs_p =

• &((struct udc_regs *const)CONFIG_SYS_USBD_BASE)->in_regs[0];

+/*

• • udc_state_transition - Write the next packet to TxFIFO.
• • @initial: Initial state.
• • @final:   Final state.
• • Helper function to implement device state changes. The device states and
• • the events that transition between them are:
• • STATE_ATTACHED
• • ||      /\
• • /      ||
• • DEVICE_HUB_CONFIGURED                   DEVICE_HUB_RESET
• • ||      /\
• • /      ||
• • STATE_POWERED
• • ||      /\
• • /      ||
• • DEVICE_RESET                            DEVICE_POWER_INTERRUPTION
• • ||      /\
• • /      ||
• • STATE_DEFAULT
• • ||      /\
• • /      ||
• • DEVICE_ADDRESS_ASSIGNED                 DEVICE_RESET
• • ||      /\
• • /      ||
• • STATE_ADDRESSED
• • ||      /\
• • /      ||
• • DEVICE_CONFIGURED                       DEVICE_DE_CONFIGURED
• • ||      /\
• • /      ||
• • STATE_CONFIGURED
• • udc_state_transition transitions up (in the direction from STATE_ATTACHED
• • to STATE_CONFIGURED) from the specified initial state to the specified final
• • state, passing through each intermediate state on the way. If the initial
• • state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
• • no state transitions will take place.
• • udc_state_transition also transitions down (in the direction from
• • STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
• • specified final state, passing through each intermediate state on the way.
• • If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
• • state, then no state transitions will take place.
• • This function must only be called with interrupts disabled.
• */

+static void udc_state_transition(usb_device_state_t initial,

• usb_device_state_t final)

...

...

+/* Stall endpoint */ +static void udc_stall_ep(u32 ep_num)

...

...

+static void *get_fifo(int ep_num, int in)

...

...

+static short usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)

...

...

+static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)

...

So far this code looks pretty generic to me.

No, this code is not generic.

...

+/*

• • spear_write_noniso_tx_fifo - Write the next packet to TxFIFO.
• • @endpoint:                Endpoint pointer.
• • If the endpoint has an active tx_urb, then the next packet of data from the
• • URB is written to the tx FIFO.  The total amount of data in the urb is given
• • by urb->actual_length.  The maximum amount of data that can be sent in any
• • one packet is given by endpoint->tx_packetSize.  The number of data bytes
• • from this URB that have already been transmitted is given by endpoint->sent.
• • endpoint->last is updated by this routine with the number of data bytes
• • transmitted in this packet.
• */

+static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance

• *endpoint)

Now her eit becomes clearly SPEAr-specific. Should this not be split into separate source files to allow reuse of the common code by other processors?

Again, all the code is spear specific. Probably, only the unction names are confusing

...

• /* This ensures that USBD packet fifo is accessed
• :- through word aligned pointer or
• :- through non word aligned pointer but only with a
• max length to make the next packet word aligned */

Incorrect multiline comment style.

Ok. Corrected globally

Too long lines.

I assume line length of 80 is acceptable. Right?

...

• /* This rx interrupt must be for a control write data
• * stage packet.
• *
• * We don't support control write data stages.
• * We should never end up here.
• */

Incorrect multiline comment style. Please fix globally.

Ok. Corrected globally

...

+struct misc_regs {

...

...

• u32 BIST5_RSLT_REG;             /* 0x118 */
• u32 SYST_ERROR_REG;             /* 0x11C */

...

...

• u32 RAS_GPP1_IN;                /* 0x8000 */

Variable names must be lower case.

Ok. Corrected globally

Best Reagrds Vipin Kumar

Dear Wolfgang,

In message 83d1d72b0912182302m68e7ba06q5e23a695f85534f@mail.gmail.com you wrote:

...

...

...

--- a/common/main.c +++ b/common/main.c @@ -397,6 +397,7 @@ void main_loop (void)

debug ("### main_loop: bootcmd="%s"\n", s ? s : "<UNDEFI> NED>");

+#if !defined(CONFIG_SPEAR_USBTTY)       if (bootdelay >= 0 && s && !abortboot (bootdelay)) {  # ifdef CONFIG_AUTOBOOT_KEYED               int prev = disable_ctrlc(1);    /* dis> able Control C checking */ @@ -413,6 +414,7 @@ void main_loop (void)               disable_ctrlc(prev);    /* restore Contr> ol C checking */  # endif       } +# endif

Why would this be needed?

We also use u-boot as a firmware which runs on the board in a special mode in which the firmware fetches and burns images into NOR/NAND flashes. Under this mode, we would like to always jump to u-boot prompt.

This can be done by plain config settings. No need to chang ethe code.

I didn't get this. I want the uboot behavior as if bootdelay is set to -1. And offcourse without changing bootdelay. I could not get if this can be done by any plain config setting Please let me know if I am missing something

...

Also, the bootdelay variable should remain unchanged as we save default environment variables as well.

Think of a different way to switch modes, please. I don't accept this change to common code.

Regards Vipin

Dear Vipin KUMAR,

In message 1260955110-5656-2-git-send-email-vipin.kumar@st.com you wrote:

Signed-off-by: Vipin vipin.kumar@st.com

drivers/i2c/Makefile | 1 + drivers/i2c/spr_i2c.c | 321 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_i2c.h | 143 +++++++++++++++ 3 files changed, 465 insertions(+), 0 deletions(-) mode change 100644 => 100755 drivers/i2c/Makefile create mode 100755 drivers/i2c/spr_i2c.c create mode 100755 include/asm-arm/arch-spear/spr_i2c.h

Your patch order is, um, sub-optimal.

You start adding an I2C driver for a non-existing CPU here.

This makes no sense, please reorder.

--- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o +COBJS-$(CONFIG_SPEARI2C) += spr_i2c.o

Please keep lists sorted (fix globally).

+/**

• • i2c_setfreq - Set i2c working mode frequency
• • Set i2c working mode frequency
• */

Incorrect multiline comment style. Please fix globally.

+static void set_speed(int i2c_spd) +{

• unsigned int cntl;
• if (i2c_spd == IC_SPEED_MODE_MAX) {

• cntl = readl(&i2c_regs_p->ic_con);
  

• cntl |= IC_CON_SPH | IC_CON_SPL;
  

• writel(cntl, &i2c_regs_p->ic_con);
  

• i2c_setfreq(MIN_HS_SCL_HIGHTIME, MIN_HS_SCL_LOWTIME);
  

• } else if (i2c_spd == IC_SPEED_MODE_FAST) {

• cntl = readl(&i2c_regs_p->ic_con);
  

• cntl |= IC_CON_SPH;
  

• cntl &= ~IC_CON_SPL;
  

• writel(cntl, &i2c_regs_p->ic_con);
  

• i2c_setfreq(MIN_FS_SCL_HIGHTIME, MIN_FS_SCL_LOWTIME);
  

• } else if (i2c_spd == IC_SPEED_MODE_STANDARD) {

• cntl = readl(&i2c_regs_p->ic_con);
  

• cntl |= IC_CON_SPF;
  

• cntl &= ~IC_CON_SPL;
  

• writel(cntl, &i2c_regs_p->ic_con);
  

• i2c_setfreq(MIN_SS_SCL_HIGHTIME, MIN_SS_SCL_LOWTIME);
  

• }

It seems you can move the lines

writel(cntl, &i2c_regs_p->ic_con); i2c_setfreq(MIN_FS_SCL_HIGHTIME, MIN_FS_SCL_LOWTIME);

out of the if/else blocks and make them common code.

+void i2c_set_bus_speed(int speed) +{

• if (speed >= I2C_MAX_SPEED)

• set_speed(IC_SPEED_MODE_MAX);
  

• else
• if (speed >= I2C_FAST_SPEED)

Missing braces (mandatory for multiline statements).

• set_speed(IC_SPEED_MODE_FAST);
  

• else

• set_speed(IC_SPEED_MODE_STANDARD);
  

+}

+/**

• • i2c_get_bus_speed - Gets the i2c speed
• • Gets the i2c speed.
• */

+int i2c_get_bus_speed(void) +{

• if (((readl(&i2c_regs_p->ic_con) & IC_CON_SPH) == IC_CON_SPH) &&

•   ((readl(&i2c_regs_p->ic_con) & IC_CON_SPL) == IC_CON_SPL)) {
  

• return I2C_MAX_SPEED;
  

• } else if (((readl(&i2c_regs_p->ic_con) & IC_CON_SPH) == IC_CON_SPH) &&

•   ((readl(&i2c_regs_p->ic_con) & IC_CON_SPL) == 0)) {
  

• return I2C_FAST_SPEED;
  

• } else if (((readl(&i2c_regs_p->ic_con) & IC_CON_SPF) == IC_CON_SPF) &&

•   ((readl(&i2c_regs_p->ic_con) & IC_CON_SPL) == 0)) {
  

• return I2C_STANDARD_SPEED;
  

• }

It makes no sense to run "readl(&i2c_regs_p->ic_con)" six times - run it once and latch the value.

Also I tend to think the logic can be written clearer.

+void i2c_init(int speed, int slaveadd) +{

• unsigned int enbl;
• /* Disable i2c */
• enbl = readl(&i2c_regs_p->ic_enable);
• enbl &= ~IC_ENABLE_0B;
• writel(enbl, &i2c_regs_p->ic_enable);
• writel((IC_CON_SD | IC_CON_SPF | IC_CON_MM), &i2c_regs_p->ic_con);
• writel(IC_TL0, &i2c_regs_p->ic_rx_tl);
• writel(IC_TL0, &i2c_regs_p->ic_tx_tl);

Is this duplication intentional? If so, a comment is needed to explain why.

+/**

• • i2c_probe - Probe the i2c chip
• • TBD
• */

+int i2c_probe(uchar chip) +{

• return 0;

+}

Please do not add dead code.

+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{

• unsigned long start_time_rx;
• if (buffer == NULL) {

• printf("I2C read: buffer is invalid\n");
  

• return 1;
  

• }
• if (alen > 1) {

• printf("I2C read: addr len %d not supported\n", alen);
  

• return 1;
  

• }
• if (addr + len > 256) {

• printf("I2C read: address out of range\n");
  

• return 1;
  

• }
• if (i2c_wait_for_bb())

• return 1;
  

Why no error message here?

• i2c_setaddress(chip);
• writel(addr, &i2c_regs_p->ic_cmd_data);
• start_time_rx = get_timer_masked();
• while (len) {

• writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
  

• if ((readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) ==
  

• 		IC_STATUS_RFNE) {
  

• 	*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
  

• 	len--;
  

• 	start_time_rx = get_timer_masked();
  

• } else {
  

• 	if (get_timer(start_time_rx) > I2C_BYTE_TO)
  

• 		return 1;
  

Why no error message here?

• udelay(4000);

Why is this needed?

• if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET))

• readl(&i2c_regs_p->ic_clr_stop_det);
  

• if (i2c_wait_for_bb())

• return 1;
  

Why no error message here?

• i2c_flush_rxfifo();
• return 0;

+}

+/**

• • i2c_write - Write to i2c memory
• • @chip: target i2c address
• • @addr: address to read from
• • @alen:
• • @buffer: buffer for read data
• • @len: no of bytes to be read
• • Write to i2c memory.
• */

+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{

• int nb = len;
• unsigned long start_time_tx;
• if (buffer == NULL) {

• printf("I2C write: buffer is invalid\n");
  

• return 1;
  

• }
• if (alen > 1) {

• printf("I2C write: addr len %d not supported\n", alen);
  

• return 1;
  

• }
• if (addr + len > 256) {

• printf("I2C write: address out of range\n");
  

• return 1;
  

• }
• if (i2c_wait_for_bb())

• return 1;
  

• i2c_setaddress(chip);
• writel(addr, &i2c_regs_p->ic_cmd_data);
• start_time_tx = get_timer_masked();
• while (len) {

• if ((readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF)
  

• 	== IC_STATUS_TFNF) {
  

• 	writel(*buffer, &i2c_regs_p->ic_cmd_data);
  

• 	buffer++;
  

• 	len--;
  

• 	start_time_tx = get_timer_masked();
  

• } else {
  

• 	if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO))
  

• 		return 1;
  

• }
  

• }
• udelay(4000);
• if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET))

• readl(&i2c_regs_p->ic_clr_stop_det);
  

• if (i2c_wait_for_bb())

• return 1;
  

• i2c_flush_rxfifo();
• return 0;

+}

This shares a _lot_ of common code with i2c_read() - factor out?

Best regards,

Wolfgang Denk