This patch adds the DTS source files needed for stm32f746-disco board based on the stm32f429/469 files from current linux kernel.

Signed-off-by: Michael Kurz michi.kurz@gmail.com ---

Changes in v2: None

arch/arm/dts/Makefile | 2 + arch/arm/dts/armv7-m.dtsi | 24 + arch/arm/dts/stm32f746-disco.dts | 154 +++ arch/arm/dts/stm32f746.dtsi | 397 +++++++ configs/stm32f746-disco_defconfig | 1 + include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1324 +++++++++++++++++++++++ 6 files changed, 1902 insertions(+) create mode 100644 arch/arm/dts/armv7-m.dtsi create mode 100644 arch/arm/dts/stm32f746-disco.dts create mode 100644 arch/arm/dts/stm32f746.dtsi create mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 836a8c4..0cb0d07 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -155,6 +155,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \

dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb

+dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb + dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/dts/armv7-m.dtsi b/arch/arm/dts/armv7-m.dtsi new file mode 100644 index 0000000..e0a6bf2 --- /dev/null +++ b/arch/arm/dts/armv7-m.dtsi @@ -0,0 +1,24 @@ +#include "skeleton.dtsi" + +/ { + nvic: interrupt-controller@e000e100 { + compatible = "arm,armv7m-nvic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe000e100 0xc00>; + }; + + systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&nvic>; + ranges; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts new file mode 100644 index 0000000..7b652f0 --- /dev/null +++ b/arch/arm/dts/stm32f746-disco.dts @@ -0,0 +1,154 @@ +/* + * Copyright 2016 - Michael Kurz michi.kurz@gmail.com + * + * Based on: + * stm32f469-disco.dts from Linux + * Copyright 2016 - Lee Jones lee.jones@linaro.org + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" + +/ { + model = "STMicroelectronics STM32F746-DISCO board"; + compatible = "st,stm32f746-disco", "st,stm32f746"; + + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x800000>; + }; + + aliases { + serial0 = &usart1; + spi0 = &qspi; + }; + + soc { + pin-controller { + usart1_pins_disco: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_pins_disco: ethernet@0 { + pins { + pinmux = <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>; + slew-rate = <2>; + }; + }; + + qspi_pins_disco: qspi@0 { + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&mac { + status = "okay"; + pinctrl-0 = <&ethernet_pins_disco>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_disco>; + pinctrl-names = "default"; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins_disco>; + pinctrl-names = "default"; + status = "okay"; + + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "spi-flash"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi new file mode 100644 index 0000000..3a6d1b8 --- /dev/null +++ b/arch/arm/dts/stm32f746.dtsi @@ -0,0 +1,397 @@ +/* + * Copyright 2016 - Michael Kurz michi.kurz@gmail.com + * + * Based on: + * stm32f429.dtsi from Linux + * Copyright 2015 - Maxime Coquelin mcoquelin.stm32@gmail.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&rcc 0 128>; + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&rcc 0 129>; + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&rcc 0 130>; + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 131>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&rcc 0 132>; + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&rcc 0 133>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 0 145>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 0 146>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 0 147>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 0 148>; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 0 158>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 0 159>; + status = "disabled"; + }; + + usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + status = "disabled"; + }; + + usart6: serial@40011400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 0 165>; + status = "disabled"; + }; + + spi1: spi@40013000 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40013000 0x400>; + interrupts = <35>; + clock-names = "spi1"; + clocks = <&rcc 0 172>; + num-cs = <1>; + big-endian; + status = "disabled"; + }; + + syscfg: system-config@40013800 { + compatible = "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, + <2>, + <3>, + <6>, + <7>, + <8>, + <9>, + <10>, + <23>, + <40>, + <41>, + <42>, + <62>, + <76>; + }; + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f746-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 0>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 1>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 2>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 3>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 4>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 5>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 6>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 7>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 8>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 9>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 10>; + st,bank-name = "GPIOK"; + }; + }; + + rcc: rcc@40023810 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + }; + + dma1: dma-controller@40026000 { + compatible = "st,stm32-dma"; + reg = <0x40026000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc 0 21>; + #dma-cells = <4>; + }; + + dma2: dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc 0 22>; + #dma-cells = <4>; + st,mem2mem; + }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <61>, <62>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + snps,mixed-burst; + dma-ranges; + status = "disabled"; + }; + + usbotg_hs: usb@40040000 { + compatible = "snps,dwc2"; + dma-ranges; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 29>; + clock-names = "otg"; + status = "disabled"; + }; + + rng: rng@50060800 { + compatible = "st,stm32-rng"; + reg = <0x50060800 0x400>; + interrupts = <80>; + clocks = <&rcc 0 38>; + }; + + qspi: quadspi@A0001000 { + compatible = "st,stm32-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <92>; + clock-names = "qspi"; + clocks = <&rcc 0 65>; + spi-max-frequency = <108000000>; + status = "disabled"; + }; + }; +}; + +&systick { + clocks = <&rcc 1 0>; + status = "okay"; +}; diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 6d71d0a..7f6a442 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_STM32=y CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h new file mode 100644 index 0000000..6348c6a --- /dev/null +++ b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h @@ -0,0 +1,1324 @@ +#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H +#define _DT_BINDINGS_STM32F746_PINFUNC_H + +#define STM32F746_PA0_FUNC_GPIO 0x0 +#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2 +#define STM32F746_PA0_FUNC_TIM5_CH1 0x3 +#define STM32F746_PA0_FUNC_TIM8_ETR 0x4 +#define STM32F746_PA0_FUNC_USART2_CTS 0x8 +#define STM32F746_PA0_FUNC_UART4_TX 0x9 +#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb +#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc +#define STM32F746_PA0_FUNC_EVENTOUT 0x10 +#define STM32F746_PA0_FUNC_ANALOG 0x11 + +#define STM32F746_PA1_FUNC_GPIO 0x100 +#define STM32F746_PA1_FUNC_TIM2_CH2 0x102 +#define STM32F746_PA1_FUNC_TIM5_CH2 0x103 +#define STM32F746_PA1_FUNC_USART2_RTS 0x108 +#define STM32F746_PA1_FUNC_UART4_RX 0x109 +#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a +#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b +#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c +#define STM32F746_PA1_FUNC_LCD_R2 0x10f +#define STM32F746_PA1_FUNC_EVENTOUT 0x110 +#define STM32F746_PA1_FUNC_ANALOG 0x111 + +#define STM32F746_PA2_FUNC_GPIO 0x200 +#define STM32F746_PA2_FUNC_TIM2_CH3 0x202 +#define STM32F746_PA2_FUNC_TIM5_CH3 0x203 +#define STM32F746_PA2_FUNC_TIM9_CH1 0x204 +#define STM32F746_PA2_FUNC_USART2_TX 0x208 +#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209 +#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c +#define STM32F746_PA2_FUNC_LCD_R1 0x20f +#define STM32F746_PA2_FUNC_EVENTOUT 0x210 +#define STM32F746_PA2_FUNC_ANALOG 0x211 + +#define STM32F746_PA3_FUNC_GPIO 0x300 +#define STM32F746_PA3_FUNC_TIM2_CH4 0x302 +#define STM32F746_PA3_FUNC_TIM5_CH4 0x303 +#define STM32F746_PA3_FUNC_TIM9_CH2 0x304 +#define STM32F746_PA3_FUNC_USART2_RX 0x308 +#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b +#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c +#define STM32F746_PA3_FUNC_LCD_B5 0x30f +#define STM32F746_PA3_FUNC_EVENTOUT 0x310 +#define STM32F746_PA3_FUNC_ANALOG 0x311 + +#define STM32F746_PA4_FUNC_GPIO 0x400 +#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406 +#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407 +#define STM32F746_PA4_FUNC_USART2_CK 0x408 +#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d +#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e +#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f +#define STM32F746_PA4_FUNC_EVENTOUT 0x410 +#define STM32F746_PA4_FUNC_ANALOG 0x411 + +#define STM32F746_PA5_FUNC_GPIO 0x500 +#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502 +#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504 +#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506 +#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b +#define STM32F746_PA5_FUNC_LCD_R4 0x50f +#define STM32F746_PA5_FUNC_EVENTOUT 0x510 +#define STM32F746_PA5_FUNC_ANALOG 0x511 + +#define STM32F746_PA6_FUNC_GPIO 0x600 +#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602 +#define STM32F746_PA6_FUNC_TIM3_CH1 0x603 +#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604 +#define STM32F746_PA6_FUNC_SPI1_MISO 0x606 +#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a +#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e +#define STM32F746_PA6_FUNC_LCD_G2 0x60f +#define STM32F746_PA6_FUNC_EVENTOUT 0x610 +#define STM32F746_PA6_FUNC_ANALOG 0x611 + +#define STM32F746_PA7_FUNC_GPIO 0x700 +#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702 +#define STM32F746_PA7_FUNC_TIM3_CH2 0x703 +#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704 +#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706 +#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a +#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c +#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d +#define STM32F746_PA7_FUNC_EVENTOUT 0x710 +#define STM32F746_PA7_FUNC_ANALOG 0x711 + +#define STM32F746_PA8_FUNC_GPIO 0x800 +#define STM32F746_PA8_FUNC_MCO1 0x801 +#define STM32F746_PA8_FUNC_TIM1_CH1 0x802 +#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804 +#define STM32F746_PA8_FUNC_I2C3_SCL 0x805 +#define STM32F746_PA8_FUNC_USART1_CK 0x808 +#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b +#define STM32F746_PA8_FUNC_LCD_R6 0x80f +#define STM32F746_PA8_FUNC_EVENTOUT 0x810 +#define STM32F746_PA8_FUNC_ANALOG 0x811 + +#define STM32F746_PA9_FUNC_GPIO 0x900 +#define STM32F746_PA9_FUNC_TIM1_CH2 0x902 +#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905 +#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906 +#define STM32F746_PA9_FUNC_USART1_TX 0x908 +#define STM32F746_PA9_FUNC_DCMI_D0 0x90e +#define STM32F746_PA9_FUNC_EVENTOUT 0x910 +#define STM32F746_PA9_FUNC_ANALOG 0x911 + +#define STM32F746_PA10_FUNC_GPIO 0xa00 +#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02 +#define STM32F746_PA10_FUNC_USART1_RX 0xa08 +#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b +#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e +#define STM32F746_PA10_FUNC_EVENTOUT 0xa10 +#define STM32F746_PA10_FUNC_ANALOG 0xa11 + +#define STM32F746_PA11_FUNC_GPIO 0xb00 +#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02 +#define STM32F746_PA11_FUNC_USART1_CTS 0xb08 +#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a +#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b +#define STM32F746_PA11_FUNC_LCD_R4 0xb0f +#define STM32F746_PA11_FUNC_EVENTOUT 0xb10 +#define STM32F746_PA11_FUNC_ANALOG 0xb11 + +#define STM32F746_PA12_FUNC_GPIO 0xc00 +#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02 +#define STM32F746_PA12_FUNC_USART1_RTS 0xc08 +#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09 +#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a +#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b +#define STM32F746_PA12_FUNC_LCD_R5 0xc0f +#define STM32F746_PA12_FUNC_EVENTOUT 0xc10 +#define STM32F746_PA12_FUNC_ANALOG 0xc11 + +#define STM32F746_PA13_FUNC_GPIO 0xd00 +#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01 +#define STM32F746_PA13_FUNC_EVENTOUT 0xd10 +#define STM32F746_PA13_FUNC_ANALOG 0xd11 + +#define STM32F746_PA14_FUNC_GPIO 0xe00 +#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01 +#define STM32F746_PA14_FUNC_EVENTOUT 0xe10 +#define STM32F746_PA14_FUNC_ANALOG 0xe11 + +#define STM32F746_PA15_FUNC_GPIO 0xf00 +#define STM32F746_PA15_FUNC_JTDI 0xf01 +#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02 +#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05 +#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06 +#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07 +#define STM32F746_PA15_FUNC_UART4_RTS 0xf09 +#define STM32F746_PA15_FUNC_EVENTOUT 0xf10 +#define STM32F746_PA15_FUNC_ANALOG 0xf11 + + +#define STM32F746_PB0_FUNC_GPIO 0x1000 +#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002 +#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003 +#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004 +#define STM32F746_PB0_FUNC_UART4_CTS 0x1009 +#define STM32F746_PB0_FUNC_LCD_R3 0x100a +#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b +#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c +#define STM32F746_PB0_FUNC_EVENTOUT 0x1010 +#define STM32F746_PB0_FUNC_ANALOG 0x1011 + +#define STM32F746_PB1_FUNC_GPIO 0x1100 +#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102 +#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103 +#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104 +#define STM32F746_PB1_FUNC_LCD_R6 0x110a +#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b +#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c +#define STM32F746_PB1_FUNC_EVENTOUT 0x1110 +#define STM32F746_PB1_FUNC_ANALOG 0x1111 + +#define STM32F746_PB2_FUNC_GPIO 0x1200 +#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207 +#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208 +#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a +#define STM32F746_PB2_FUNC_EVENTOUT 0x1210 +#define STM32F746_PB2_FUNC_ANALOG 0x1211 + +#define STM32F746_PB3_FUNC_GPIO 0x1300 +#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301 +#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302 +#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306 +#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307 +#define STM32F746_PB3_FUNC_EVENTOUT 0x1310 +#define STM32F746_PB3_FUNC_ANALOG 0x1311 + +#define STM32F746_PB4_FUNC_GPIO 0x1400 +#define STM32F746_PB4_FUNC_NJTRST 0x1401 +#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403 +#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406 +#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407 +#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408 +#define STM32F746_PB4_FUNC_EVENTOUT 0x1410 +#define STM32F746_PB4_FUNC_ANALOG 0x1411 + +#define STM32F746_PB5_FUNC_GPIO 0x1500 +#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503 +#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505 +#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506 +#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507 +#define STM32F746_PB5_FUNC_CAN2_RX 0x150a +#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b +#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c +#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d +#define STM32F746_PB5_FUNC_DCMI_D10 0x150e +#define STM32F746_PB5_FUNC_EVENTOUT 0x1510 +#define STM32F746_PB5_FUNC_ANALOG 0x1511 + +#define STM32F746_PB6_FUNC_GPIO 0x1600 +#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603 +#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604 +#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605 +#define STM32F746_PB6_FUNC_USART1_TX 0x1608 +#define STM32F746_PB6_FUNC_CAN2_TX 0x160a +#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b +#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d +#define STM32F746_PB6_FUNC_DCMI_D5 0x160e +#define STM32F746_PB6_FUNC_EVENTOUT 0x1610 +#define STM32F746_PB6_FUNC_ANALOG 0x1611 + +#define STM32F746_PB7_FUNC_GPIO 0x1700 +#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703 +#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705 +#define STM32F746_PB7_FUNC_USART1_RX 0x1708 +#define STM32F746_PB7_FUNC_FMC_NL 0x170d +#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e +#define STM32F746_PB7_FUNC_EVENTOUT 0x1710 +#define STM32F746_PB7_FUNC_ANALOG 0x1711 + +#define STM32F746_PB8_FUNC_GPIO 0x1800 +#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803 +#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804 +#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805 +#define STM32F746_PB8_FUNC_CAN1_RX 0x180a +#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c +#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d +#define STM32F746_PB8_FUNC_DCMI_D6 0x180e +#define STM32F746_PB8_FUNC_LCD_B6 0x180f +#define STM32F746_PB8_FUNC_EVENTOUT 0x1810 +#define STM32F746_PB8_FUNC_ANALOG 0x1811 + +#define STM32F746_PB9_FUNC_GPIO 0x1900 +#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903 +#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904 +#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905 +#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906 +#define STM32F746_PB9_FUNC_CAN1_TX 0x190a +#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d +#define STM32F746_PB9_FUNC_DCMI_D7 0x190e +#define STM32F746_PB9_FUNC_LCD_B7 0x190f +#define STM32F746_PB9_FUNC_EVENTOUT 0x1910 +#define STM32F746_PB9_FUNC_ANALOG 0x1911 + +#define STM32F746_PB10_FUNC_GPIO 0x1a00 +#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02 +#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05 +#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06 +#define STM32F746_PB10_FUNC_USART3_TX 0x1a08 +#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b +#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c +#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f +#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10 +#define STM32F746_PB10_FUNC_ANALOG 0x1a11 + +#define STM32F746_PB11_FUNC_GPIO 0x1b00 +#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02 +#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05 +#define STM32F746_PB11_FUNC_USART3_RX 0x1b08 +#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b +#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c +#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f +#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10 +#define STM32F746_PB11_FUNC_ANALOG 0x1b11 + +#define STM32F746_PB12_FUNC_GPIO 0x1c00 +#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02 +#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05 +#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06 +#define STM32F746_PB12_FUNC_USART3_CK 0x1c08 +#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a +#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b +#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c +#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d +#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10 +#define STM32F746_PB12_FUNC_ANALOG 0x1c11 + +#define STM32F746_PB13_FUNC_GPIO 0x1d00 +#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02 +#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06 +#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08 +#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a +#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b +#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c +#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10 +#define STM32F746_PB13_FUNC_ANALOG 0x1d11 + +#define STM32F746_PB14_FUNC_GPIO 0x1e00 +#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02 +#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04 +#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06 +#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08 +#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a +#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d +#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10 +#define STM32F746_PB14_FUNC_ANALOG 0x1e11 + +#define STM32F746_PB15_FUNC_GPIO 0x1f00 +#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01 +#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02 +#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04 +#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06 +#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a +#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d +#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10 +#define STM32F746_PB15_FUNC_ANALOG 0x1f11 + + +#define STM32F746_PC0_FUNC_GPIO 0x2000 +#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009 +#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b +#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d +#define STM32F746_PC0_FUNC_LCD_R5 0x200f +#define STM32F746_PC0_FUNC_EVENTOUT 0x2010 +#define STM32F746_PC0_FUNC_ANALOG 0x2011 + +#define STM32F746_PC1_FUNC_GPIO 0x2100 +#define STM32F746_PC1_FUNC_TRACED0 0x2101 +#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106 +#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107 +#define STM32F746_PC1_FUNC_ETH_MDC 0x210c +#define STM32F746_PC1_FUNC_EVENTOUT 0x2110 +#define STM32F746_PC1_FUNC_ANALOG 0x2111 + +#define STM32F746_PC2_FUNC_GPIO 0x2200 +#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206 +#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b +#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c +#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d +#define STM32F746_PC2_FUNC_EVENTOUT 0x2210 +#define STM32F746_PC2_FUNC_ANALOG 0x2211 + +#define STM32F746_PC3_FUNC_GPIO 0x2300 +#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306 +#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b +#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c +#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d +#define STM32F746_PC3_FUNC_EVENTOUT 0x2310 +#define STM32F746_PC3_FUNC_ANALOG 0x2311 + +#define STM32F746_PC4_FUNC_GPIO 0x2400 +#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406 +#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409 +#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c +#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d +#define STM32F746_PC4_FUNC_EVENTOUT 0x2410 +#define STM32F746_PC4_FUNC_ANALOG 0x2411 + +#define STM32F746_PC5_FUNC_GPIO 0x2500 +#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509 +#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c +#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d +#define STM32F746_PC5_FUNC_EVENTOUT 0x2510 +#define STM32F746_PC5_FUNC_ANALOG 0x2511 + +#define STM32F746_PC6_FUNC_GPIO 0x2600 +#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603 +#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604 +#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606 +#define STM32F746_PC6_FUNC_USART6_TX 0x2609 +#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d +#define STM32F746_PC6_FUNC_DCMI_D0 0x260e +#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f +#define STM32F746_PC6_FUNC_EVENTOUT 0x2610 +#define STM32F746_PC6_FUNC_ANALOG 0x2611 + +#define STM32F746_PC7_FUNC_GPIO 0x2700 +#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703 +#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704 +#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707 +#define STM32F746_PC7_FUNC_USART6_RX 0x2709 +#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d +#define STM32F746_PC7_FUNC_DCMI_D1 0x270e +#define STM32F746_PC7_FUNC_LCD_G6 0x270f +#define STM32F746_PC7_FUNC_EVENTOUT 0x2710 +#define STM32F746_PC7_FUNC_ANALOG 0x2711 + +#define STM32F746_PC8_FUNC_GPIO 0x2800 +#define STM32F746_PC8_FUNC_TRACED1 0x2801 +#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803 +#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804 +#define STM32F746_PC8_FUNC_UART5_RTS 0x2808 +#define STM32F746_PC8_FUNC_USART6_CK 0x2809 +#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d +#define STM32F746_PC8_FUNC_DCMI_D2 0x280e +#define STM32F746_PC8_FUNC_EVENTOUT 0x2810 +#define STM32F746_PC8_FUNC_ANALOG 0x2811 + +#define STM32F746_PC9_FUNC_GPIO 0x2900 +#define STM32F746_PC9_FUNC_MCO2 0x2901 +#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903 +#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904 +#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905 +#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906 +#define STM32F746_PC9_FUNC_UART5_CTS 0x2908 +#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a +#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d +#define STM32F746_PC9_FUNC_DCMI_D3 0x290e +#define STM32F746_PC9_FUNC_EVENTOUT 0x2910 +#define STM32F746_PC9_FUNC_ANALOG 0x2911 + +#define STM32F746_PC10_FUNC_GPIO 0x2a00 +#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07 +#define STM32F746_PC10_FUNC_USART3_TX 0x2a08 +#define STM32F746_PC10_FUNC_UART4_TX 0x2a09 +#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a +#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d +#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e +#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f +#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10 +#define STM32F746_PC10_FUNC_ANALOG 0x2a11 + +#define STM32F746_PC11_FUNC_GPIO 0x2b00 +#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07 +#define STM32F746_PC11_FUNC_USART3_RX 0x2b08 +#define STM32F746_PC11_FUNC_UART4_RX 0x2b09 +#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a +#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d +#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e +#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10 +#define STM32F746_PC11_FUNC_ANALOG 0x2b11 + +#define STM32F746_PC12_FUNC_GPIO 0x2c00 +#define STM32F746_PC12_FUNC_TRACED3 0x2c01 +#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07 +#define STM32F746_PC12_FUNC_USART3_CK 0x2c08 +#define STM32F746_PC12_FUNC_UART5_TX 0x2c09 +#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d +#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e +#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10 +#define STM32F746_PC12_FUNC_ANALOG 0x2c11 + +#define STM32F746_PC13_FUNC_GPIO 0x2d00 +#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10 +#define STM32F746_PC13_FUNC_ANALOG 0x2d11 + +#define STM32F746_PC14_FUNC_GPIO 0x2e00 +#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10 +#define STM32F746_PC14_FUNC_ANALOG 0x2e11 + +#define STM32F746_PC15_FUNC_GPIO 0x2f00 +#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10 +#define STM32F746_PC15_FUNC_ANALOG 0x2f11 + + +#define STM32F746_PD0_FUNC_GPIO 0x3000 +#define STM32F746_PD0_FUNC_CAN1_RX 0x300a +#define STM32F746_PD0_FUNC_FMC_D2 0x300d +#define STM32F746_PD0_FUNC_EVENTOUT 0x3010 +#define STM32F746_PD0_FUNC_ANALOG 0x3011 + +#define STM32F746_PD1_FUNC_GPIO 0x3100 +#define STM32F746_PD1_FUNC_CAN1_TX 0x310a +#define STM32F746_PD1_FUNC_FMC_D3 0x310d +#define STM32F746_PD1_FUNC_EVENTOUT 0x3110 +#define STM32F746_PD1_FUNC_ANALOG 0x3111 + +#define STM32F746_PD2_FUNC_GPIO 0x3200 +#define STM32F746_PD2_FUNC_TRACED2 0x3201 +#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203 +#define STM32F746_PD2_FUNC_UART5_RX 0x3209 +#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d +#define STM32F746_PD2_FUNC_DCMI_D11 0x320e +#define STM32F746_PD2_FUNC_EVENTOUT 0x3210 +#define STM32F746_PD2_FUNC_ANALOG 0x3211 + +#define STM32F746_PD3_FUNC_GPIO 0x3300 +#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306 +#define STM32F746_PD3_FUNC_USART2_CTS 0x3308 +#define STM32F746_PD3_FUNC_FMC_CLK 0x330d +#define STM32F746_PD3_FUNC_DCMI_D5 0x330e +#define STM32F746_PD3_FUNC_LCD_G7 0x330f +#define STM32F746_PD3_FUNC_EVENTOUT 0x3310 +#define STM32F746_PD3_FUNC_ANALOG 0x3311 + +#define STM32F746_PD4_FUNC_GPIO 0x3400 +#define STM32F746_PD4_FUNC_USART2_RTS 0x3408 +#define STM32F746_PD4_FUNC_FMC_NOE 0x340d +#define STM32F746_PD4_FUNC_EVENTOUT 0x3410 +#define STM32F746_PD4_FUNC_ANALOG 0x3411 + +#define STM32F746_PD5_FUNC_GPIO 0x3500 +#define STM32F746_PD5_FUNC_USART2_TX 0x3508 +#define STM32F746_PD5_FUNC_FMC_NWE 0x350d +#define STM32F746_PD5_FUNC_EVENTOUT 0x3510 +#define STM32F746_PD5_FUNC_ANALOG 0x3511 + +#define STM32F746_PD6_FUNC_GPIO 0x3600 +#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606 +#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607 +#define STM32F746_PD6_FUNC_USART2_RX 0x3608 +#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d +#define STM32F746_PD6_FUNC_DCMI_D10 0x360e +#define STM32F746_PD6_FUNC_LCD_B2 0x360f +#define STM32F746_PD6_FUNC_EVENTOUT 0x3610 +#define STM32F746_PD6_FUNC_ANALOG 0x3611 + +#define STM32F746_PD7_FUNC_GPIO 0x3700 +#define STM32F746_PD7_FUNC_USART2_CK 0x3708 +#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709 +#define STM32F746_PD7_FUNC_FMC_NE1 0x370d +#define STM32F746_PD7_FUNC_EVENTOUT 0x3710 +#define STM32F746_PD7_FUNC_ANALOG 0x3711 + +#define STM32F746_PD8_FUNC_GPIO 0x3800 +#define STM32F746_PD8_FUNC_USART3_TX 0x3808 +#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809 +#define STM32F746_PD8_FUNC_FMC_D13 0x380d +#define STM32F746_PD8_FUNC_EVENTOUT 0x3810 +#define STM32F746_PD8_FUNC_ANALOG 0x3811 + +#define STM32F746_PD9_FUNC_GPIO 0x3900 +#define STM32F746_PD9_FUNC_USART3_RX 0x3908 +#define STM32F746_PD9_FUNC_FMC_D14 0x390d +#define STM32F746_PD9_FUNC_EVENTOUT 0x3910 +#define STM32F746_PD9_FUNC_ANALOG 0x3911 + +#define STM32F746_PD10_FUNC_GPIO 0x3a00 +#define STM32F746_PD10_FUNC_USART3_CK 0x3a08 +#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d +#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f +#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10 +#define STM32F746_PD10_FUNC_ANALOG 0x3a11 + +#define STM32F746_PD11_FUNC_GPIO 0x3b00 +#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05 +#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08 +#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a +#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b +#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d +#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10 +#define STM32F746_PD11_FUNC_ANALOG 0x3b11 + +#define STM32F746_PD12_FUNC_GPIO 0x3c00 +#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03 +#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04 +#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05 +#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08 +#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a +#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b +#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d +#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10 +#define STM32F746_PD12_FUNC_ANALOG 0x3c11 + +#define STM32F746_PD13_FUNC_GPIO 0x3d00 +#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03 +#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04 +#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05 +#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a +#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b +#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d +#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10 +#define STM32F746_PD13_FUNC_ANALOG 0x3d11 + +#define STM32F746_PD14_FUNC_GPIO 0x3e00 +#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03 +#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09 +#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d +#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10 +#define STM32F746_PD14_FUNC_ANALOG 0x3e11 + +#define STM32F746_PD15_FUNC_GPIO 0x3f00 +#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03 +#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09 +#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d +#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10 +#define STM32F746_PD15_FUNC_ANALOG 0x3f11 + + +#define STM32F746_PE0_FUNC_GPIO 0x4000 +#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003 +#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004 +#define STM32F746_PE0_FUNC_UART8_RX 0x4009 +#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b +#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d +#define STM32F746_PE0_FUNC_DCMI_D2 0x400e +#define STM32F746_PE0_FUNC_EVENTOUT 0x4010 +#define STM32F746_PE0_FUNC_ANALOG 0x4011 + +#define STM32F746_PE1_FUNC_GPIO 0x4100 +#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104 +#define STM32F746_PE1_FUNC_UART8_TX 0x4109 +#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d +#define STM32F746_PE1_FUNC_DCMI_D3 0x410e +#define STM32F746_PE1_FUNC_EVENTOUT 0x4110 +#define STM32F746_PE1_FUNC_ANALOG 0x4111 + +#define STM32F746_PE2_FUNC_GPIO 0x4200 +#define STM32F746_PE2_FUNC_TRACECLK 0x4201 +#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206 +#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207 +#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a +#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c +#define STM32F746_PE2_FUNC_FMC_A23 0x420d +#define STM32F746_PE2_FUNC_EVENTOUT 0x4210 +#define STM32F746_PE2_FUNC_ANALOG 0x4211 + +#define STM32F746_PE3_FUNC_GPIO 0x4300 +#define STM32F746_PE3_FUNC_TRACED0 0x4301 +#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307 +#define STM32F746_PE3_FUNC_FMC_A19 0x430d +#define STM32F746_PE3_FUNC_EVENTOUT 0x4310 +#define STM32F746_PE3_FUNC_ANALOG 0x4311 + +#define STM32F746_PE4_FUNC_GPIO 0x4400 +#define STM32F746_PE4_FUNC_TRACED1 0x4401 +#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406 +#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407 +#define STM32F746_PE4_FUNC_FMC_A20 0x440d +#define STM32F746_PE4_FUNC_DCMI_D4 0x440e +#define STM32F746_PE4_FUNC_LCD_B0 0x440f +#define STM32F746_PE4_FUNC_EVENTOUT 0x4410 +#define STM32F746_PE4_FUNC_ANALOG 0x4411 + +#define STM32F746_PE5_FUNC_GPIO 0x4500 +#define STM32F746_PE5_FUNC_TRACED2 0x4501 +#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504 +#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506 +#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507 +#define STM32F746_PE5_FUNC_FMC_A21 0x450d +#define STM32F746_PE5_FUNC_DCMI_D6 0x450e +#define STM32F746_PE5_FUNC_LCD_G0 0x450f +#define STM32F746_PE5_FUNC_EVENTOUT 0x4510 +#define STM32F746_PE5_FUNC_ANALOG 0x4511 + +#define STM32F746_PE6_FUNC_GPIO 0x4600 +#define STM32F746_PE6_FUNC_TRACED3 0x4601 +#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602 +#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604 +#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606 +#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607 +#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b +#define STM32F746_PE6_FUNC_FMC_A22 0x460d +#define STM32F746_PE6_FUNC_DCMI_D7 0x460e +#define STM32F746_PE6_FUNC_LCD_G1 0x460f +#define STM32F746_PE6_FUNC_EVENTOUT 0x4610 +#define STM32F746_PE6_FUNC_ANALOG 0x4611 + +#define STM32F746_PE7_FUNC_GPIO 0x4700 +#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702 +#define STM32F746_PE7_FUNC_UART7_RX 0x4709 +#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b +#define STM32F746_PE7_FUNC_FMC_D4 0x470d +#define STM32F746_PE7_FUNC_EVENTOUT 0x4710 +#define STM32F746_PE7_FUNC_ANALOG 0x4711 + +#define STM32F746_PE8_FUNC_GPIO 0x4800 +#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802 +#define STM32F746_PE8_FUNC_UART7_TX 0x4809 +#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b +#define STM32F746_PE8_FUNC_FMC_D5 0x480d +#define STM32F746_PE8_FUNC_EVENTOUT 0x4810 +#define STM32F746_PE8_FUNC_ANALOG 0x4811 + +#define STM32F746_PE9_FUNC_GPIO 0x4900 +#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902 +#define STM32F746_PE9_FUNC_UART7_RTS 0x4909 +#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b +#define STM32F746_PE9_FUNC_FMC_D6 0x490d +#define STM32F746_PE9_FUNC_EVENTOUT 0x4910 +#define STM32F746_PE9_FUNC_ANALOG 0x4911 + +#define STM32F746_PE10_FUNC_GPIO 0x4a00 +#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02 +#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09 +#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b +#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d +#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10 +#define STM32F746_PE10_FUNC_ANALOG 0x4a11 + +#define STM32F746_PE11_FUNC_GPIO 0x4b00 +#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02 +#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06 +#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b +#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d +#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f +#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10 +#define STM32F746_PE11_FUNC_ANALOG 0x4b11 + +#define STM32F746_PE12_FUNC_GPIO 0x4c00 +#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02 +#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06 +#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b +#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d +#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f +#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10 +#define STM32F746_PE12_FUNC_ANALOG 0x4c11 + +#define STM32F746_PE13_FUNC_GPIO 0x4d00 +#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02 +#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06 +#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b +#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d +#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f +#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10 +#define STM32F746_PE13_FUNC_ANALOG 0x4d11 + +#define STM32F746_PE14_FUNC_GPIO 0x4e00 +#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02 +#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06 +#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b +#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d +#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f +#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10 +#define STM32F746_PE14_FUNC_ANALOG 0x4e11 + +#define STM32F746_PE15_FUNC_GPIO 0x4f00 +#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02 +#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d +#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f +#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10 +#define STM32F746_PE15_FUNC_ANALOG 0x4f11 + + +#define STM32F746_PF0_FUNC_GPIO 0x5000 +#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005 +#define STM32F746_PF0_FUNC_FMC_A0 0x500d +#define STM32F746_PF0_FUNC_EVENTOUT 0x5010 +#define STM32F746_PF0_FUNC_ANALOG 0x5011 + +#define STM32F746_PF1_FUNC_GPIO 0x5100 +#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105 +#define STM32F746_PF1_FUNC_FMC_A1 0x510d +#define STM32F746_PF1_FUNC_EVENTOUT 0x5110 +#define STM32F746_PF1_FUNC_ANALOG 0x5111 + +#define STM32F746_PF2_FUNC_GPIO 0x5200 +#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205 +#define STM32F746_PF2_FUNC_FMC_A2 0x520d +#define STM32F746_PF2_FUNC_EVENTOUT 0x5210 +#define STM32F746_PF2_FUNC_ANALOG 0x5211 + +#define STM32F746_PF3_FUNC_GPIO 0x5300 +#define STM32F746_PF3_FUNC_FMC_A3 0x530d +#define STM32F746_PF3_FUNC_EVENTOUT 0x5310 +#define STM32F746_PF3_FUNC_ANALOG 0x5311 + +#define STM32F746_PF4_FUNC_GPIO 0x5400 +#define STM32F746_PF4_FUNC_FMC_A4 0x540d +#define STM32F746_PF4_FUNC_EVENTOUT 0x5410 +#define STM32F746_PF4_FUNC_ANALOG 0x5411 + +#define STM32F746_PF5_FUNC_GPIO 0x5500 +#define STM32F746_PF5_FUNC_FMC_A5 0x550d +#define STM32F746_PF5_FUNC_EVENTOUT 0x5510 +#define STM32F746_PF5_FUNC_ANALOG 0x5511 + +#define STM32F746_PF6_FUNC_GPIO 0x5600 +#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604 +#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606 +#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607 +#define STM32F746_PF6_FUNC_UART7_RX 0x5609 +#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a +#define STM32F746_PF6_FUNC_EVENTOUT 0x5610 +#define STM32F746_PF6_FUNC_ANALOG 0x5611 + +#define STM32F746_PF7_FUNC_GPIO 0x5700 +#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704 +#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706 +#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707 +#define STM32F746_PF7_FUNC_UART7_TX 0x5709 +#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a +#define STM32F746_PF7_FUNC_EVENTOUT 0x5710 +#define STM32F746_PF7_FUNC_ANALOG 0x5711 + +#define STM32F746_PF8_FUNC_GPIO 0x5800 +#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806 +#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807 +#define STM32F746_PF8_FUNC_UART7_RTS 0x5809 +#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a +#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b +#define STM32F746_PF8_FUNC_EVENTOUT 0x5810 +#define STM32F746_PF8_FUNC_ANALOG 0x5811 + +#define STM32F746_PF9_FUNC_GPIO 0x5900 +#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906 +#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907 +#define STM32F746_PF9_FUNC_UART7_CTS 0x5909 +#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a +#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b +#define STM32F746_PF9_FUNC_EVENTOUT 0x5910 +#define STM32F746_PF9_FUNC_ANALOG 0x5911 + +#define STM32F746_PF10_FUNC_GPIO 0x5a00 +#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e +#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f +#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10 +#define STM32F746_PF10_FUNC_ANALOG 0x5a11 + +#define STM32F746_PF11_FUNC_GPIO 0x5b00 +#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06 +#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b +#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d +#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e +#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10 +#define STM32F746_PF11_FUNC_ANALOG 0x5b11 + +#define STM32F746_PF12_FUNC_GPIO 0x5c00 +#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d +#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10 +#define STM32F746_PF12_FUNC_ANALOG 0x5c11 + +#define STM32F746_PF13_FUNC_GPIO 0x5d00 +#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05 +#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d +#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10 +#define STM32F746_PF13_FUNC_ANALOG 0x5d11 + +#define STM32F746_PF14_FUNC_GPIO 0x5e00 +#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05 +#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d +#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10 +#define STM32F746_PF14_FUNC_ANALOG 0x5e11 + +#define STM32F746_PF15_FUNC_GPIO 0x5f00 +#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05 +#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d +#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10 +#define STM32F746_PF15_FUNC_ANALOG 0x5f11 + + +#define STM32F746_PG0_FUNC_GPIO 0x6000 +#define STM32F746_PG0_FUNC_FMC_A10 0x600d +#define STM32F746_PG0_FUNC_EVENTOUT 0x6010 +#define STM32F746_PG0_FUNC_ANALOG 0x6011 + +#define STM32F746_PG1_FUNC_GPIO 0x6100 +#define STM32F746_PG1_FUNC_FMC_A11 0x610d +#define STM32F746_PG1_FUNC_EVENTOUT 0x6110 +#define STM32F746_PG1_FUNC_ANALOG 0x6111 + +#define STM32F746_PG2_FUNC_GPIO 0x6200 +#define STM32F746_PG2_FUNC_FMC_A12 0x620d +#define STM32F746_PG2_FUNC_EVENTOUT 0x6210 +#define STM32F746_PG2_FUNC_ANALOG 0x6211 + +#define STM32F746_PG3_FUNC_GPIO 0x6300 +#define STM32F746_PG3_FUNC_FMC_A13 0x630d +#define STM32F746_PG3_FUNC_EVENTOUT 0x6310 +#define STM32F746_PG3_FUNC_ANALOG 0x6311 + +#define STM32F746_PG4_FUNC_GPIO 0x6400 +#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d +#define STM32F746_PG4_FUNC_EVENTOUT 0x6410 +#define STM32F746_PG4_FUNC_ANALOG 0x6411 + +#define STM32F746_PG5_FUNC_GPIO 0x6500 +#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d +#define STM32F746_PG5_FUNC_EVENTOUT 0x6510 +#define STM32F746_PG5_FUNC_ANALOG 0x6511 + +#define STM32F746_PG6_FUNC_GPIO 0x6600 +#define STM32F746_PG6_FUNC_DCMI_D12 0x660e +#define STM32F746_PG6_FUNC_LCD_R7 0x660f +#define STM32F746_PG6_FUNC_EVENTOUT 0x6610 +#define STM32F746_PG6_FUNC_ANALOG 0x6611 + +#define STM32F746_PG7_FUNC_GPIO 0x6700 +#define STM32F746_PG7_FUNC_USART6_CK 0x6709 +#define STM32F746_PG7_FUNC_FMC_INT 0x670d +#define STM32F746_PG7_FUNC_DCMI_D13 0x670e +#define STM32F746_PG7_FUNC_LCD_CLK 0x670f +#define STM32F746_PG7_FUNC_EVENTOUT 0x6710 +#define STM32F746_PG7_FUNC_ANALOG 0x6711 + +#define STM32F746_PG8_FUNC_GPIO 0x6800 +#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806 +#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808 +#define STM32F746_PG8_FUNC_USART6_RTS 0x6809 +#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c +#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d +#define STM32F746_PG8_FUNC_EVENTOUT 0x6810 +#define STM32F746_PG8_FUNC_ANALOG 0x6811 + +#define STM32F746_PG9_FUNC_GPIO 0x6900 +#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908 +#define STM32F746_PG9_FUNC_USART6_RX 0x6909 +#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a +#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b +#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d +#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e +#define STM32F746_PG9_FUNC_EVENTOUT 0x6910 +#define STM32F746_PG9_FUNC_ANALOG 0x6911 + +#define STM32F746_PG10_FUNC_GPIO 0x6a00 +#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a +#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b +#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d +#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e +#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f +#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10 +#define STM32F746_PG10_FUNC_ANALOG 0x6a11 + +#define STM32F746_PG11_FUNC_GPIO 0x6b00 +#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08 +#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c +#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e +#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f +#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10 +#define STM32F746_PG11_FUNC_ANALOG 0x6b11 + +#define STM32F746_PG12_FUNC_GPIO 0x6c00 +#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04 +#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06 +#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08 +#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09 +#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a +#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d +#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f +#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10 +#define STM32F746_PG12_FUNC_ANALOG 0x6c11 + +#define STM32F746_PG13_FUNC_GPIO 0x6d00 +#define STM32F746_PG13_FUNC_TRACED0 0x6d01 +#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04 +#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06 +#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09 +#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c +#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d +#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f +#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10 +#define STM32F746_PG13_FUNC_ANALOG 0x6d11 + +#define STM32F746_PG14_FUNC_GPIO 0x6e00 +#define STM32F746_PG14_FUNC_TRACED1 0x6e01 +#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04 +#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06 +#define STM32F746_PG14_FUNC_USART6_TX 0x6e09 +#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a +#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c +#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d +#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f +#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10 +#define STM32F746_PG14_FUNC_ANALOG 0x6e11 + +#define STM32F746_PG15_FUNC_GPIO 0x6f00 +#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09 +#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d +#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e +#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10 +#define STM32F746_PG15_FUNC_ANALOG 0x6f11 + + +#define STM32F746_PH0_FUNC_GPIO 0x7000 +#define STM32F746_PH0_FUNC_EVENTOUT 0x7010 +#define STM32F746_PH0_FUNC_ANALOG 0x7011 + +#define STM32F746_PH1_FUNC_GPIO 0x7100 +#define STM32F746_PH1_FUNC_EVENTOUT 0x7110 +#define STM32F746_PH1_FUNC_ANALOG 0x7111 + +#define STM32F746_PH2_FUNC_GPIO 0x7200 +#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204 +#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a +#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b +#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c +#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d +#define STM32F746_PH2_FUNC_LCD_R0 0x720f +#define STM32F746_PH2_FUNC_EVENTOUT 0x7210 +#define STM32F746_PH2_FUNC_ANALOG 0x7211 + +#define STM32F746_PH3_FUNC_GPIO 0x7300 +#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a +#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b +#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c +#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d +#define STM32F746_PH3_FUNC_LCD_R1 0x730f +#define STM32F746_PH3_FUNC_EVENTOUT 0x7310 +#define STM32F746_PH3_FUNC_ANALOG 0x7311 + +#define STM32F746_PH4_FUNC_GPIO 0x7400 +#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405 +#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b +#define STM32F746_PH4_FUNC_EVENTOUT 0x7410 +#define STM32F746_PH4_FUNC_ANALOG 0x7411 + +#define STM32F746_PH5_FUNC_GPIO 0x7500 +#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505 +#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506 +#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d +#define STM32F746_PH5_FUNC_EVENTOUT 0x7510 +#define STM32F746_PH5_FUNC_ANALOG 0x7511 + +#define STM32F746_PH6_FUNC_GPIO 0x7600 +#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605 +#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606 +#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a +#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c +#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d +#define STM32F746_PH6_FUNC_DCMI_D8 0x760e +#define STM32F746_PH6_FUNC_EVENTOUT 0x7610 +#define STM32F746_PH6_FUNC_ANALOG 0x7611 + +#define STM32F746_PH7_FUNC_GPIO 0x7700 +#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705 +#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706 +#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c +#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d +#define STM32F746_PH7_FUNC_DCMI_D9 0x770e +#define STM32F746_PH7_FUNC_EVENTOUT 0x7710 +#define STM32F746_PH7_FUNC_ANALOG 0x7711 + +#define STM32F746_PH8_FUNC_GPIO 0x7800 +#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805 +#define STM32F746_PH8_FUNC_FMC_D16 0x780d +#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e +#define STM32F746_PH8_FUNC_LCD_R2 0x780f +#define STM32F746_PH8_FUNC_EVENTOUT 0x7810 +#define STM32F746_PH8_FUNC_ANALOG 0x7811 + +#define STM32F746_PH9_FUNC_GPIO 0x7900 +#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905 +#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a +#define STM32F746_PH9_FUNC_FMC_D17 0x790d +#define STM32F746_PH9_FUNC_DCMI_D0 0x790e +#define STM32F746_PH9_FUNC_LCD_R3 0x790f +#define STM32F746_PH9_FUNC_EVENTOUT 0x7910 +#define STM32F746_PH9_FUNC_ANALOG 0x7911 + +#define STM32F746_PH10_FUNC_GPIO 0x7a00 +#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03 +#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05 +#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d +#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e +#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f +#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10 +#define STM32F746_PH10_FUNC_ANALOG 0x7a11 + +#define STM32F746_PH11_FUNC_GPIO 0x7b00 +#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03 +#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05 +#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d +#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e +#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f +#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10 +#define STM32F746_PH11_FUNC_ANALOG 0x7b11 + +#define STM32F746_PH12_FUNC_GPIO 0x7c00 +#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03 +#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05 +#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d +#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e +#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f +#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10 +#define STM32F746_PH12_FUNC_ANALOG 0x7c11 + +#define STM32F746_PH13_FUNC_GPIO 0x7d00 +#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04 +#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a +#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d +#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f +#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10 +#define STM32F746_PH13_FUNC_ANALOG 0x7d11 + +#define STM32F746_PH14_FUNC_GPIO 0x7e00 +#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04 +#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d +#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e +#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f +#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10 +#define STM32F746_PH14_FUNC_ANALOG 0x7e11 + +#define STM32F746_PH15_FUNC_GPIO 0x7f00 +#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04 +#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d +#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e +#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f +#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10 +#define STM32F746_PH15_FUNC_ANALOG 0x7f11 + + +#define STM32F746_PI0_FUNC_GPIO 0x8000 +#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003 +#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006 +#define STM32F746_PI0_FUNC_FMC_D24 0x800d +#define STM32F746_PI0_FUNC_DCMI_D13 0x800e +#define STM32F746_PI0_FUNC_LCD_G5 0x800f +#define STM32F746_PI0_FUNC_EVENTOUT 0x8010 +#define STM32F746_PI0_FUNC_ANALOG 0x8011 + +#define STM32F746_PI1_FUNC_GPIO 0x8100 +#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104 +#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106 +#define STM32F746_PI1_FUNC_FMC_D25 0x810d +#define STM32F746_PI1_FUNC_DCMI_D8 0x810e +#define STM32F746_PI1_FUNC_LCD_G6 0x810f +#define STM32F746_PI1_FUNC_EVENTOUT 0x8110 +#define STM32F746_PI1_FUNC_ANALOG 0x8111 + +#define STM32F746_PI2_FUNC_GPIO 0x8200 +#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204 +#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206 +#define STM32F746_PI2_FUNC_FMC_D26 0x820d +#define STM32F746_PI2_FUNC_DCMI_D9 0x820e +#define STM32F746_PI2_FUNC_LCD_G7 0x820f +#define STM32F746_PI2_FUNC_EVENTOUT 0x8210 +#define STM32F746_PI2_FUNC_ANALOG 0x8211 + +#define STM32F746_PI3_FUNC_GPIO 0x8300 +#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304 +#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306 +#define STM32F746_PI3_FUNC_FMC_D27 0x830d +#define STM32F746_PI3_FUNC_DCMI_D10 0x830e +#define STM32F746_PI3_FUNC_EVENTOUT 0x8310 +#define STM32F746_PI3_FUNC_ANALOG 0x8311 + +#define STM32F746_PI4_FUNC_GPIO 0x8400 +#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404 +#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b +#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d +#define STM32F746_PI4_FUNC_DCMI_D5 0x840e +#define STM32F746_PI4_FUNC_LCD_B4 0x840f +#define STM32F746_PI4_FUNC_EVENTOUT 0x8410 +#define STM32F746_PI4_FUNC_ANALOG 0x8411 + +#define STM32F746_PI5_FUNC_GPIO 0x8500 +#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504 +#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b +#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d +#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e +#define STM32F746_PI5_FUNC_LCD_B5 0x850f +#define STM32F746_PI5_FUNC_EVENTOUT 0x8510 +#define STM32F746_PI5_FUNC_ANALOG 0x8511 + +#define STM32F746_PI6_FUNC_GPIO 0x8600 +#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604 +#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b +#define STM32F746_PI6_FUNC_FMC_D28 0x860d +#define STM32F746_PI6_FUNC_DCMI_D6 0x860e +#define STM32F746_PI6_FUNC_LCD_B6 0x860f +#define STM32F746_PI6_FUNC_EVENTOUT 0x8610 +#define STM32F746_PI6_FUNC_ANALOG 0x8611 + +#define STM32F746_PI7_FUNC_GPIO 0x8700 +#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704 +#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b +#define STM32F746_PI7_FUNC_FMC_D29 0x870d +#define STM32F746_PI7_FUNC_DCMI_D7 0x870e +#define STM32F746_PI7_FUNC_LCD_B7 0x870f +#define STM32F746_PI7_FUNC_EVENTOUT 0x8710 +#define STM32F746_PI7_FUNC_ANALOG 0x8711 + +#define STM32F746_PI8_FUNC_GPIO 0x8800 +#define STM32F746_PI8_FUNC_EVENTOUT 0x8810 +#define STM32F746_PI8_FUNC_ANALOG 0x8811 + +#define STM32F746_PI9_FUNC_GPIO 0x8900 +#define STM32F746_PI9_FUNC_CAN1_RX 0x890a +#define STM32F746_PI9_FUNC_FMC_D30 0x890d +#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f +#define STM32F746_PI9_FUNC_EVENTOUT 0x8910 +#define STM32F746_PI9_FUNC_ANALOG 0x8911 + +#define STM32F746_PI10_FUNC_GPIO 0x8a00 +#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c +#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d +#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f +#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10 +#define STM32F746_PI10_FUNC_ANALOG 0x8a11 + +#define STM32F746_PI11_FUNC_GPIO 0x8b00 +#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b +#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10 +#define STM32F746_PI11_FUNC_ANALOG 0x8b11 + +#define STM32F746_PI12_FUNC_GPIO 0x8c00 +#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f +#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10 +#define STM32F746_PI12_FUNC_ANALOG 0x8c11 + +#define STM32F746_PI13_FUNC_GPIO 0x8d00 +#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f +#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10 +#define STM32F746_PI13_FUNC_ANALOG 0x8d11 + +#define STM32F746_PI14_FUNC_GPIO 0x8e00 +#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f +#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10 +#define STM32F746_PI14_FUNC_ANALOG 0x8e11 + +#define STM32F746_PI15_FUNC_GPIO 0x8f00 +#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f +#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10 +#define STM32F746_PI15_FUNC_ANALOG 0x8f11 + + +#define STM32F746_PJ0_FUNC_GPIO 0x9000 +#define STM32F746_PJ0_FUNC_LCD_R1 0x900f +#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010 +#define STM32F746_PJ0_FUNC_ANALOG 0x9011 + +#define STM32F746_PJ1_FUNC_GPIO 0x9100 +#define STM32F746_PJ1_FUNC_LCD_R2 0x910f +#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110 +#define STM32F746_PJ1_FUNC_ANALOG 0x9111 + +#define STM32F746_PJ2_FUNC_GPIO 0x9200 +#define STM32F746_PJ2_FUNC_LCD_R3 0x920f +#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210 +#define STM32F746_PJ2_FUNC_ANALOG 0x9211 + +#define STM32F746_PJ3_FUNC_GPIO 0x9300 +#define STM32F746_PJ3_FUNC_LCD_R4 0x930f +#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310 +#define STM32F746_PJ3_FUNC_ANALOG 0x9311 + +#define STM32F746_PJ4_FUNC_GPIO 0x9400 +#define STM32F746_PJ4_FUNC_LCD_R5 0x940f +#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410 +#define STM32F746_PJ4_FUNC_ANALOG 0x9411 + +#define STM32F746_PJ5_FUNC_GPIO 0x9500 +#define STM32F746_PJ5_FUNC_LCD_R6 0x950f +#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510 +#define STM32F746_PJ5_FUNC_ANALOG 0x9511 + +#define STM32F746_PJ6_FUNC_GPIO 0x9600 +#define STM32F746_PJ6_FUNC_LCD_R7 0x960f +#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610 +#define STM32F746_PJ6_FUNC_ANALOG 0x9611 + +#define STM32F746_PJ7_FUNC_GPIO 0x9700 +#define STM32F746_PJ7_FUNC_LCD_G0 0x970f +#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710 +#define STM32F746_PJ7_FUNC_ANALOG 0x9711 + +#define STM32F746_PJ8_FUNC_GPIO 0x9800 +#define STM32F746_PJ8_FUNC_LCD_G1 0x980f +#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810 +#define STM32F746_PJ8_FUNC_ANALOG 0x9811 + +#define STM32F746_PJ9_FUNC_GPIO 0x9900 +#define STM32F746_PJ9_FUNC_LCD_G2 0x990f +#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910 +#define STM32F746_PJ9_FUNC_ANALOG 0x9911 + +#define STM32F746_PJ10_FUNC_GPIO 0x9a00 +#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f +#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10 +#define STM32F746_PJ10_FUNC_ANALOG 0x9a11 + +#define STM32F746_PJ11_FUNC_GPIO 0x9b00 +#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f +#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10 +#define STM32F746_PJ11_FUNC_ANALOG 0x9b11 + +#define STM32F746_PJ12_FUNC_GPIO 0x9c00 +#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f +#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10 +#define STM32F746_PJ12_FUNC_ANALOG 0x9c11 + +#define STM32F746_PJ13_FUNC_GPIO 0x9d00 +#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f +#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10 +#define STM32F746_PJ13_FUNC_ANALOG 0x9d11 + +#define STM32F746_PJ14_FUNC_GPIO 0x9e00 +#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f +#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10 +#define STM32F746_PJ14_FUNC_ANALOG 0x9e11 + +#define STM32F746_PJ15_FUNC_GPIO 0x9f00 +#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f +#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10 +#define STM32F746_PJ15_FUNC_ANALOG 0x9f11 + + +#define STM32F746_PK0_FUNC_GPIO 0xa000 +#define STM32F746_PK0_FUNC_LCD_G5 0xa00f +#define STM32F746_PK0_FUNC_EVENTOUT 0xa010 +#define STM32F746_PK0_FUNC_ANALOG 0xa011 + +#define STM32F746_PK1_FUNC_GPIO 0xa100 +#define STM32F746_PK1_FUNC_LCD_G6 0xa10f +#define STM32F746_PK1_FUNC_EVENTOUT 0xa110 +#define STM32F746_PK1_FUNC_ANALOG 0xa111 + +#define STM32F746_PK2_FUNC_GPIO 0xa200 +#define STM32F746_PK2_FUNC_LCD_G7 0xa20f +#define STM32F746_PK2_FUNC_EVENTOUT 0xa210 +#define STM32F746_PK2_FUNC_ANALOG 0xa211 + +#define STM32F746_PK3_FUNC_GPIO 0xa300 +#define STM32F746_PK3_FUNC_LCD_B4 0xa30f +#define STM32F746_PK3_FUNC_EVENTOUT 0xa310 +#define STM32F746_PK3_FUNC_ANALOG 0xa311 + +#define STM32F746_PK4_FUNC_GPIO 0xa400 +#define STM32F746_PK4_FUNC_LCD_B5 0xa40f +#define STM32F746_PK4_FUNC_EVENTOUT 0xa410 +#define STM32F746_PK4_FUNC_ANALOG 0xa411 + +#define STM32F746_PK5_FUNC_GPIO 0xa500 +#define STM32F746_PK5_FUNC_LCD_B6 0xa50f +#define STM32F746_PK5_FUNC_EVENTOUT 0xa510 +#define STM32F746_PK5_FUNC_ANALOG 0xa511 + +#define STM32F746_PK6_FUNC_GPIO 0xa600 +#define STM32F746_PK6_FUNC_LCD_B7 0xa60f +#define STM32F746_PK6_FUNC_EVENTOUT 0xa610 +#define STM32F746_PK6_FUNC_ANALOG 0xa611 + +#define STM32F746_PK7_FUNC_GPIO 0xa700 +#define STM32F746_PK7_FUNC_LCD_DE 0xa70f +#define STM32F746_PK7_FUNC_EVENTOUT 0xa710 +#define STM32F746_PK7_FUNC_ANALOG 0xa711 + +#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */

Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - prefix all constants with STM32_ - remove double constants

Signed-off-by: Michael Kurz michi.kurz@gmail.com

---

Changes in v2: - add cleanup patch

arch/arm/include/asm/arch-stm32f4/stm32.h | 2 +- arch/arm/include/asm/arch-stm32f7/fmc.h | 7 +- arch/arm/include/asm/arch-stm32f7/gpt.h | 9 +- arch/arm/include/asm/arch-stm32f7/rcc.h | 64 ------- arch/arm/include/asm/arch-stm32f7/stm32.h | 119 +++++------- arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 3 + arch/arm/mach-stm32/stm32f7/clock.c | 227 ++++++++++++++--------- arch/arm/mach-stm32/stm32f7/timer.c | 4 +- board/st/stm32f746-disco/stm32f746-disco.c | 10 +- drivers/mtd/stm32_flash.c | 2 +- drivers/serial/serial_stm32x7.c | 4 +- 11 files changed, 203 insertions(+), 248 deletions(-) delete mode 100644 arch/arm/include/asm/arch-stm32f7/rcc.h

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6cc1966..b77345a 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -102,7 +102,7 @@ struct stm32_pwr_regs { #define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) #define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)

-#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) +#define STM32_FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)

static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [0 ... 3] = 16 * 1024, diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h index 7dd5077..24e6f1e 100644 --- a/arch/arm/include/asm/arch-stm32f7/fmc.h +++ b/arch/arm/include/asm/arch-stm32f7/fmc.h @@ -24,7 +24,6 @@ struct stm32_fmc_regs { /* * FMC registers base */ -#define STM32_SDRAM_FMC_BASE 0xA0000140 #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)

/* Control register SDCR */ @@ -58,12 +57,12 @@ struct stm32_fmc_regs { #define FMC_SDCMR_MODE_SELFREFRESH 5 #define FMC_SDCMR_MODE_POWERDOWN 6

-#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3)

#define FMC_SDCMR_MODE_REGISTER_SHIFT 9

-#define FMC_SDSR_BUSY (1 << 5) +#define FMC_SDSR_BUSY BIT(5)

#define FMC_BUSY_WAIT() do { \ __asm__ __volatile__ ("dsb" : : : "memory"); \ diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h index 903bdf6..7591519 100644 --- a/arch/arm/include/asm/arch-stm32f7/gpt.h +++ b/arch/arm/include/asm/arch-stm32f7/gpt.h @@ -34,12 +34,11 @@ struct gpt_regs { u32 tim2_5_or; };

-struct gpt_regs *const gpt1_regs_ptr = - (struct gpt_regs *)TIM2_BASE; +struct gpt_regs *const gpt1_regs_ptr = (struct gpt_regs *)STM32_TIM2_BASE;

/* Timer control1 register */ -#define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) +#define GPT_CR1_CEN BIT(0) +#define GPT_MODE_AUTO_RELOAD BIT(7)

/* Auto reload register for free running config */ #define GPT_FREE_RUNNING 0xFFFFFFFF @@ -48,6 +47,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define CONFIG_STM32_HZ 1000

/* Timer Event Generation registers */ -#define TIM_EGR_UG (1 << 0) +#define TIM_EGR_UG BIT(0)

#endif diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h deleted file mode 100644 index 8bfb7b6..0000000 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2016 - * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_RCC_H -#define _STM32_RCC_H - -#define RCC_CR 0x00 /* clock control */ -#define RCC_PLLCFGR 0x04 /* PLL configuration */ -#define RCC_CFGR 0x08 /* clock configuration */ -#define RCC_CIR 0x0C /* clock interrupt */ -#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */ -#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */ -#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */ -#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */ -#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */ -#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */ -#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */ -#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */ -#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */ -#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */ -#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */ -#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */ -#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */ -#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */ -#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */ -#define RCC_BDCR 0x70 /* Backup domain control */ -#define RCC_CSR 0x74 /* clock control & status */ -#define RCC_SSCGR 0x80 /* spread spectrum clock generation */ -#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */ -#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ -#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ -#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ - -#define RCC_APB1ENR_TIM2EN (1 << 0) -#define RCC_APB1ENR_PWREN (1 << 28) - -/* - * RCC USART specific definitions - */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) - -/* - * RCC GPIO specific definitions - */ -#define RCC_ENR_GPIO_A_EN (1 << 0) -#define RCC_ENR_GPIO_B_EN (1 << 1) -#define RCC_ENR_GPIO_C_EN (1 << 2) -#define RCC_ENR_GPIO_D_EN (1 << 3) -#define RCC_ENR_GPIO_E_EN (1 << 4) -#define RCC_ENR_GPIO_F_EN (1 << 5) -#define RCC_ENR_GPIO_G_EN (1 << 6) -#define RCC_ENR_GPIO_H_EN (1 << 7) -#define RCC_ENR_GPIO_I_EN (1 << 8) -#define RCC_ENR_GPIO_J_EN (1 << 9) -#define RCC_ENR_GPIO_K_EN (1 << 10) - -#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index de55ae5..efc4fd7 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -9,46 +9,47 @@ #define _ASM_ARCH_HARDWARE_H

/* STM32F746 */ -#define ITCM_FLASH_BASE 0x00200000UL -#define AXIM_FLASH_BASE 0x08000000UL +#define STM32_ITCM_FLASH_BASE 0x00200000UL +#define STM32_AXIM_FLASH_BASE 0x08000000UL + +#define STM32_ITCM_SRAM_BASE 0x00000000UL +#define STM32_DTCM_SRAM_BASE 0x20000000UL +#define STM32_SRAM1_BASE 0x20010000UL +#define STM32_SRAM2_BASE 0x2004C000UL + +#define STM32_PERIPH_BASE 0x40000000UL + +#define STM32_APB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) +#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) +#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) +#define STM32_AHB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) +#define STM32_AHB3_PERIPH_BASE (STM32_PERIPH_BASE + 0x20000000) + +#define STM32_TIM2_BASE (STM32_APB1_PERIPH_BASE + 0x0000) +#define STM32_USART2_BASE (STM32_APB1_PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1_PERIPH_BASE + 0x4800) +#define STM32_PWR_BASE (STM32_APB1_PERIPH_BASE + 0x7000) + +#define STM32_USART1_BASE (STM32_APB2_PERIPH_BASE + 0x1000) +#define STM32_USART6_BASE (STM32_APB2_PERIPH_BASE + 0x1400) +#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800) + +#define STM32_GPIOA_BASE (STM32_AHB1_PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (STM32_AHB1_PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (STM32_AHB1_PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (STM32_AHB1_PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (STM32_AHB1_PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (STM32_AHB1_PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (STM32_AHB1_PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (STM32_AHB1_PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (STM32_AHB1_PERIPH_BASE + 0x2000) +#define STM32_GPIOJ_BASE (STM32_AHB1_PERIPH_BASE + 0x2400) +#define STM32_GPIOK_BASE (STM32_AHB1_PERIPH_BASE + 0x2800) +#define STM32_RCC_BASE (STM32_AHB1_PERIPH_BASE + 0x3800) +#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00) + +#define STM32_SDRAM_FMC_BASE (STM32_AHB3_PERIPH_BASE + 0x40000140)

-#define ITCM_SRAM_BASE 0x00000000UL -#define DTCM_SRAM_BASE 0x20000000UL -#define SRAM1_BASE 0x20010000UL -#define SRAM2_BASE 0x2004C000UL - -#define PERIPH_BASE 0x40000000UL - -#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) - -#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) -#define USART2_BASE (APB1_PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1_PERIPH_BASE + 0x4800) -#define PWR_BASE (APB1_PERIPH_BASE + 0x7000) - -#define USART1_BASE (APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2_PERIPH_BASE + 0x1400) - -#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) -#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) -#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) -#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) -#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) -#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) -#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) -#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) -#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) -#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) -#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) -#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) -#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) - - -#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140)

static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [0 ... 3] = 32 * 1024, @@ -62,43 +63,7 @@ enum clock { CLOCK_APB1, CLOCK_APB2 }; -#define STM32_BUS_MASK 0xFFFF0000 - -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 pllcfgr; /* RCC PLL configuration */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 ahb1rstr; /* RCC AHB1 peripheral reset */ - u32 ahb2rstr; /* RCC AHB2 peripheral reset */ - u32 ahb3rstr; /* RCC AHB3 peripheral reset */ - u32 rsv0; - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 rsv1[2]; - u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ - u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ - u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ - u32 rsv2; - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 rsv3[2]; - u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ - u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ - u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ - u32 rsv4; - u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ - u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ - u32 rsv5[2]; - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ - u32 rsv6[2]; - u32 sscgr; /* RCC spread spectrum clock generation */ - u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; - u32 dckcfgr; -}; -#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) +#define STM32_BUS_MASK GENMASK(31, 16)

struct stm32_pwr_regs { u32 cr1; /* power control register 1 */ @@ -106,7 +71,7 @@ struct stm32_pwr_regs { u32 cr2; /* power control register 2 */ u32 csr2; /* power control/status register 2 */ }; -#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) +#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)

int configure_clocks(void); unsigned long clock_get(enum clock clck); diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 38adc4e..9b315a8 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -33,6 +33,9 @@ enum periph_clock { GPIO_I_CLOCK_CFG, GPIO_J_CLOCK_CFG, GPIO_K_CLOCK_CFG, + SYSCFG_CLOCK_CFG, + TIMER2_CLOCK_CFG, + FMC_CLOCK_CFG, };

#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c index 78d22d4..839d928 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -7,80 +7,130 @@

#include <common.h> #include <asm/io.h> -#include <asm/arch/rcc.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h>

-#define RCC_CR_HSION (1 << 0) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_PLLRDY (1 << 25) +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + u32 pllsaicfgr; /* PLLSAI configuration */ + u32 dckcfgr1; /* dedicated clocks configuration register 1 */ + u32 dckcfgr2; /* dedicated clocks configuration register 2 */ +}; +#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)

-#define RCC_PLLCFGR_PLLM_MASK 0x3F -#define RCC_PLLCFGR_PLLN_MASK 0x7FC0 -#define RCC_PLLCFGR_PLLP_MASK 0x30000 -#define RCC_PLLCFGR_PLLQ_MASK 0xF000000 -#define RCC_PLLCFGR_PLLSRC (1 << 22) -#define RCC_PLLCFGR_PLLM_SHIFT 0 -#define RCC_PLLCFGR_PLLN_SHIFT 6 -#define RCC_PLLCFGR_PLLP_SHIFT 16 -#define RCC_PLLCFGR_PLLQ_SHIFT 24

-#define RCC_CFGR_AHB_PSC_MASK 0xF0 -#define RCC_CFGR_APB1_PSC_MASK 0x1C00 -#define RCC_CFGR_APB2_PSC_MASK 0xE000 -#define RCC_CFGR_SW0 (1 << 0) -#define RCC_CFGR_SW1 (1 << 1) -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_HSI 0 -#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 -#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 -#define RCC_CFGR_SWS0 (1 << 2) -#define RCC_CFGR_SWS1 (1 << 3) -#define RCC_CFGR_SWS_MASK 0xC -#define RCC_CFGR_SWS_HSI 0 -#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 -#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_PPRE1_SHIFT 10 -#define RCC_CFGR_PPRE2_SHIFT 13 +/* + * RCC AHB1ENR specific definitions + */ +#define RCC_AHB1ENR_GPIO_A_EN BIT(0) +#define RCC_AHB1ENR_GPIO_B_EN BIT(1) +#define RCC_AHB1ENR_GPIO_C_EN BIT(2) +#define RCC_AHB1ENR_GPIO_D_EN BIT(3) +#define RCC_AHB1ENR_GPIO_E_EN BIT(4) +#define RCC_AHB1ENR_GPIO_F_EN BIT(5) +#define RCC_AHB1ENR_GPIO_G_EN BIT(6) +#define RCC_AHB1ENR_GPIO_H_EN BIT(7) +#define RCC_AHB1ENR_GPIO_I_EN BIT(8) +#define RCC_AHB1ENR_GPIO_J_EN BIT(9) +#define RCC_AHB1ENR_GPIO_K_EN BIT(10) +#define RCC_AHB1ENR_ETHMAC_EN BIT(25) +#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) +#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) +#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)

-#define RCC_APB1ENR_PWREN (1 << 28) +/* + * RCC AHB3ENR specific definitions + */ +#define RCC_AHB3ENR_FMC_EN BIT(0)

/* - * RCC USART specific definitions + * RCC APB1ENR specific definitions */ -#define RCC_ENR_USART1EN (1 << 4) -#define RCC_ENR_USART2EN (1 << 17) -#define RCC_ENR_USART3EN (1 << 18) -#define RCC_ENR_USART6EN (1 << 5) +#define RCC_APB1ENR_TIM2EN BIT(0) +#define RCC_APB1ENR_USART2EN BIT(17) +#define RCC_APB1ENR_USART3EN BIT(18) +#define RCC_APB1ENR_PWREN BIT(28)

/* - * Offsets of some PWR registers + * RCC APB2ENR specific definitions */ -#define PWR_CR1_ODEN (1 << 16) -#define PWR_CR1_ODSWEN (1 << 17) -#define PWR_CSR1_ODRDY (1 << 16) -#define PWR_CSR1_ODSWRDY (1 << 17) +#define RCC_APB2ENR_USART1EN BIT(4) +#define RCC_APB2ENR_USART6EN BIT(5) +#define RCC_APB2ENR_SYSCFGEN BIT(14)

+#define RCC_CR_HSION BIT(0) +#define RCC_CR_HSEON BIT(16) +#define RCC_CR_HSERDY BIT(17) +#define RCC_CR_HSEBYP BIT(18) +#define RCC_CR_CSSON BIT(19) +#define RCC_CR_PLLON BIT(24) +#define RCC_CR_PLLRDY BIT(25) + +#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) +#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) +#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) +#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) +#define RCC_PLLCFGR_PLLSRC BIT(22) +#define RCC_PLLCFGR_PLLM_SHIFT 0 +#define RCC_PLLCFGR_PLLN_SHIFT 6 +#define RCC_PLLCFGR_PLLP_SHIFT 16 +#define RCC_PLLCFGR_PLLQ_SHIFT 24 + +#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) +#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) +#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) +#define RCC_CFGR_SW0 BIT(0) +#define RCC_CFGR_SW1 BIT(1) +#define RCC_CFGR_SW_MASK GENMASK(1, 0) +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 +#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 +#define RCC_CFGR_SWS0 BIT(2) +#define RCC_CFGR_SWS1 BIT(3) +#define RCC_CFGR_SWS_MASK GENMASK(3, 2) +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 +#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE2_SHIFT 13

/* - * RCC GPIO specific definitions + * Offsets of some PWR registers */ -#define RCC_ENR_GPIO_A_EN (1 << 0) -#define RCC_ENR_GPIO_B_EN (1 << 1) -#define RCC_ENR_GPIO_C_EN (1 << 2) -#define RCC_ENR_GPIO_D_EN (1 << 3) -#define RCC_ENR_GPIO_E_EN (1 << 4) -#define RCC_ENR_GPIO_F_EN (1 << 5) -#define RCC_ENR_GPIO_G_EN (1 << 6) -#define RCC_ENR_GPIO_H_EN (1 << 7) -#define RCC_ENR_GPIO_I_EN (1 << 8) -#define RCC_ENR_GPIO_J_EN (1 << 9) -#define RCC_ENR_GPIO_K_EN (1 << 10) +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17)

struct pll_psc { u8 pll_m; @@ -92,21 +142,21 @@ struct pll_psc { u8 apb2_psc; };

-#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF

-#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7

#if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" @@ -243,40 +293,49 @@ void clock_setup(int peripheral) { switch (peripheral) { case USART1_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN); + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN); break; case GPIO_A_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN); break; case GPIO_B_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN); break; case GPIO_C_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN); break; case GPIO_D_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN); break; case GPIO_E_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN); break; case GPIO_F_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN); break; case GPIO_G_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN); break; case GPIO_H_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN); break; case GPIO_I_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN); break; case GPIO_J_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN); break; case GPIO_K_CLOCK_CFG: - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN); + break; + case SYSCFG_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); + break; + case TIMER2_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); + break; + case FMC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); break; default: break; diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c index a7dee10..c15f8bb 100644 --- a/arch/arm/mach-stm32/stm32f7/timer.c +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -8,8 +8,8 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/stm32_defs.h> #include <asm/arch/gpt.h> -#include <asm/arch/rcc.h>

#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) #define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ) @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { /* Timer2 clock configuration */ - setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN); + clock_setup(TIMER2_CLOCK_CFG); /* Stop the timer */ writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 404fdfa..db5510e 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -10,7 +10,6 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/rcc.h> #include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> @@ -114,11 +113,6 @@ out: return rv; }

-/* - * STM32 RCC FMC specific definitions - */ -#define RCC_ENR_FMC (1 << 0) /* FMC module clock */ - static inline u32 _ns2clk(u32 ns, u32 freq) { u32 tmp = freq/1000000; @@ -176,7 +170,7 @@ int dram_init(void) if (rv) return rv;

- setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC); + clock_setup(FMC_CLOCK_CFG);

/* * Get frequency for NS2CLK calculation. @@ -273,7 +267,7 @@ out: }

static const struct stm32x7_serial_platdata serial_platdata = { - .base = (struct stm32_usart *)USART1_BASE, + .base = (struct stm32_usart *)STM32_USART1_BASE, .clock = CONFIG_SYS_CLK_FREQ, };

diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index e16b6cd..9e42c23 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -12,7 +12,7 @@

flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];

-#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE) +#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE)

void stm32_flash_latency_cfg(int latency) { diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 592c0bd..53a344e 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -21,9 +21,9 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) struct stm32_usart *const usart = plat->base; u32 clock, int_div, frac_div, tmp;

- if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE) + if (((u32)usart & STM32_BUS_MASK) == STM32_APB1_PERIPH_BASE) clock = clock_get(CLOCK_APB1); - else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE) + else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2_PERIPH_BASE) clock = clock_get(CLOCK_APB2); else return -EINVAL;

This patch enables support for the smsc phy on the stm32f746-disco board.

Signed-off-by: Michael Kurz michi.kurz@gmail.com ---

Changes in v2: None

include/configs/stm32f746-disco.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 4088064..246cc2e 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -46,6 +46,7 @@ #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII +#define CONFIG_PHY_SMSC

#define CONFIG_STM32_HSE_HZ 25000000 #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */

This patch adds support for the QSPI IP found in stm32f7 devices.

Signed-off-by: Michael Kurz michi.kurz@gmail.com

--- This currently hard disables any multi i/o in the device tree, as it is impossible to get this working without interpreting the commands of the spi-flash framework in the xfer function and setting the used i/o lines accordingly. As i understand a spi-nor framework is currently in the making which addresses these problems. Should i base this driver on the new framework or is it ok in the current form and should later be ported to the new one?

Changes in v2: - Replaced bit shifts and masks with BIT() and GENMASK() macro

arch/arm/dts/stm32f746-disco.dts | 4 +- arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 6 +- arch/arm/mach-stm32/stm32f7/clock.c | 4 + board/st/stm32f746-disco/stm32f746-disco.c | 60 +++ configs/stm32f746-disco_defconfig | 7 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/stm32_qspi.c | 628 +++++++++++++++++++++++ 8 files changed, 714 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/stm32_qspi.c

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 7b652f0..b58889a 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -146,8 +146,8 @@ #size-cells = <1>; compatible = "micron,n25q128a13", "spi-flash"; spi-max-frequency = <108000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; memory-map = <0x90000000 0x1000000>; reg = <0>; }; diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h index 508b5f2..3c5604a 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -15,8 +15,9 @@ * */ enum periph_id { - UART1_GPIOA_9_10 = 0, - UART2_GPIOD_5_6, + PERIPH_ID_USART1 = 37, + + PERIPH_ID_QUADSPI = 92, };

enum periph_clock { @@ -37,6 +38,7 @@ enum periph_clock { TIMER2_CLOCK_CFG, FMC_CLOCK_CFG, STMMAC_CLOCK_CFG, + QSPI_CLOCK_CFG, };

#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c index b068828..818401e 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -71,6 +71,7 @@ struct stm32_rcc_regs { * RCC AHB3ENR specific definitions */ #define RCC_AHB3ENR_FMC_EN BIT(0) +#define RCC_AHB3ENR_QSPI_EN BIT(1)

/* * RCC APB1ENR specific definitions @@ -342,6 +343,9 @@ void clock_setup(int peripheral) setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); break; + case QSPI_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN); + break; default: break; } diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 970eabe..dcf3a4e 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -326,6 +326,60 @@ static int stmmac_setup(void) } #endif

+#ifdef CONFIG_STM32_QSPI +const struct stm32_gpio_ctl gpio_ctl_qspi_9 = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_100M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF9 +}; + +const struct stm32_gpio_ctl gpio_ctl_qspi_10 = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_100M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF10 +}; + +static const struct stm32_gpio_dsc qspi_af9_gpio[] = { + {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */ +}; + +static const struct stm32_gpio_dsc qspi_af10_gpio[] = { + {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */ +}; + +static int qspi_setup(void) +{ + int res = 0; + int i; + + clock_setup(GPIO_B_CLOCK_CFG); + clock_setup(GPIO_D_CLOCK_CFG); + clock_setup(GPIO_E_CLOCK_CFG); + + for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) { + res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9); + if (res) + return res; + } + + for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) { + res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10); + if (res) + return res; + } + + return 0; +} +#endif + u32 get_board_rev(void) { return 0; @@ -346,6 +400,12 @@ int board_early_init_f(void) return res; #endif

+#ifdef CONFIG_STM32_QSPI + res = qspi_setup(); + if (res) + return res; +#endif + return 0; }

diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 7301380..4a81f02 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -12,6 +12,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_SF=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -24,8 +25,14 @@ CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y # CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0f51b3a..f3f7dbe 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -124,6 +124,14 @@ config SANDBOX_SPI }; };

+config STM32_QSPI + bool "STM32F7 QSPI driver" + depends on STM32F7 + help + Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash chips on platforms embedding + this ST IP core. + config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 247c5f6..59068d0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o +obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c new file mode 100644 index 0000000..123a1f3 --- /dev/null +++ b/drivers/spi/stm32_qspi.c @@ -0,0 +1,628 @@ +/* + * (C) Copyright 2016 + * + * Michael Kurz, michi.kurz@gmail.com + * + * STM32 QSPI driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <spi_flash.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/stm32.h> +#include <asm/arch/stm32_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct stm32_qspi_regs { + u32 cr; /* 0x00 */ + u32 dcr; /* 0x04 */ + u32 sr; /* 0x08 */ + u32 fcr; /* 0x0C */ + u32 dlr; /* 0x10 */ + u32 ccr; /* 0x14 */ + u32 ar; /* 0x18 */ + u32 abr; /* 0x1C */ + u32 dr; /* 0x20 */ + u32 psmkr; /* 0x24 */ + u32 psmar; /* 0x28 */ + u32 pir; /* 0x2C */ + u32 lptr; /* 0x30 */ +}; + +/* + * QUADSPI control register + */ +#define STM32_QSPI_CR_EN BIT(0) +#define STM32_QSPI_CR_ABORT BIT(1) +#define STM32_QSPI_CR_DMAEN BIT(2) +#define STM32_QSPI_CR_TCEN BIT(3) +#define STM32_QSPI_CR_SSHIFT BIT(4) +#define STM32_QSPI_CR_DFM BIT(6) +#define STM32_QSPI_CR_FSEL BIT(7) +#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0) +#define STM32_QSPI_CR_FTHRES_SHIFT (8) +#define STM32_QSPI_CR_TEIE BIT(16) +#define STM32_QSPI_CR_TCIE BIT(17) +#define STM32_QSPI_CR_FTIE BIT(18) +#define STM32_QSPI_CR_SMIE BIT(19) +#define STM32_QSPI_CR_TOIE BIT(20) +#define STM32_QSPI_CR_APMS BIT(22) +#define STM32_QSPI_CR_PMM BIT(23) +#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0) +#define STM32_QSPI_CR_PRESCALER_SHIFT (24) + +/* + * QUADSPI device configuration register + */ +#define STM32_QSPI_DCR_CKMODE BIT(0) +#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0) +#define STM32_QSPI_DCR_CSHT_SHIFT (8) +#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0) +#define STM32_QSPI_DCR_FSIZE_SHIFT (16) + +/* + * QUADSPI status register + */ +#define STM32_QSPI_SR_TEF BIT(0) +#define STM32_QSPI_SR_TCF BIT(1) +#define STM32_QSPI_SR_FTF BIT(2) +#define STM32_QSPI_SR_SMF BIT(3) +#define STM32_QSPI_SR_TOF BIT(4) +#define STM32_QSPI_SR_BUSY BIT(5) +#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0) +#define STM32_QSPI_SR_FLEVEL_SHIFT (8) + +/* + * QUADSPI flag clear register + */ +#define STM32_QSPI_FCR_CTEF BIT(0) +#define STM32_QSPI_FCR_CTCF BIT(1) +#define STM32_QSPI_FCR_CSMF BIT(3) +#define STM32_QSPI_FCR_CTOF BIT(4) + +/* + * QUADSPI communication configuration register + */ +#define STM32_QSPI_CCR_DDRM BIT(31) +#define STM32_QSPI_CCR_DHHC BIT(30) +#define STM32_QSPI_CCR_SIOO BIT(28) +#define STM32_QSPI_CCR_FMODE_SHIFT (26) +#define STM32_QSPI_CCR_DMODE_SHIFT (24) +#define STM32_QSPI_CCR_DCYC_SHIFT (18) +#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0) +#define STM32_QSPI_CCR_ABSIZE_SHIFT (16) +#define STM32_QSPI_CCR_ABMODE_SHIFT (14) +#define STM32_QSPI_CCR_ADSIZE_SHIFT (12) +#define STM32_QSPI_CCR_ADMODE_SHIFT (10) +#define STM32_QSPI_CCR_IMODE_SHIFT (8) +#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0) + +enum STM32_QSPI_CCR_IMODE { + STM32_QSPI_CCR_IMODE_NONE = 0, + STM32_QSPI_CCR_IMODE_ONE_LINE = 1, + STM32_QSPI_CCR_IMODE_TWO_LINE = 2, + STM32_QSPI_CCR_IMODE_FOUR_LINE = 3, +}; + +enum STM32_QSPI_CCR_ADMODE { + STM32_QSPI_CCR_ADMODE_NONE = 0, + STM32_QSPI_CCR_ADMODE_ONE_LINE = 1, + STM32_QSPI_CCR_ADMODE_TWO_LINE = 2, + STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3, +}; + +enum STM32_QSPI_CCR_ADSIZE { + STM32_QSPI_CCR_ADSIZE_8BIT = 0, + STM32_QSPI_CCR_ADSIZE_16BIT = 1, + STM32_QSPI_CCR_ADSIZE_24BIT = 2, + STM32_QSPI_CCR_ADSIZE_32BIT = 3, +}; + +enum STM32_QSPI_CCR_ABMODE { + STM32_QSPI_CCR_ABMODE_NONE = 0, + STM32_QSPI_CCR_ABMODE_ONE_LINE = 1, + STM32_QSPI_CCR_ABMODE_TWO_LINE = 2, + STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3, +}; + +enum STM32_QSPI_CCR_ABSIZE { + STM32_QSPI_CCR_ABSIZE_8BIT = 0, + STM32_QSPI_CCR_ABSIZE_16BIT = 1, + STM32_QSPI_CCR_ABSIZE_24BIT = 2, + STM32_QSPI_CCR_ABSIZE_32BIT = 3, +}; + +enum STM32_QSPI_CCR_DMODE { + STM32_QSPI_CCR_DMODE_NONE = 0, + STM32_QSPI_CCR_DMODE_ONE_LINE = 1, + STM32_QSPI_CCR_DMODE_TWO_LINE = 2, + STM32_QSPI_CCR_DMODE_FOUR_LINE = 3, +}; + +enum STM32_QSPI_CCR_FMODE { + STM32_QSPI_CCR_IND_WRITE = 0, + STM32_QSPI_CCR_IND_READ = 1, + STM32_QSPI_CCR_AUTO_POLL = 2, + STM32_QSPI_CCR_MEM_MAP = 3, +}; + +/* default SCK frequency, unit: HZ */ +#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000 + +struct stm32_qspi_platdata { + u32 base; + u32 memory_map; + u32 max_hz; +}; + +struct stm32_qspi_priv { + struct stm32_qspi_regs *regs; + u32 max_hz; + u32 mode; + + u32 command; + u32 address; + u32 dummycycles; +#define CMD_HAS_ADR BIT(24) +#define CMD_HAS_DUMMY BIT(25) +#define CMD_HAS_DATA BIT(26) +}; + +static void _stm32_qspi_disable(struct stm32_qspi_priv *priv) +{ + clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); +} + +static void _stm32_qspi_enable(struct stm32_qspi_priv *priv) +{ + setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); +} + +static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) +{ + while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) + ; +} + +static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv) +{ + while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) + ; +} + +static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) +{ + while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) + ; +} + +static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size) +{ + u32 fsize = fls(size) - 1; + clrsetbits_le32(&priv->regs->dcr, + STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT, + fsize << STM32_QSPI_DCR_FSIZE_SHIFT); +} + +static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) +{ + unsigned int ccr_reg = 0; + u8 imode, admode, dmode; + u32 mode = priv->mode; + u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); + + imode = STM32_QSPI_CCR_IMODE_ONE_LINE; + admode = STM32_QSPI_CCR_ADMODE_ONE_LINE; + + if (mode & SPI_RX_QUAD) { + dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; + if (mode & SPI_TX_QUAD) { + imode = STM32_QSPI_CCR_IMODE_FOUR_LINE; + admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE; + } + } else if (mode & SPI_RX_DUAL) { + dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; + if (mode & SPI_TX_DUAL) { + imode = STM32_QSPI_CCR_IMODE_TWO_LINE; + admode = STM32_QSPI_CCR_ADMODE_TWO_LINE; + } + } else { + dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; + } + + if (priv->command & CMD_HAS_DATA) + ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT); + + if (priv->command & CMD_HAS_DUMMY) + ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK) + << STM32_QSPI_CCR_DCYC_SHIFT); + + if (priv->command & CMD_HAS_ADR) { + ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT + << STM32_QSPI_CCR_ADSIZE_SHIFT); + ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT); + } + ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT); + ccr_reg |= cmd; + return ccr_reg; +} + +static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv, + struct spi_flash *flash) +{ + priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA + | CMD_HAS_DUMMY; + priv->dummycycles = flash->dummy_byte * 8; + + unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv); + ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT); + + _stm32_qspi_wait_for_not_busy(priv); + + writel(ccr_reg, &priv->regs->ccr); + + priv->dummycycles = 0; +} + +static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv) +{ + setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT); +} + +static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv, + u32 length) +{ + writel(length - 1, &priv->regs->dlr); +} + +static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg) +{ + writel(cr_reg, &priv->regs->ccr); + + if (priv->command & CMD_HAS_ADR) + writel(priv->address, &priv->regs->ar); +} + +static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, + struct spi_flash *flash, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) +{ + unsigned int words = bitlen / 8; + + if (flags & SPI_XFER_MMAP) { + _stm32_qspi_enable_mmap(priv, flash); + return 0; + } else if (flags & SPI_XFER_MMAP_END) { + _stm32_qspi_disable_mmap(priv); + return 0; + } + + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + debug("spi_xfer: Non byte aligned SPI transfer\n"); + return -1; + } + + if (dout && din) { + debug("spi_xfer: QSPI cannot have data in and data out set\n"); + return -1; + } + + if (!dout && (flags & SPI_XFER_BEGIN)) { + debug("spi_xfer: QSPI transfer must begin with command\n"); + return -1; + } + + if (dout) { + if (flags & SPI_XFER_BEGIN) { + /* data is command */ + priv->command = dout[0] | CMD_HAS_DATA; + if (words >= 4) { + /* address is here too */ + priv->address = (dout[1] << 16) | + (dout[2] << 8) | dout[3]; + priv->command |= CMD_HAS_ADR; + } + + if (words > 4) { + /* rest is dummy bytes */ + priv->dummycycles = (words - 4) * 8; + priv->command |= CMD_HAS_DUMMY; + } + + if (flags & SPI_XFER_END) { + /* command without data */ + priv->command &= ~(CMD_HAS_DATA); + } + } + + if (flags & SPI_XFER_END) { + u32 ccr_reg = _stm32_qspi_gen_ccr(priv); + ccr_reg |= STM32_QSPI_CCR_IND_WRITE + << STM32_QSPI_CCR_FMODE_SHIFT; + + _stm32_qspi_wait_for_not_busy(priv); + + if (priv->command & CMD_HAS_DATA) + _stm32_qspi_set_xfer_length(priv, words); + + _stm32_qspi_start_xfer(priv, ccr_reg); + + debug("%s: write: ccr:0x%08x adr:0x%08x\n", + __func__, priv->regs->ccr, priv->regs->ar); + + if (priv->command & CMD_HAS_DATA) { + _stm32_qspi_wait_for_ftf(priv); + + debug("%s: words:%d data:", __func__, words); + + int i = 0; + while (words > i) { + writeb(dout[i], &priv->regs->dr); + debug("%02x ", dout[i]); + i++; + } + debug("\n"); + + _stm32_qspi_wait_for_complete(priv); + } else { + _stm32_qspi_wait_for_not_busy(priv); + } + } + } else if (din) { + u32 ccr_reg = _stm32_qspi_gen_ccr(priv); + ccr_reg |= STM32_QSPI_CCR_IND_READ + << STM32_QSPI_CCR_FMODE_SHIFT; + + _stm32_qspi_wait_for_not_busy(priv); + + _stm32_qspi_set_xfer_length(priv, words); + + _stm32_qspi_start_xfer(priv, ccr_reg); + + debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__, + priv->regs->ccr, priv->regs->ar, priv->regs->dlr); + + debug("%s: data:", __func__); + + int i = 0; + while (words > i) { + din[i] = readb(&priv->regs->dr); + debug("%02x ", din[i]); + i++; + } + debug("\n"); + } + + return 0; +} + +static int stm32_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct fdt_resource res_regs, res_mem; + struct stm32_qspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + int ret; + + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "QuadSPI", &res_regs); + if (ret) { + debug("Error: can't get regs base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "QuadSPI-memory", &res_mem); + if (ret) { + debug("Error: can't get mmap base address(ret = %d)!\n", ret); + return -ENOMEM; + } + + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + STM32_QSPI_DEFAULT_SCK_FREQ); + + plat->base = res_regs.start; + plat->memory_map = res_mem.start; + + debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n", + __func__, + plat->base, + plat->memory_map, + plat->max_hz + ); + + return 0; +} + +static int stm32_qspi_probe(struct udevice *bus) +{ + struct stm32_qspi_platdata *plat = dev_get_platdata(bus); + struct stm32_qspi_priv *priv = dev_get_priv(bus); + struct dm_spi_bus *dm_spi_bus; + + dm_spi_bus = bus->uclass_priv; + + dm_spi_bus->max_hz = plat->max_hz; + + priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; + + priv->max_hz = plat->max_hz; + + clock_setup(QSPI_CLOCK_CFG); + + setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); + + return 0; +} + +static int stm32_qspi_remove(struct udevice *bus) +{ + return 0; +} + +static int stm32_qspi_claim_bus(struct udevice *dev) +{ + struct stm32_qspi_priv *priv; + struct udevice *bus; + struct spi_flash *flash; + + bus = dev->parent; + priv = dev_get_priv(bus); + flash = dev_get_uclass_priv(dev); + + _stm32_qspi_set_flash_size(priv, flash->size); + + _stm32_qspi_enable(priv); + + return 0; +} + +static int stm32_qspi_release_bus(struct udevice *dev) +{ + struct stm32_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + _stm32_qspi_disable(priv); + + return 0; +} + +static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct stm32_qspi_priv *priv; + struct udevice *bus; + struct spi_flash *flash; + + bus = dev->parent; + priv = dev_get_priv(bus); + flash = dev_get_uclass_priv(dev); + + return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout, + (u8 *)din, flags); +} + +static int stm32_qspi_set_speed(struct udevice *bus, uint speed) +{ + struct stm32_qspi_platdata *plat = bus->platdata; + struct stm32_qspi_priv *priv = dev_get_priv(bus); + + if (speed > plat->max_hz) + speed = plat->max_hz; + + u32 qspi_clk = clock_get(CLOCK_AHB); + u32 prescaler = 255; + if (speed > 0) { + prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; + if (prescaler > 255) + prescaler = 255; + else if (prescaler < 0) + prescaler = 0; + } + + u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); + csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK; + + _stm32_qspi_wait_for_not_busy(priv); + + clrsetbits_le32(&priv->regs->cr, + STM32_QSPI_CR_PRESCALER_MASK << + STM32_QSPI_CR_PRESCALER_SHIFT, + prescaler << STM32_QSPI_CR_PRESCALER_SHIFT); + + + clrsetbits_le32(&priv->regs->dcr, + STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT, + csht << STM32_QSPI_DCR_CSHT_SHIFT); + + debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, + (qspi_clk / (prescaler + 1))); + + return 0; +} + +static int stm32_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct stm32_qspi_priv *priv = dev_get_priv(bus); + + _stm32_qspi_wait_for_not_busy(priv); + + if ((mode & SPI_CPHA) && (mode & SPI_CPOL)) + setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); + else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL)) + clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); + else + return -ENODEV; + + if (mode & SPI_CS_HIGH) + return -ENODEV; + + if (mode & SPI_RX_QUAD) + priv->mode |= SPI_RX_QUAD; + else if (mode & SPI_RX_DUAL) + priv->mode |= SPI_RX_DUAL; + else + priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL); + + if (mode & SPI_TX_QUAD) + priv->mode |= SPI_TX_QUAD; + else if (mode & SPI_TX_DUAL) + priv->mode |= SPI_TX_DUAL; + else + priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL); + + debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); + + if (mode & SPI_RX_QUAD) + debug("quad, tx: "); + else if (mode & SPI_RX_DUAL) + debug("dual, tx: "); + else + debug("single, tx: "); + + if (mode & SPI_TX_QUAD) + debug("quad\n"); + else if (mode & SPI_TX_DUAL) + debug("dual\n"); + else + debug("single\n"); + + return 0; +} + +static const struct dm_spi_ops stm32_qspi_ops = { + .claim_bus = stm32_qspi_claim_bus, + .release_bus = stm32_qspi_release_bus, + .xfer = stm32_qspi_xfer, + .set_speed = stm32_qspi_set_speed, + .set_mode = stm32_qspi_set_mode, +}; + +static const struct udevice_id stm32_qspi_ids[] = { + { .compatible = "st,stm32-qspi" }, + { } +}; + +U_BOOT_DRIVER(stm32_qspi) = { + .name = "stm32_qspi", + .id = UCLASS_SPI, + .of_match = stm32_qspi_ids, + .ops = &stm32_qspi_ops, + .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv), + .probe = stm32_qspi_probe, + .remove = stm32_qspi_remove, +};