[U-Boot] [PATCH 1/3] x86: fsp: Consolidate Azalia header file
So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic.
This also corrects reset_wait_timer from us to ms.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/baytrail/fsp_configs.c | 13 ++++---- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 ------------------------ arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 26 ---------------- arch/x86/include/asm/fsp/fsp_azalia.h | 39 ++++++++++++++++++++++++ arch/x86/include/asm/fsp/fsp_support.h | 1 + 5 files changed, 46 insertions(+), 72 deletions(-) delete mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 45f9bf9..926f26b 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -8,13 +8,12 @@
#include <common.h> #include <fdtdec.h> -#include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
/* ALC262 Verb Table - 10EC0262 */ -static const uint32_t verb_table_data13[] = { +static const u32 verb_table_data13[] = { /* Pin Complex (NID 0x11) */ 0x01171cf0, 0x01171d11, @@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = { * Codec Address: CAd value (0/1/2) * Codec Vendor: 0x10EC0262 */ -static const struct pch_azalia_verb_table azalia_verb_table[] = { +static const struct azalia_verb_table azalia_verb_table[] = { { { 0x10ec0262, @@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table azalia_verb_table[] = { } };
-const struct pch_azalia_config azalia_config = { +const struct azalia_config azalia_config = { .pme_enable = 1, .docking_supported = 1, .docking_attached = 0, .hdmi_codec_enable = 1, .azalia_v_ci_enable = 1, .rsvdbits = 0, - .azalia_verb_table_num = 1, - .azalia_verb_table = azalia_verb_table, - .reset_wait_timer_us = 300 + .verb_table_num = 1, + .verb_table = azalia_verb_table, + .reset_wait_timer_ms = 300 };
/** diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h deleted file mode 100644 index d96a20f..0000000 --- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2015 Google, Inc - * - * SPDX-License-Identifier: Intel - */ - -#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_ - -struct __packed pch_azalia_verb_table_header { - uint32_t vendor_device_id; - uint16_t sub_system_id; - uint8_t revision_id; /* 0xff applies to all steppings */ - uint8_t front_panel_support; - uint16_t number_of_rear_jacks; - uint16_t number_of_front_jacks; -}; - -struct __packed pch_azalia_verb_table { - struct pch_azalia_verb_table_header verb_table_header; - const uint32_t *verb_table_data; -}; - -struct __packed pch_azalia_config { - uint8_t pme_enable:1; - uint8_t docking_supported:1; - uint8_t docking_attached:1; - uint8_t hdmi_codec_enable:1; - uint8_t azalia_v_ci_enable:1; - uint8_t rsvdbits:3; - /* number of verb tables provided by platform */ - uint8_t azalia_verb_table_num; - const struct pch_azalia_verb_table *azalia_verb_table; - /* delay timer after azalia reset */ - uint16_t reset_wait_timer_us; -}; - -#endif diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h index ecb01fa..99c4c0a 100644 --- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h @@ -29,32 +29,6 @@ struct __packed memory_upd { u8 reserved[189]; /* Offset 0x0043 */ };
-struct __packed azalia_verb_table_header { - u32 vendor_device_id; - u16 sub_system_id; - u8 revision_id; - u8 front_panel_support; - u16 number_of_rear_jacks; - u16 number_of_front_jacks; -}; - -struct __packed azalia_verb_table { - struct azalia_verb_table_header header; - u32 *data; -}; - -struct __packed azalia_config { - u8 pme_enable:1; - u8 docking_supported:1; - u8 docking_attached:1; - u8 hdmi_codec_enable:1; - u8 azalia_v_ci_enable:1; - u8 reserved:3; - u8 verb_table_num; - struct azalia_verb_table *verb_table; - u16 reset_wait_timer_ms; -}; - struct gpio_family { u32 confg; u32 confg_changes; diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h new file mode 100644 index 0000000..a1467bf --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_azalia.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: Intel + */ + +#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_ + +struct __packed azalia_verb_table_header { + u32 vendor_device_id; + u16 sub_system_id; + u8 revision_id; /* 0xff applies to all steppings */ + u8 front_panel_support; + u16 number_of_rear_jacks; + u16 number_of_front_jacks; +}; + +struct __packed azalia_verb_table { + struct azalia_verb_table_header header; + const u32 *data; +}; + +struct __packed azalia_config { + u8 pme_enable:1; + u8 docking_supported:1; + u8 docking_attached:1; + u8 hdmi_codec_enable:1; + u8 azalia_v_ci_enable:1; + u8 rsvdbits:3; + /* number of verb tables provided by platform */ + u8 verb_table_num; + const struct azalia_verb_table *verb_table; + /* delay timer after azalia reset */ + u16 reset_wait_timer_ms; +}; + +#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 97a50b0..df3add0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -15,6 +15,7 @@ #include "fsp_hob.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" +#include "fsp_azalia.h" #include <asm/arch/fsp/fsp_vpd.h> #include <asm/arch/fsp/fsp_configs.h>
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/baytrail/fsp_configs.c | 15 +++++++++++++-- arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 2 +- 2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 926f26b..3052fb6 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -120,6 +120,17 @@ const struct azalia_config azalia_config = { };
/** + * Override the FSP's Azalia configuration data + * + * @azalia: pointer to be updated to point to a ROM address where Azalia + * configuration data is stored + */ +static void update_fsp_azalia_configs(struct azalia_config **azalia) +{ + *azalia = (struct azalia_config *)&azalia_config; +} + +/** * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. @@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config, rt_buf->common.boot_mode = config->common.boot_mode; rt_buf->common.upd_data = &config->fsp_upd;
- fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); if (node < 0) { debug("%s: Cannot find FSP node\n", __func__); @@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config, SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); + if (fsp_upd->enable_azalia) + update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", LPE_MODE_PCI); diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 8c07b37..e2f0e39 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -45,7 +45,7 @@ struct __packed upd_region { uint8_t enable_sata; /* Offset 0x002d */ uint8_t sata_mode; /* Offset 0x002e */ uint8_t enable_azalia; /* Offset 0x002f */ - uint32_t azalia_config_ptr; /* Offset 0x0030 */ + struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ uint8_t lpe_mode; /* Offset 0x0035 */ uint8_t lpss_sio_mode; /* Offset 0x0036 */
On 13.10.2017 10:30, Bin Meng wrote:
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 15 +++++++++++++-- arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 2 +- 2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 926f26b..3052fb6 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -120,6 +120,17 @@ const struct azalia_config azalia_config = { };
/**
- Override the FSP's Azalia configuration data
- @azalia: pointer to be updated to point to a ROM address where Azalia
configuration data is stored- */
+static void update_fsp_azalia_configs(struct azalia_config **azalia) +{
- *azalia = (struct azalia_config *)&azalia_config;
+}
+/**
- Override the FSP's configuration data.
- If the device tree does not specify an integer setting, use the default
- provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
@@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config, rt_buf->common.boot_mode = config->common.boot_mode; rt_buf->common.upd_data = &config->fsp_upd;
- fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); if (node < 0) { debug("%s: Cannot find FSP node\n", __func__);
@@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config, SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia");
- if (fsp_upd->enable_azalia)
update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr);diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 8c07b37..e2f0e39 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -45,7 +45,7 @@ struct __packed upd_region { uint8_t enable_sata; /* Offset 0x002d */ uint8_t sata_mode; /* Offset 0x002e */ uint8_t enable_azalia; /* Offset 0x002f */
- uint32_t azalia_config_ptr; /* Offset 0x0030 */
- struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ uint8_t lpe_mode; /* Offset 0x0035 */ uint8_t lpss_sio_mode; /* Offset 0x0036 */
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Fri, Oct 13, 2017 at 7:14 PM, Stefan Roese sr@denx.de wrote:
On 13.10.2017 10:30, Bin Meng wrote:
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 15 +++++++++++++-- arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 2 +- 2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 926f26b..3052fb6 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -120,6 +120,17 @@ const struct azalia_config azalia_config = { }; /**
- Override the FSP's Azalia configuration data
- @azalia: pointer to be updated to point to a ROM address where
Azalia
configuration data is stored- */
+static void update_fsp_azalia_configs(struct azalia_config **azalia) +{
*azalia = (struct azalia_config *)&azalia_config;+}
+/**
- Override the FSP's configuration data.
- If the device tree does not specify an integer setting, use the
default
- provided in Intel's Baytrail_FSP_Gold4.tgz release
FSP/BayleyBayFsp.bsf file. @@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config, rt_buf->common.boot_mode = config->common.boot_mode; rt_buf->common.upd_data = &config->fsp_upd;
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); if (node < 0) { debug("%s: Cannot find FSP node\n", __func__);@@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config, SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia");
if (fsp_upd->enable_azalia)update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node,"fsp,enable-xhci"); fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", LPE_MODE_PCI); diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 8c07b37..e2f0e39 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -45,7 +45,7 @@ struct __packed upd_region { uint8_t enable_sata; /* Offset 0x002d */ uint8_t sata_mode; /* Offset 0x002e */ uint8_t enable_azalia; /* Offset 0x002f */
uint32_t azalia_config_ptr; /* Offset 0x0030 */
struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ uint8_t lpe_mode; /* Offset 0x0035 */ uint8_t lpss_sio_mode; /* Offset 0x0036 */Reviewed-by: Stefan Roese sr@denx.de
applied to u-boot-x86, thanks!
Azalia configuration may be different across boards, hence it's not appropriate to do that in the SoC level. Instead, let's make the SoC update_fsp_azalia_configs() routine as a weak version, and do the actual work in the board codes.
So far it seems only som-db5800-som-6867 board enables the Azalia. Move the original codes into som-db5800-som-6867.c.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/baytrail/fsp_configs.c | 111 +-------------------- .../som-db5800-som-6867/som-db5800-som-6867.c | 111 +++++++++++++++++++++ 2 files changed, 113 insertions(+), 109 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 3052fb6..6b762e5 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -12,122 +12,15 @@
DECLARE_GLOBAL_DATA_PTR;
-/* ALC262 Verb Table - 10EC0262 */ -static const u32 verb_table_data13[] = { - /* Pin Complex (NID 0x11) */ - 0x01171cf0, - 0x01171d11, - 0x01171e11, - 0x01171f41, - /* Pin Complex (NID 0x12) */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d40, - 0x01471e01, - 0x01471f01, - /* Pin Complex (NID 0x15) */ - 0x01571cf0, - 0x01571d11, - 0x01571e11, - 0x01571f41, - /* Pin Complex (NID 0x16) */ - 0x01671cf0, - 0x01671d11, - 0x01671e11, - 0x01671f41, - /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d98, - 0x01871ea1, - 0x01871f01, - /* Pin Complex (NID 0x19) */ - 0x01971c21, - 0x01971d98, - 0x01971ea1, - 0x01971f02, - /* Pin Complex (NID 0x1A) */ - 0x01a71c2f, - 0x01a71d30, - 0x01a71e81, - 0x01a71f01, - /* Pin Complex */ - 0x01b71c1f, - 0x01b71d40, - 0x01b71e21, - 0x01b71f02, - /* Pin Complex */ - 0x01c71cf0, - 0x01c71d11, - 0x01c71e11, - 0x01c71f41, - /* Pin Complex */ - 0x01d71c01, - 0x01d71dc6, - 0x01d71e14, - 0x01d71f40, - /* Pin Complex */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - /* Pin Complex */ - 0x01f71cf0, - 0x01f71d11, - 0x01f71e11, - 0x01f71f41, -}; - -/* - * This needs to be in ROM since if we put it in CAR, FSP init loses it when - * it drops CAR. - * - * TODO(sjg@chromium.org): Move to device tree when FSP allows it - * - * VerbTable: (RealTek ALC262) - * Revision ID = 0xFF, support all steps - * Codec Verb Table For AZALIA - * Codec Address: CAd value (0/1/2) - * Codec Vendor: 0x10EC0262 - */ -static const struct azalia_verb_table azalia_verb_table[] = { - { - { - 0x10ec0262, - 0x0000, - 0xff, - 0x01, - 0x000b, - 0x0002, - }, - verb_table_data13 - } -}; - -const struct azalia_config azalia_config = { - .pme_enable = 1, - .docking_supported = 1, - .docking_attached = 0, - .hdmi_codec_enable = 1, - .azalia_v_ci_enable = 1, - .rsvdbits = 0, - .verb_table_num = 1, - .verb_table = azalia_verb_table, - .reset_wait_timer_ms = 300 -}; - /** * Override the FSP's Azalia configuration data * * @azalia: pointer to be updated to point to a ROM address where Azalia * configuration data is stored */ -static void update_fsp_azalia_configs(struct azalia_config **azalia) +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) { - *azalia = (struct azalia_config *)&azalia_config; + *azalia = NULL; }
/** diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 6158795..202e9875 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -6,6 +6,117 @@ */
#include <common.h> +#include <asm/fsp/fsp_support.h> + +/* ALC262 Verb Table - 10EC0262 */ +static const u32 verb_table_data13[] = { + /* Pin Complex (NID 0x11) */ + 0x01171cf0, + 0x01171d11, + 0x01171e11, + 0x01171f41, + /* Pin Complex (NID 0x12) */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d40, + 0x01471e01, + 0x01471f01, + /* Pin Complex (NID 0x15) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin Complex (NID 0x16) */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d98, + 0x01871ea1, + 0x01871f01, + /* Pin Complex (NID 0x19) */ + 0x01971c21, + 0x01971d98, + 0x01971ea1, + 0x01971f02, + /* Pin Complex (NID 0x1A) */ + 0x01a71c2f, + 0x01a71d30, + 0x01a71e81, + 0x01a71f01, + /* Pin Complex */ + 0x01b71c1f, + 0x01b71d40, + 0x01b71e21, + 0x01b71f02, + /* Pin Complex */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin Complex */ + 0x01d71c01, + 0x01d71dc6, + 0x01d71e14, + 0x01d71f40, + /* Pin Complex */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + /* Pin Complex */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +/* + * This needs to be in ROM since if we put it in CAR, FSP init loses it when + * it drops CAR. + * + * VerbTable: (RealTek ALC262) + * Revision ID = 0xFF, support all steps + * Codec Verb Table For AZALIA + * Codec Address: CAd value (0/1/2) + * Codec Vendor: 0x10EC0262 + */ +static const struct azalia_verb_table azalia_verb_table[] = { + { + { + 0x10ec0262, + 0x0000, + 0xff, + 0x01, + 0x000b, + 0x0002, + }, + verb_table_data13 + } +}; + +static const struct azalia_config azalia_config = { + .pme_enable = 1, + .docking_supported = 1, + .docking_attached = 0, + .hdmi_codec_enable = 1, + .azalia_v_ci_enable = 1, + .rsvdbits = 0, + .verb_table_num = 1, + .verb_table = azalia_verb_table, + .reset_wait_timer_ms = 300 +}; + +void update_fsp_azalia_configs(const struct azalia_config **azalia) +{ + *azalia = &azalia_config; +}
int board_early_init_f(void) {
On 13.10.2017 10:30, Bin Meng wrote:
Azalia configuration may be different across boards, hence it's not appropriate to do that in the SoC level. Instead, let's make the SoC update_fsp_azalia_configs() routine as a weak version, and do the actual work in the board codes.
So far it seems only som-db5800-som-6867 board enables the Azalia. Move the original codes into som-db5800-som-6867.c.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 111 +-------------------- .../som-db5800-som-6867/som-db5800-som-6867.c | 111 +++++++++++++++++++++ 2 files changed, 113 insertions(+), 109 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 3052fb6..6b762e5 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -12,122 +12,15 @@
DECLARE_GLOBAL_DATA_PTR;
-/* ALC262 Verb Table - 10EC0262 */ -static const u32 verb_table_data13[] = {
- /* Pin Complex (NID 0x11) */
- 0x01171cf0,
- 0x01171d11,
- 0x01171e11,
- 0x01171f41,
- /* Pin Complex (NID 0x12) */
- 0x01271cf0,
- 0x01271d11,
- 0x01271e11,
- 0x01271f41,
- /* Pin Complex (NID 0x14) */
- 0x01471c10,
- 0x01471d40,
- 0x01471e01,
- 0x01471f01,
- /* Pin Complex (NID 0x15) */
- 0x01571cf0,
- 0x01571d11,
- 0x01571e11,
- 0x01571f41,
- /* Pin Complex (NID 0x16) */
- 0x01671cf0,
- 0x01671d11,
- 0x01671e11,
- 0x01671f41,
- /* Pin Complex (NID 0x18) */
- 0x01871c20,
- 0x01871d98,
- 0x01871ea1,
- 0x01871f01,
- /* Pin Complex (NID 0x19) */
- 0x01971c21,
- 0x01971d98,
- 0x01971ea1,
- 0x01971f02,
- /* Pin Complex (NID 0x1A) */
- 0x01a71c2f,
- 0x01a71d30,
- 0x01a71e81,
- 0x01a71f01,
- /* Pin Complex */
- 0x01b71c1f,
- 0x01b71d40,
- 0x01b71e21,
- 0x01b71f02,
- /* Pin Complex */
- 0x01c71cf0,
- 0x01c71d11,
- 0x01c71e11,
- 0x01c71f41,
- /* Pin Complex */
- 0x01d71c01,
- 0x01d71dc6,
- 0x01d71e14,
- 0x01d71f40,
- /* Pin Complex */
- 0x01e71cf0,
- 0x01e71d11,
- 0x01e71e11,
- 0x01e71f41,
- /* Pin Complex */
- 0x01f71cf0,
- 0x01f71d11,
- 0x01f71e11,
- 0x01f71f41,
-};
-/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
-static const struct azalia_verb_table azalia_verb_table[] = {
- {
{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13- }
-};
-const struct azalia_config azalia_config = {
- .pme_enable = 1,
- .docking_supported = 1,
- .docking_attached = 0,
- .hdmi_codec_enable = 1,
- .azalia_v_ci_enable = 1,
- .rsvdbits = 0,
- .verb_table_num = 1,
- .verb_table = azalia_verb_table,
- .reset_wait_timer_ms = 300
-};
- /**
*/
- Override the FSP's Azalia configuration data
- @azalia: pointer to be updated to point to a ROM address where Azalia
configuration data is stored-static void update_fsp_azalia_configs(struct azalia_config **azalia) +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) {
- *azalia = (struct azalia_config *)&azalia_config;
*azalia = NULL; }
/**
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 6158795..202e9875 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -6,6 +6,117 @@ */
#include <common.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const u32 verb_table_data13[] = {
- /* Pin Complex (NID 0x11) */
- 0x01171cf0,
- 0x01171d11,
- 0x01171e11,
- 0x01171f41,
- /* Pin Complex (NID 0x12) */
- 0x01271cf0,
- 0x01271d11,
- 0x01271e11,
- 0x01271f41,
- /* Pin Complex (NID 0x14) */
- 0x01471c10,
- 0x01471d40,
- 0x01471e01,
- 0x01471f01,
- /* Pin Complex (NID 0x15) */
- 0x01571cf0,
- 0x01571d11,
- 0x01571e11,
- 0x01571f41,
- /* Pin Complex (NID 0x16) */
- 0x01671cf0,
- 0x01671d11,
- 0x01671e11,
- 0x01671f41,
- /* Pin Complex (NID 0x18) */
- 0x01871c20,
- 0x01871d98,
- 0x01871ea1,
- 0x01871f01,
- /* Pin Complex (NID 0x19) */
- 0x01971c21,
- 0x01971d98,
- 0x01971ea1,
- 0x01971f02,
- /* Pin Complex (NID 0x1A) */
- 0x01a71c2f,
- 0x01a71d30,
- 0x01a71e81,
- 0x01a71f01,
- /* Pin Complex */
- 0x01b71c1f,
- 0x01b71d40,
- 0x01b71e21,
- 0x01b71f02,
- /* Pin Complex */
- 0x01c71cf0,
- 0x01c71d11,
- 0x01c71e11,
- 0x01c71f41,
- /* Pin Complex */
- 0x01d71c01,
- 0x01d71dc6,
- 0x01d71e14,
- 0x01d71f40,
- /* Pin Complex */
- 0x01e71cf0,
- 0x01e71d11,
- 0x01e71e11,
- 0x01e71f41,
- /* Pin Complex */
- 0x01f71cf0,
- 0x01f71d11,
- 0x01f71e11,
- 0x01f71f41,
+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it when
- it drops CAR.
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct azalia_verb_table azalia_verb_table[] = {
- {
{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13- }
+};
+static const struct azalia_config azalia_config = {
- .pme_enable = 1,
- .docking_supported = 1,
- .docking_attached = 0,
- .hdmi_codec_enable = 1,
- .azalia_v_ci_enable = 1,
- .rsvdbits = 0,
- .verb_table_num = 1,
- .verb_table = azalia_verb_table,
- .reset_wait_timer_ms = 300
+};
+void update_fsp_azalia_configs(const struct azalia_config **azalia) +{
- *azalia = &azalia_config;
+}
int board_early_init_f(void) {
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Fri, Oct 13, 2017 at 7:14 PM, Stefan Roese sr@denx.de wrote:
On 13.10.2017 10:30, Bin Meng wrote:
Azalia configuration may be different across boards, hence it's not appropriate to do that in the SoC level. Instead, let's make the SoC update_fsp_azalia_configs() routine as a weak version, and do the actual work in the board codes.
So far it seems only som-db5800-som-6867 board enables the Azalia. Move the original codes into som-db5800-som-6867.c.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 111 +-------------------- .../som-db5800-som-6867/som-db5800-som-6867.c | 111 +++++++++++++++++++++ 2 files changed, 113 insertions(+), 109 deletions(-)
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 3052fb6..6b762e5 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -12,122 +12,15 @@ DECLARE_GLOBAL_DATA_PTR; -/* ALC262 Verb Table - 10EC0262 */ -static const u32 verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,-};
-/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it
when
- it drops CAR.
- TODO(sjg@chromium.org): Move to device tree when FSP allows it
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
-static const struct azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}-};
-const struct azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.verb_table_num = 1,.verb_table = azalia_verb_table,.reset_wait_timer_ms = 300-};
- /**
- Override the FSP's Azalia configuration data
- @azalia: pointer to be updated to point to a ROM address where
Azalia
configuration data is stored*/ -static void update_fsp_azalia_configs(struct azalia_config **azalia) +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) {
*azalia = (struct azalia_config *)&azalia_config;
*azalia = NULL;diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 6158795..202e9875 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -6,6 +6,117 @@ */ #include <common.h> +#include <asm/fsp/fsp_support.h>
+/* ALC262 Verb Table - 10EC0262 */ +static const u32 verb_table_data13[] = {
/* Pin Complex (NID 0x11) */0x01171cf0,0x01171d11,0x01171e11,0x01171f41,/* Pin Complex (NID 0x12) */0x01271cf0,0x01271d11,0x01271e11,0x01271f41,/* Pin Complex (NID 0x14) */0x01471c10,0x01471d40,0x01471e01,0x01471f01,/* Pin Complex (NID 0x15) */0x01571cf0,0x01571d11,0x01571e11,0x01571f41,/* Pin Complex (NID 0x16) */0x01671cf0,0x01671d11,0x01671e11,0x01671f41,/* Pin Complex (NID 0x18) */0x01871c20,0x01871d98,0x01871ea1,0x01871f01,/* Pin Complex (NID 0x19) */0x01971c21,0x01971d98,0x01971ea1,0x01971f02,/* Pin Complex (NID 0x1A) */0x01a71c2f,0x01a71d30,0x01a71e81,0x01a71f01,/* Pin Complex */0x01b71c1f,0x01b71d40,0x01b71e21,0x01b71f02,/* Pin Complex */0x01c71cf0,0x01c71d11,0x01c71e11,0x01c71f41,/* Pin Complex */0x01d71c01,0x01d71dc6,0x01d71e14,0x01d71f40,/* Pin Complex */0x01e71cf0,0x01e71d11,0x01e71e11,0x01e71f41,/* Pin Complex */0x01f71cf0,0x01f71d11,0x01f71e11,0x01f71f41,+};
+/*
- This needs to be in ROM since if we put it in CAR, FSP init loses it
when
- it drops CAR.
- VerbTable: (RealTek ALC262)
- Revision ID = 0xFF, support all steps
- Codec Verb Table For AZALIA
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
- */
+static const struct azalia_verb_table azalia_verb_table[] = {
{{0x10ec0262,0x0000,0xff,0x01,0x000b,0x0002,},verb_table_data13}+};
+static const struct azalia_config azalia_config = {
.pme_enable = 1,.docking_supported = 1,.docking_attached = 0,.hdmi_codec_enable = 1,.azalia_v_ci_enable = 1,.rsvdbits = 0,.verb_table_num = 1,.verb_table = azalia_verb_table,.reset_wait_timer_ms = 300+};
+void update_fsp_azalia_configs(const struct azalia_config **azalia) +{
*azalia = &azalia_config;+} int board_early_init_f(void) {
Reviewed-by: Stefan Roese sr@denx.de
applied to u-boot-x86, thanks!
On 13.10.2017 10:30, Bin Meng wrote:
So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic.
This also corrects reset_wait_timer from us to ms.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 13 ++++---- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 ------------------------ arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 26 ---------------- arch/x86/include/asm/fsp/fsp_azalia.h | 39 ++++++++++++++++++++++++ arch/x86/include/asm/fsp/fsp_support.h | 1 + 5 files changed, 46 insertions(+), 72 deletions(-) delete mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 45f9bf9..926f26b 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -8,13 +8,12 @@
#include <common.h> #include <fdtdec.h> -#include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
/* ALC262 Verb Table - 10EC0262 */ -static const uint32_t verb_table_data13[] = { +static const u32 verb_table_data13[] = { /* Pin Complex (NID 0x11) */ 0x01171cf0, 0x01171d11, @@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = {
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
*/ -static const struct pch_azalia_verb_table azalia_verb_table[] = { +static const struct azalia_verb_table azalia_verb_table[] = { { { 0x10ec0262, @@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table azalia_verb_table[] = { } };
-const struct pch_azalia_config azalia_config = { +const struct azalia_config azalia_config = { .pme_enable = 1, .docking_supported = 1, .docking_attached = 0, .hdmi_codec_enable = 1, .azalia_v_ci_enable = 1, .rsvdbits = 0,
- .azalia_verb_table_num = 1,
- .azalia_verb_table = azalia_verb_table,
- .reset_wait_timer_us = 300
.verb_table_num = 1,
.verb_table = azalia_verb_table,
.reset_wait_timer_ms = 300 };
/**
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h deleted file mode 100644 index d96a20f..0000000 --- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h +++ /dev/null @@ -1,39 +0,0 @@ -/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2015 Google, Inc
- SPDX-License-Identifier: Intel
- */
-#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_
-struct __packed pch_azalia_verb_table_header {
- uint32_t vendor_device_id;
- uint16_t sub_system_id;
- uint8_t revision_id; /* 0xff applies to all steppings */
- uint8_t front_panel_support;
- uint16_t number_of_rear_jacks;
- uint16_t number_of_front_jacks;
-};
-struct __packed pch_azalia_verb_table {
- struct pch_azalia_verb_table_header verb_table_header;
- const uint32_t *verb_table_data;
-};
-struct __packed pch_azalia_config {
- uint8_t pme_enable:1;
- uint8_t docking_supported:1;
- uint8_t docking_attached:1;
- uint8_t hdmi_codec_enable:1;
- uint8_t azalia_v_ci_enable:1;
- uint8_t rsvdbits:3;
- /* number of verb tables provided by platform */
- uint8_t azalia_verb_table_num;
- const struct pch_azalia_verb_table *azalia_verb_table;
- /* delay timer after azalia reset */
- uint16_t reset_wait_timer_us;
-};
-#endif diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h index ecb01fa..99c4c0a 100644 --- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h @@ -29,32 +29,6 @@ struct __packed memory_upd { u8 reserved[189]; /* Offset 0x0043 */ };
-struct __packed azalia_verb_table_header {
- u32 vendor_device_id;
- u16 sub_system_id;
- u8 revision_id;
- u8 front_panel_support;
- u16 number_of_rear_jacks;
- u16 number_of_front_jacks;
-};
-struct __packed azalia_verb_table {
- struct azalia_verb_table_header header;
- u32 *data;
-};
-struct __packed azalia_config {
- u8 pme_enable:1;
- u8 docking_supported:1;
- u8 docking_attached:1;
- u8 hdmi_codec_enable:1;
- u8 azalia_v_ci_enable:1;
- u8 reserved:3;
- u8 verb_table_num;
- struct azalia_verb_table *verb_table;
- u16 reset_wait_timer_ms;
-};
- struct gpio_family { u32 confg; u32 confg_changes;
diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h new file mode 100644 index 0000000..a1467bf --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_azalia.h @@ -0,0 +1,39 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2015, Google, Inc
- SPDX-License-Identifier: Intel
- */
+#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_
+struct __packed azalia_verb_table_header {
- u32 vendor_device_id;
- u16 sub_system_id;
- u8 revision_id; /* 0xff applies to all steppings */
- u8 front_panel_support;
- u16 number_of_rear_jacks;
- u16 number_of_front_jacks;
+};
+struct __packed azalia_verb_table {
- struct azalia_verb_table_header header;
- const u32 *data;
+};
+struct __packed azalia_config {
- u8 pme_enable:1;
- u8 docking_supported:1;
- u8 docking_attached:1;
- u8 hdmi_codec_enable:1;
- u8 azalia_v_ci_enable:1;
- u8 rsvdbits:3;
- /* number of verb tables provided by platform */
- u8 verb_table_num;
- const struct azalia_verb_table *verb_table;
- /* delay timer after azalia reset */
- u16 reset_wait_timer_ms;
+};
+#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 97a50b0..df3add0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -15,6 +15,7 @@ #include "fsp_hob.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" +#include "fsp_azalia.h" #include <asm/arch/fsp/fsp_vpd.h> #include <asm/arch/fsp/fsp_configs.h>
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
On Fri, Oct 13, 2017 at 7:14 PM, Stefan Roese sr@denx.de wrote:
On 13.10.2017 10:30, Bin Meng wrote:
So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic.
This also corrects reset_wait_timer from us to ms.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/fsp_configs.c | 13 ++++---- arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39
arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 26 ---------------- arch/x86/include/asm/fsp/fsp_azalia.h | 39 ++++++++++++++++++++++++ arch/x86/include/asm/fsp/fsp_support.h | 1 + 5 files changed, 46 insertions(+), 72 deletions(-) delete mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 45f9bf9..926f26b 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -8,13 +8,12 @@ #include <common.h> #include <fdtdec.h> -#include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h> DECLARE_GLOBAL_DATA_PTR; /* ALC262 Verb Table - 10EC0262 */ -static const uint32_t verb_table_data13[] = { +static const u32 verb_table_data13[] = { /* Pin Complex (NID 0x11) */ 0x01171cf0, 0x01171d11, @@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = {
- Codec Address: CAd value (0/1/2)
- Codec Vendor: 0x10EC0262
*/ -static const struct pch_azalia_verb_table azalia_verb_table[] = { +static const struct azalia_verb_table azalia_verb_table[] = { { { 0x10ec0262, @@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table azalia_verb_table[] = { } }; -const struct pch_azalia_config azalia_config = { +const struct azalia_config azalia_config = { .pme_enable = 1, .docking_supported = 1, .docking_attached = 0, .hdmi_codec_enable = 1, .azalia_v_ci_enable = 1, .rsvdbits = 0,
.azalia_verb_table_num = 1,.azalia_verb_table = azalia_verb_table,.reset_wait_timer_us = 300
.verb_table_num = 1,.verb_table = azalia_verb_table,.reset_wait_timer_ms = 300diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h deleted file mode 100644 index d96a20f..0000000 --- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h +++ /dev/null @@ -1,39 +0,0 @@ -/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2015 Google, Inc
- SPDX-License-Identifier: Intel
- */
-#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_
-struct __packed pch_azalia_verb_table_header {
uint32_t vendor_device_id;uint16_t sub_system_id;uint8_t revision_id; /* 0xff applies to all steppings*/
uint8_t front_panel_support;uint16_t number_of_rear_jacks;uint16_t number_of_front_jacks;-};
-struct __packed pch_azalia_verb_table {
struct pch_azalia_verb_table_header verb_table_header;const uint32_t *verb_table_data;-};
-struct __packed pch_azalia_config {
uint8_t pme_enable:1;uint8_t docking_supported:1;uint8_t docking_attached:1;uint8_t hdmi_codec_enable:1;uint8_t azalia_v_ci_enable:1;uint8_t rsvdbits:3;/* number of verb tables provided by platform */uint8_t azalia_verb_table_num;const struct pch_azalia_verb_table *azalia_verb_table;/* delay timer after azalia reset */uint16_t reset_wait_timer_us;-};
-#endif diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h index ecb01fa..99c4c0a 100644 --- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h @@ -29,32 +29,6 @@ struct __packed memory_upd { u8 reserved[189]; /* Offset 0x0043 */ }; -struct __packed azalia_verb_table_header {
u32 vendor_device_id;u16 sub_system_id;u8 revision_id;u8 front_panel_support;u16 number_of_rear_jacks;u16 number_of_front_jacks;-};
-struct __packed azalia_verb_table {
struct azalia_verb_table_header header;u32 *data;-};
-struct __packed azalia_config {
u8 pme_enable:1;u8 docking_supported:1;u8 docking_attached:1;u8 hdmi_codec_enable:1;u8 azalia_v_ci_enable:1;u8 reserved:3;u8 verb_table_num;struct azalia_verb_table *verb_table;u16 reset_wait_timer_ms;-};
- struct gpio_family { u32 confg; u32 confg_changes;
diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h new file mode 100644 index 0000000..a1467bf --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_azalia.h @@ -0,0 +1,39 @@ +/*
- Copyright (C) 2013, Intel Corporation
- Copyright (C) 2015, Google, Inc
- SPDX-License-Identifier: Intel
- */
+#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_
+struct __packed azalia_verb_table_header {
u32 vendor_device_id;u16 sub_system_id;u8 revision_id; /* 0xff applies to all steppings */u8 front_panel_support;u16 number_of_rear_jacks;u16 number_of_front_jacks;+};
+struct __packed azalia_verb_table {
struct azalia_verb_table_header header;const u32 *data;+};
+struct __packed azalia_config {
u8 pme_enable:1;u8 docking_supported:1;u8 docking_attached:1;u8 hdmi_codec_enable:1;u8 azalia_v_ci_enable:1;u8 rsvdbits:3;/* number of verb tables provided by platform */u8 verb_table_num;const struct azalia_verb_table *verb_table;/* delay timer after azalia reset */u16 reset_wait_timer_ms;+};
+#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 97a50b0..df3add0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -15,6 +15,7 @@ #include "fsp_hob.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" +#include "fsp_azalia.h" #include <asm/arch/fsp/fsp_vpd.h> #include <asm/arch/fsp/fsp_configs.h>
Reviewed-by: Stefan Roese sr@denx.de
applied to u-boot-x86, thanks!
participants (2)
-
Bin Meng -
Stefan Roese