[U-Boot] [PATCH 0/5] i.MX7ULP EVK: update ddr script to make board boot
This patchset is to upstream ddr script from NXP vendor tree, witout this patchset, the ULP B0 EVK board could not boot up.
Ye Li (5): mx7ulp: Fix APLL num and denom setting issue mx7ulp_evk: Update LPDDR3 script mx7ulp_evk: Change APLL and its PFD0 frequencies mx7ulp: Select the SCG1 APLL PFD as a system clock source mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0
board/freescale/mx7ulp_evk/imximage.cfg | 17 ++++++----------- board/freescale/mx7ulp_evk/plugin.S | 23 ++++++++--------------- 2 files changed, 14 insertions(+), 26 deletions(-)
From: Ye Li ye.li@nxp.com
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule.
Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/imximage.cfg | 6 ------ board/freescale/mx7ulp_evk/plugin.S | 19 +------------------ 2 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index a6e18d9440..78df69f40e 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -43,13 +43,7 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x403f00dc 0x00000000 DATA 4 0x403e0040 0x01000020 -DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e0508 0x00140000 -DATA 4 0x403E0510 0x00000004 -DATA 4 0x403E0514 0x00000002 -DATA 4 0x403e0500 0x00000001 -CHECK_BITS_SET 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x8080801E CHECK_BITS_SET 4 0x403e050c 0x00000040 DATA 4 0x403E0030 0x00000001 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 082b2beaa3..802ae5f49a 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -13,26 +13,9 @@ ldr r2, =0x403e0000 ldr r3, =0x01000020 str r3, [r2, #0x40] - ldr r3, =0x01000000 - str r3, [r2, #0x500] + ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00140000 - str r3, [r2, #0x508] - ldr r3, =0x00000004 - str r3, [r2, #0x510] - ldr r3, =0x00000002 - str r3, [r2, #0x514] - ldr r3, =0x00000001 - str r3, [r2, #0x500] - - ldr r3, =0x01000000 -wait1: - ldr r4, [r2, #0x500] - and r4, r3 - cmp r4, r3 - bne wait1 - ldr r3, =0x8080801E str r3, [r2, #0x50c]
From: Ye Li ye.li@nxp.com
Update LPDDR3 script with the changes below: -Update the precharge command to CMD=01 at the DDR initialization phase -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn
Test: One EVK board passes overnight stress test.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/imximage.cfg | 9 ++------- board/freescale/mx7ulp_evk/plugin.S | 13 ++----------- 2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index 78df69f40e..e7d87beb5f 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -88,11 +88,6 @@ DATA 4 0x40AB0820 0x33333333 DATA 4 0x40AB0824 0x33333333 DATA 4 0x40AB0828 0x33333333
-DATA 4 0x40AB082C 0xf3333333 -DATA 4 0x40AB0830 0xf3333333 -DATA 4 0x40AB0834 0xf3333333 -DATA 4 0x40AB0838 0xf3333333 - DATA 4 0x40AB08C0 0x24922492 DATA 4 0x40AB08B8 0x00000800
@@ -107,8 +102,8 @@ DATA 4 0x40AB0030 0x009F0E10 DATA 4 0x40AB0040 0x0000003F DATA 4 0x40AB0000 0xC3190000
-DATA 4 0x40AB001C 0x00008050 -DATA 4 0x40AB001C 0x00008058 +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 DATA 4 0x40AB001C 0x003F8030 DATA 4 0x40AB001C 0x003F8038 DATA 4 0x40AB001C 0xFF0A8030 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 802ae5f49a..73636c679f 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -115,15 +115,6 @@ wait2: ldr r1, =0x33333333 str r1, [r0, #0x828]
- ldr r1, =0xf3333333 - str r1, [r0, #0x82c] - ldr r1, =0xf3333333 - str r1, [r0, #0x830] - ldr r1, =0xf3333333 - str r1, [r0, #0x834] - ldr r1, =0xf3333333 - str r1, [r0, #0x838] - ldr r1, =0x24922492 str r1, [r0, #0x8c0] ldr r1, =0x00000800 @@ -151,9 +142,9 @@ wait2: ldr r1, =0xC3190000 str r1, [r0, #0x0]
- ldr r1, =0x00008050 + ldr r1, =0x00008010 str r1, [r0, #0x1c] - ldr r1, =0x00008058 + ldr r1, =0x00008018 str r1, [r0, #0x1c] ldr r1, =0x003F8030 str r1, [r0, #0x1c]
From: Ye Li ye.li@nxp.com
To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate.
The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.
Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings:
PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5
Signed-off-by: Ye Li ye.li@nxp.com Tested-by: Fancy Fang chen.fang@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/imximage.cfg | 8 +++++++- board/freescale/mx7ulp_evk/plugin.S | 20 +++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index e7d87beb5f..d4f6c3c62d 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -43,8 +43,14 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x403f00dc 0x00000000 DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e050c 0x8080801E +DATA 4 0x403e0508 0x00160000 +DATA 4 0x403E0510 0x00000002 +DATA 4 0x403E0514 0x00000005 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808020 CHECK_BITS_SET 4 0x403e050c 0x00000040 DATA 4 0x403E0030 0x00000001 DATA 4 0x403e0040 0x11000020 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 73636c679f..ccd2fc03a4 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -13,10 +13,28 @@ ldr r2, =0x403e0000 ldr r3, =0x01000020 str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500]
ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x8080801E + ldr r3, =0x00160000 + str r3, [r2, #0x508] + ldr r3, =0x00000002 + str r3, [r2, #0x510] + ldr r3, =0x00000005 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x80808020 str r3, [r2, #0x50c]
ldr r3, =0x00000040
From: Ye Li ye.li@nxp.com
Due to the APLL out glitch issue, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design.
Signed-off-by: Ye Li ye.li@nxp.com Acked-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/imximage.cfg | 2 +- board/freescale/mx7ulp_evk/plugin.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index d4f6c3c62d..6bc7c199f5 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -45,7 +45,7 @@ DATA 4 0x403f00dc 0x00000000 DATA 4 0x403e0040 0x01000020 DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e0508 0x00160000 +DATA 4 0x403e0508 0x00160002 DATA 4 0x403E0510 0x00000002 DATA 4 0x403E0514 0x00000005 DATA 4 0x403e0500 0x00000001 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index ccd2fc03a4..55dfecc751 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -18,7 +18,7 @@
ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00160000 + ldr r3, =0x00160002 str r3, [r2, #0x508] ldr r3, =0x00000002 str r3, [r2, #0x510]
From: Ye Li ye.li@nxp.com
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz. We update DDR clock relevant settings to approach the target. But since the limitation on LCDIF pix clock for HDMI output (refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:
APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock
To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept, so the divider 14 is calculated as: 14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)
NIC0_DIV: 1 NIC1_DIV: 0 LCDIF_PCC_DIV: 6
APLL and APLL PFD0 settings:
PFD0 FRAC: 27 APLL MULT: 22 APLL NUM: 1 APLL DENOM: 20
This patch applies the new settings for both DCD and plugin. There is no DDR script change on this new frequency. Overnight memtester is passed.
Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com --- board/freescale/mx7ulp_evk/imximage.cfg | 6 +++--- board/freescale/mx7ulp_evk/plugin.S | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index 6bc7c199f5..43ebc23091 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -46,11 +46,11 @@ DATA 4 0x403e0040 0x01000020 DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 DATA 4 0x403e0508 0x00160002 -DATA 4 0x403E0510 0x00000002 -DATA 4 0x403E0514 0x00000005 +DATA 4 0x403E0510 0x00000001 +DATA 4 0x403E0514 0x00000014 DATA 4 0x403e0500 0x00000001 CHECK_BITS_SET 4 0x403e0500 0x01000000 -DATA 4 0x403e050c 0x80808020 +DATA 4 0x403e050c 0x8080801B CHECK_BITS_SET 4 0x403e050c 0x00000040 DATA 4 0x403E0030 0x00000001 DATA 4 0x403e0040 0x11000020 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 55dfecc751..2cc93dbdd5 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */
#include <config.h> @@ -20,9 +21,9 @@ str r3, [r2, #0x50c] ldr r3, =0x00160002 str r3, [r2, #0x508] - ldr r3, =0x00000002 + ldr r3, =0x00000001 str r3, [r2, #0x510] - ldr r3, =0x00000005 + ldr r3, =0x00000014 str r3, [r2, #0x514] ldr r3, =0x00000001 str r3, [r2, #0x500] @@ -34,7 +35,7 @@ wait1: cmp r4, r3 bne wait1
- ldr r3, =0x80808020 + ldr r3, =0x8080801B str r3, [r2, #0x50c]
ldr r3, =0x00000040
Hi Peng and Ye Li,
On Wed, May 15, 2019 at 6:56 AM Peng Fan peng.fan@nxp.com wrote:
This patchset is to upstream ddr script from NXP vendor tree, witout this patchset, the ULP B0 EVK board could not boot up.
Ye Li (5): mx7ulp: Fix APLL num and denom setting issue mx7ulp_evk: Update LPDDR3 script mx7ulp_evk: Change APLL and its PFD0 frequencies mx7ulp: Select the SCG1 APLL PFD as a system clock source mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0
This series fixes the boot issue on a mx7ulp evk board with B0 silicon:
Tested-by: Fabio Estevam festevam@gmail.com
Stefano,
Could you please consider it for 2019.10 inclusion?
Thanks
participants (2)
-
Fabio Estevam -
Peng Fan