[PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates

William Zhang

2 May 2023 2 May '23

8:58 p.m.

This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

[1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zhang@broadcom.c...

Changes in v2: - Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

-- 2.37.3

Show replies by date

William Zhang

2 May 2 May

8:58 p.m.

New subject: [PATCH v2 1/9] dt-bindings: spi: Add bcm63xx-hsspi controller support

Bring the device tree binding document from Linux to u-boot

Port from linux patches: Link: https://lore.kernel.org/r/20230207065826.285013-2-william.zhang@broadcom.com Link: https://lore.kernel.org/r/20230207065826.285013-3-william.zhang@broadcom.com

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

.../spi/brcm,bcm63xx-hsspi.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml

diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml new file mode 100644 index 000000000000..6554978583f8 --- /dev/null +++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC High Speed SPI controller + +maintainers: + - William Zhang william.zhang@broadcom.com + - Kursad Oney kursad.oney@broadcom.com + - Jonas Gorski jonas.gorski@gmail.com + +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0 + controller was carried over to recent ARM based chips, such as BCM63138, + BCM4908 and BCM6858. The old MIPS based chip should continue to use the + brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to + use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as + defined below to match the specific chip along with ip revision info. + + This rev 1.0 controller has a limitation that can not keep the chip select line + active between the SPI transfers within the same SPI message. This can + terminate the transaction to some SPI devices prematurely. The issue can be + worked around by either the controller's prepend mode or using the dummy chip + select workaround. Driver automatically picks the suitable mode based on + transfer type so it is transparent to the user. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller rev 1.1 that add the capability to allow the driver to control chip + select explicitly. This solves the issue in the old controller. + +properties: + compatible: + oneOf: + - const: brcm,bcm6328-hsspi + - items: + - enum: + - brcm,bcm47622-hsspi + - brcm,bcm4908-hsspi + - brcm,bcm63138-hsspi + - brcm,bcm63146-hsspi + - brcm,bcm63148-hsspi + - brcm,bcm63158-hsspi + - brcm,bcm63178-hsspi + - brcm,bcm6846-hsspi + - brcm,bcm6856-hsspi + - brcm,bcm6858-hsspi + - brcm,bcm6878-hsspi + - const: brcm,bcmbca-hsspi-v1.0 + - items: + - enum: + - brcm,bcm4912-hsspi + - brcm,bcm6756-hsspi + - brcm,bcm6813-hsspi + - brcm,bcm6855-hsspi + - const: brcm,bcmbca-hsspi-v1.1 + + reg: + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl + minItems: 1 + + clocks: + items: + - description: SPI master reference clock + - description: SPI master pll clock + + clock-names: + items: + - const: hsspi + - const: pll + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi-v1.0 + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + required: + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi@ff801000 { + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + };

-- 2.37.3

William Zhang

8:58 p.m.

New subject: [PATCH v2 2/9] ARM: dts: broadcom: bcmbca: Add spi controller node

Add support for HSSPI controller in ARMv7 chip dts files.

Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-4-william.zhang@broadcom.com

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

arch/arm/dts/bcm47622.dtsi | 18 ++++++++++++++++++ arch/arm/dts/bcm63138.dtsi | 18 ++++++++++++++++++ arch/arm/dts/bcm63148.dtsi | 18 ++++++++++++++++++ arch/arm/dts/bcm63178.dtsi | 19 +++++++++++++++++++ arch/arm/dts/bcm6756.dtsi | 19 +++++++++++++++++++ arch/arm/dts/bcm6846.dtsi | 18 ++++++++++++++++++ arch/arm/dts/bcm6855.dtsi | 27 +++++++++++++++++++-------- arch/arm/dts/bcm6878.dtsi | 19 +++++++++++++++++++ arch/arm/dts/bcm947622.dts | 4 ++++ arch/arm/dts/bcm963138.dts | 4 ++++ arch/arm/dts/bcm963148.dts | 4 ++++ arch/arm/dts/bcm963178.dts | 4 ++++ arch/arm/dts/bcm96756.dts | 4 ++++ arch/arm/dts/bcm96846.dts | 4 ++++ arch/arm/dts/bcm96855.dts | 4 ++++ arch/arm/dts/bcm96878.dts | 4 ++++ 16 files changed, 180 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi index c016e12b7372..86b1dff65aca 100644 --- a/arch/arm/dts/bcm47622.dtsi +++ b/arch/arm/dts/bcm47622.dtsi @@ -83,6 +83,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -114,6 +120,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi index 42b442aec9f4..2a673c39ba68 100644 --- a/arch/arm/dts/bcm63138.dtsi +++ b/arch/arm/dts/bcm63138.dtsi @@ -60,6 +60,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

/* ARM bus */ @@ -145,5 +151,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi index df5307b6b3af..d9aed2bd7ff0 100644 --- a/arch/arm/dts/bcm63148.dtsi +++ b/arch/arm/dts/bcm63148.dtsi @@ -59,6 +59,12 @@ #clock-cells = <0>; clock-frequency = <50000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

psci { @@ -99,5 +105,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi index cbd094dde6d0..4c94d62e1a21 100644 --- a/arch/arm/dts/bcm63178.dtsi +++ b/arch/arm/dts/bcm63178.dtsi @@ -70,6 +70,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -77,6 +78,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -108,6 +115,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm6756.dtsi b/arch/arm/dts/bcm6756.dtsi index ce1b59faf800..cfabd22b0251 100644 --- a/arch/arm/dts/bcm6756.dtsi +++ b/arch/arm/dts/bcm6756.dtsi @@ -87,6 +87,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -118,6 +124,19 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi index 8aa47a2583b2..05e5870474b0 100644 --- a/arch/arm/dts/bcm6846.dtsi +++ b/arch/arm/dts/bcm6846.dtsi @@ -60,6 +60,12 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

psci { @@ -99,5 +105,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi index 10c003a57c95..59680a9aa2f5 100644 --- a/arch/arm/dts/bcm6855.dtsi +++ b/arch/arm/dts/bcm6855.dtsi @@ -81,14 +81,6 @@ clock-mult = <1>; };

- hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - wdt_clk: wdt-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -96,6 +88,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -128,6 +126,19 @@ ranges = <0 0xff800000 0x800000>; bootph-all;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm6878.dtsi b/arch/arm/dts/bcm6878.dtsi index 1e8b5fa96c25..ab08d2662162 100644 --- a/arch/arm/dts/bcm6878.dtsi +++ b/arch/arm/dts/bcm6878.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -67,6 +68,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -99,6 +106,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts index 6f083724ab8e..93b8ce22678d 100644 --- a/arch/arm/dts/bcm947622.dts +++ b/arch/arm/dts/bcm947622.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963138.dts b/arch/arm/dts/bcm963138.dts index 6158a8733554..b3c57e6efc25 100644 --- a/arch/arm/dts/bcm963138.dts +++ b/arch/arm/dts/bcm963138.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963148.dts b/arch/arm/dts/bcm963148.dts index 98f6a6d09f50..1f5d6d783f09 100644 --- a/arch/arm/dts/bcm963148.dts +++ b/arch/arm/dts/bcm963148.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts index fa096e9cde23..d036e99dd8d1 100644 --- a/arch/arm/dts/bcm963178.dts +++ b/arch/arm/dts/bcm963178.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts index 9a4a87ba9c8a..8b104f3fb14a 100644 --- a/arch/arm/dts/bcm96756.dts +++ b/arch/arm/dts/bcm96756.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts index c70ebccabc19..55852c229608 100644 --- a/arch/arm/dts/bcm96846.dts +++ b/arch/arm/dts/bcm96846.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts index e4e740c73e97..cac2a40ef5c1 100644 --- a/arch/arm/dts/bcm96855.dts +++ b/arch/arm/dts/bcm96855.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts index 8fbc175cb452..b7af8ade7a9d 100644 --- a/arch/arm/dts/bcm96878.dts +++ b/arch/arm/dts/bcm96878.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +};

-- 2.37.3

William Zhang

8:58 p.m.

New subject: [PATCH v2 3/9] arm64: dts: broadcom: bcmbca: Add spi controller node

Add support for HSSPI controller in ARMv8 chip dts files.

Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

arch/arm/dts/bcm4908.dtsi | 17 +++++++++++++++++ arch/arm/dts/bcm4912.dtsi | 20 ++++++++++++++++++++ arch/arm/dts/bcm63146.dtsi | 19 +++++++++++++++++++ arch/arm/dts/bcm63158.dtsi | 15 ++++++--------- arch/arm/dts/bcm6813.dtsi | 20 ++++++++++++++++++++ arch/arm/dts/bcm6856.dtsi | 23 ++++++++++------------- arch/arm/dts/bcm6858.dtsi | 23 ++++++++++------------- arch/arm/dts/bcm94908.dts | 4 ++++ arch/arm/dts/bcm94912.dts | 4 ++++ arch/arm/dts/bcm963146.dts | 4 ++++ arch/arm/dts/bcm963158.dts | 4 ++++ arch/arm/dts/bcm96813.dts | 4 ++++ arch/arm/dts/bcm96856.dts | 4 ++++ arch/arm/dts/bcm96858.dts | 4 ++++ 14 files changed, 130 insertions(+), 35 deletions(-)

diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi index 0be5cfeeffa9..fc9874623b18 100644 --- a/arch/arm/dts/bcm4908.dtsi +++ b/arch/arm/dts/bcm4908.dtsi @@ -106,6 +106,12 @@ clock-frequency = <50000000>; clock-output-names = "periph"; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

bus@ff800000 { @@ -123,5 +129,16 @@ status = "disabled"; };

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi index 3d016c2ce675..b10a0ae06187 100644 --- a/arch/arm/dts/bcm4912.dtsi +++ b/arch/arm/dts/bcm4912.dtsi @@ -78,6 +78,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -85,6 +86,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -116,6 +123,19 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi index 04de96bd0a03..48226cf1a7d4 100644 --- a/arch/arm/dts/bcm63146.dtsi +++ b/arch/arm/dts/bcm63146.dtsi @@ -59,6 +59,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -66,6 +67,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -98,6 +105,18 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 4bed1f914a9b..ffb824fe600d 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -82,11 +82,9 @@ };

hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; + clock-frequency = <400000000>; };

uart_clk: uart-clk { @@ -249,16 +247,15 @@ status = "disabled"; };

- hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; + compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0"; reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; num-cs = <8>; - status = "disabled"; };

diff --git a/arch/arm/dts/bcm6813.dtsi b/arch/arm/dts/bcm6813.dtsi index c3e6197be808..eaa5ee889f51 100644 --- a/arch/arm/dts/bcm6813.dtsi +++ b/arch/arm/dts/bcm6813.dtsi @@ -78,6 +78,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -85,6 +86,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; };

psci { @@ -116,6 +123,19 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>;

+ hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi index 38c88f8399bb..245a7d65cf1b 100644 --- a/arch/arm/dts/bcm6856.dtsi +++ b/arch/arm/dts/bcm6856.dtsi @@ -63,14 +63,6 @@ clock-frequency = <200000000>; };

- hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - wdt_clk: wdt-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -78,6 +70,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

psci { @@ -224,16 +222,15 @@ status = "disabled"; };

- hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; + compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0"; reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; num-cs = <8>; - status = "disabled"; };

diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index dc95047a2659..ba30f70f1a9b 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -82,14 +82,6 @@ clock-frequency = <200000000>; };

- hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - wdt_clk: wdt-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -97,6 +89,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; };

psci { @@ -243,16 +241,15 @@ status = "disabled"; };

- hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; + compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0"; reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; num-cs = <8>; - status = "disabled"; };

diff --git a/arch/arm/dts/bcm94908.dts b/arch/arm/dts/bcm94908.dts index fcbd3c430ace..c4e6e71f6310 100644 --- a/arch/arm/dts/bcm94908.dts +++ b/arch/arm/dts/bcm94908.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts index a3623e6f6919..e69cd683211a 100644 --- a/arch/arm/dts/bcm94912.dts +++ b/arch/arm/dts/bcm94912.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts index e39f1e6d4774..db2c82d6dfd8 100644 --- a/arch/arm/dts/bcm963146.dts +++ b/arch/arm/dts/bcm963146.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index eba07e0b1ca6..25c12bc63545 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96813.dts b/arch/arm/dts/bcm96813.dts index af17091ae764..faba21f03120 100644 --- a/arch/arm/dts/bcm96813.dts +++ b/arch/arm/dts/bcm96813.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts index 032aeb75c983..9808331eede2 100644 --- a/arch/arm/dts/bcm96856.dts +++ b/arch/arm/dts/bcm96856.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts index 0cbf582f5d54..1f561c8e13b0 100644 --- a/arch/arm/dts/bcm96858.dts +++ b/arch/arm/dts/bcm96858.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +};

-- 2.37.3

William Zhang

8:58 p.m.

New subject: [PATCH v2 4/9] spi: bcm63xx-hsspi: Enable SPI drivers by default

SPI controller is always presented in BCMBCA platform SoCs so enable the controller driver and SPI core by default.

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

arch/arm/Kconfig | 2 ++ arch/arm/mach-bcmbca/Kconfig | 11 +++++++++++ drivers/spi/Kconfig | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e225419..4aa91282f649 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -650,6 +650,8 @@ config ARCH_BCMSTB config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM + select DM_SPI + select SPI select OF_CONTROL imply CMD_DM

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 62b371612b6a..6441ed5929d2 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -11,6 +11,7 @@ config BCM47622 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI

config BCM4908 bool "Support for Broadcom 4908 Family" @@ -18,6 +19,7 @@ config BCM4908 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI

config BCM4912 bool "Support for Broadcom 4912 Family" @@ -33,6 +35,7 @@ config BCM63138 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI

config BCM63146 bool "Support for Broadcom 63146 Family" @@ -40,6 +43,7 @@ config BCM63146 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI

config BCM63148 bool "Support for Broadcom 63148 Family" @@ -47,6 +51,7 @@ config BCM63148 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI

config BCM63158 bool "Support for Broadcom 63158 Family" @@ -54,6 +59,7 @@ config BCM63158 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI

config BCM63178 bool "Support for Broadcom 63178 Family" @@ -61,6 +67,7 @@ config BCM63178 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI

config BCM6756 bool "Support for Broadcom 6756 Family" @@ -82,6 +89,7 @@ config BCM6846 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI

config BCM6855 bool "Support for Broadcom 6855 Family" @@ -99,6 +107,7 @@ config BCM6856 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. @@ -109,6 +118,7 @@ config BCM6858 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. @@ -119,6 +129,7 @@ config BCM6878 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI

source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd26819..47a261f1e1b8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -101,9 +101,9 @@ config ATMEL_SPI

config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) + depends on (ARCH_BMIPS || ARCH_BCMBCA) help - Enable the BCM6328 HSSPI driver. This driver can be used to + Enable the BCM63XX HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom SPI core.

-- 2.37.3

William Zhang

8:58 p.m.

New subject: [PATCH v2 5/9] spi: bcm63xx-hsspi: Add new compatible string support

New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding.

Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

drivers/spi/bcm63xx_hsspi.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 4d714adc4afd..495feba02262 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -310,6 +310,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {

static const struct udevice_id bcm63xx_hsspi_ids[] = { { .compatible = "brcm,bcm6328-hsspi", }, + { .compatible = "brcm,bcmbca-hsspi-v1.0", }, { /* sentinel */ } };

-- 2.37.3

Jagan Teki

2 Jun 2 Jun

7:46 a.m.

New subject: [PATCH v2 5/9] spi: bcm63xx-hsspi: Add new compatible string support

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...

New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding.

Port from linux patch: Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com

Signed-off-by: William Zhang william.zhang@broadcom.com

Reviewed-by: Jagan Teki jagan@amarulasolutions.com

William Zhang

2 May 2 May

8:58 p.m.

New subject: [PATCH v2 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting

Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues.

This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width.

Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

drivers/spi/bcm63xx_hsspi.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 495feba02262..0d12c345b1dd 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, size_t data_bytes = bitlen / 8; size_t step_size = HSSPI_FIFO_SIZE; uint16_t opcode = 0; - uint32_t val; + uint32_t val = SPI_PFL_MODE_FILL_MASK; const uint8_t *tx = dout; uint8_t *rx = din;

@@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, step_size -= HSSPI_FIFO_OP_SIZE;

/* dual mode */ - if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || - (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) + if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || + (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { opcode |= HSSPI_FIFO_OP_MBIT_MASK;

- /* profile mode */ - val = SPI_PFL_MODE_FILL_MASK | - SPI_PFL_MODE_MDRDSZ_MASK | - SPI_PFL_MODE_MDWRSZ_MASK; + /* profile mode */ + if (plat->mode & SPI_RX_DUAL) + val |= SPI_PFL_MODE_MDRDSZ_MASK; + if (plat->mode & SPI_TX_DUAL) + val |= SPI_PFL_MODE_MDWRSZ_MASK; + } + if (plat->mode & SPI_3WIRE) val |= SPI_PFL_MODE_3WIRE_MASK; writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));

-- 2.37.3

Jagan Teki

2 Jun 2 Jun

7:47 a.m.

New subject: [PATCH v2 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...

Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues.

This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width.

Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com

Reviewed-by: Jagan Teki jagan@amarulasolutions.com

William Zhang

2 May 2 May

8:58 p.m.

New subject: [PATCH v2 7/9] spi: bcm63xx-hsspi: Add prepend mode support

Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the u-boot based on linux kernel driver. It basically picks the dummy cs as !actual_cs so typically dummy cs is 1 when most of the case only cs 0 is used in the board design. Then invert the polarity of both cs and tell the controller to start the transfers using dummy cs. Assuming both cs are active low before the inversion, effectively this keeps dummy cs high and actual cs low during the transfer and workaround the issue.

This workaround requires that dummy cs 1 pin to is set to SPI chip selection function in the pinmux when the transfer clock is above 25MHz. The old chips likely have default pinmux set to chip select on the dummy cs pin so it works but this is not case for the new Broadband BCA chips and this workaround stop working. This is specifically an issue to support SPI NAND and SPI NOR flash because these flash devices can typically run at or above 100MHz.

This patch utilizes the prepend feature of the controller to combine the multiple transfers in the same message to a single transfer when possible. This way there is no need to keep clock low between transfers and solve the issue without any pinmux requirement.

Multiple transfers within a SPI message may be combined into one transfer if the following are all true: * One or more half duplex write transfer in single bit mode * Optional full duplex read/write at the end * No delay and cs_change between transfers

Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. So this change switches to the prepend mode as the default mode. For any SPI message that does not meet the above requirement, we switch to original dummy cs mode but limit the clock rate to the safe 25MHz.

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

drivers/spi/bcm63xx_hsspi.c | 259 +++++++++++++++++++++++++++++++++--- 1 file changed, 242 insertions(+), 17 deletions(-)

diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 0d12c345b1dd..a24bb430cbb4 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -20,7 +20,13 @@

#define HSSPI_PP 0

-#define SPI_MAX_SYNC_CLOCK 30000000 +/* + * The maximum frequency for SPI synchronous mode is 30MHz for some chips and + * 25MHz for some others. This depends on the chip layout and SPI signals + * distance to the pad. We use the lower of these values to cover all relevant + * chips. + */ +#define SPI_MAX_SYNC_CLOCK 25000000

/* SPI Control register */ #define SPI_CTL_REG 0x000 @@ -72,12 +78,16 @@ #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) #define SPI_PFL_MODE_FILL_SHIFT 0 #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDST_SHIFT 8 +#define SPI_PFL_MODE_MDWRST_SHIFT 12 #define SPI_PFL_MODE_MDRDSZ_SHIFT 16 #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) #define SPI_PFL_MODE_MDWRSZ_SHIFT 18 #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) #define SPI_PFL_MODE_3WIRE_SHIFT 20 #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT) +#define SPI_PFL_MODE_PREPCNT_SHIFT 24 +#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)

/* SPI Ping-Pong FIFO registers */ #define HSSPI_FIFO_SIZE 0x200 @@ -96,12 +106,21 @@ #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)

+#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE) +#define HSSPI_MAX_PREPEND_SIZE 15 + +#define HSSPI_XFER_MODE_PREPEND 0 +#define HSSPI_XFER_MODE_DUMMYCS 1 + struct bcm63xx_hsspi_priv { void __iomem *regs; ulong clk_rate; uint8_t num_cs; uint8_t cs_pols; uint speed; + uint xfer_mode; + uint32_t prepend_cnt; + uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE]; };

static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, @@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, struct dm_spi_slave_plat *plat) { uint32_t clr, set; + uint speed = priv->speed; + + if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS && + speed > SPI_MAX_SYNC_CLOCK) { + speed = SPI_MAX_SYNC_CLOCK; + debug("Force to dummy cs mode. Reduce the speed to %dHz\n", speed); + }

/* profile clock */ - set = DIV_ROUND_UP(priv->clk_rate, priv->speed); + set = DIV_ROUND_UP(priv->clk_rate, speed); set = DIV_ROUND_UP(2048, set); set &= SPI_PFL_CLK_FREQ_MASK; set |= SPI_PFL_CLK_RSTLOOP_MASK; @@ -164,7 +190,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, set |= SPI_PFL_SIG_LATCHRIS_MASK;

/* async clk */ - if (priv->speed > SPI_MAX_SYNC_CLOCK) + if (speed > SPI_MAX_SYNC_CLOCK) set |= SPI_PFL_SIG_ASYNCIN_MASK;

clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); @@ -173,17 +199,24 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, set = 0; clr = 0;

- /* invert cs polarity */ - if (priv->cs_pols & BIT(plat->cs)) - clr |= BIT(plat->cs); - else - set |= BIT(plat->cs); - - /* invert dummy cs polarity */ - if (priv->cs_pols & BIT(!plat->cs)) - clr |= BIT(!plat->cs); - else - set |= BIT(!plat->cs); + if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) { + if (priv->cs_pols & BIT(plat->cs)) + set |= BIT(plat->cs); + else + clr |= BIT(plat->cs); + } else { + /* invert cs polarity */ + if (priv->cs_pols & BIT(plat->cs)) + clr |= BIT(plat->cs); + else + set |= BIT(plat->cs); + + /* invert dummy cs polarity */ + if (priv->cs_pols & BIT(!plat->cs)) + clr |= BIT(!plat->cs); + else + set |= BIT(!plat->cs); + }

clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); } @@ -212,13 +245,18 @@ static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) * all the time. This hack is also used in the upstream linux driver and * allows keeping CS active between transfers even if the HW doesn't give * this possibility. + * + * This workaround only works when the dummy CS (usually CS1 when the actual + * CS is 0) pinmuxed to SPI chip select function if SPI clock is faster than + * SPI_MAX_SYNC_CLOCK. In old broadcom chip, CS1 pin is default to chip select + * function. But this is not the case for new chips. To make this function + * always work, it should be called with maximum clock of SPI_MAX_SYNC_CLOCK. */ -static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_bytes, + const void *dout, void *din, unsigned long flags) { struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); - size_t data_bytes = bitlen / 8; size_t step_size = HSSPI_FIFO_SIZE; uint16_t opcode = 0; uint32_t val = SPI_PFL_MODE_FILL_MASK; @@ -304,6 +342,182 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, return 0; }

+static int bcm63xx_prepare_prepend_transfer(struct bcm63xx_hsspi_priv *priv, + unsigned int data_bytes, const void *dout, void *din, + unsigned long flags) +{ + /* + * only support multiple half duplex write transfer + optional + * full duplex read/write at the end. + */ + if (flags & SPI_XFER_BEGIN) { + /* clear prepends */ + priv->prepend_cnt = 0; + } + + if (din) { + /* buffering reads not possible for prepend mode */ + if (!(flags & SPI_XFER_END)) { + debug("unable to buffer reads\n"); + return HSSPI_XFER_MODE_DUMMYCS; + } + + /* check rx size */ + if (data_bytes > HSSPI_MAX_DATA_SIZE) { + debug("max rx bytes exceeded\n"); + return HSSPI_XFER_MODE_DUMMYCS; + } + } + + if (dout) { + /* check tx size */ + if (flags & SPI_XFER_END) { + if (priv->prepend_cnt + data_bytes > HSSPI_MAX_DATA_SIZE) { + debug("max tx bytes exceeded\n"); + return HSSPI_XFER_MODE_DUMMYCS; + } + } else { + if (priv->prepend_cnt + data_bytes > HSSPI_MAX_PREPEND_SIZE) { + debug("max prepend bytes exceeded\n"); + return HSSPI_XFER_MODE_DUMMYCS; + } + + /* + * buffer transfer data in the prepend buf in case we have to fall + * back to dummy cs mode. + */ + memcpy(&priv->prepend_buf[priv->prepend_cnt], dout, data_bytes); + priv->prepend_cnt += data_bytes; + } + } + + return HSSPI_XFER_MODE_PREPEND; +} + +static int bcm63xx_hsspi_xfer_prepend(struct udevice *dev, unsigned int data_bytes, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + uint16_t opcode = 0; + uint32_t val, offset; + int ret; + + if (flags & SPI_XFER_END) { + offset = HSSPI_FIFO_BASE + HSSPI_FIFO_OP_SIZE; + if (priv->prepend_cnt) { + /* copy prepend data */ + memcpy_toio(priv->regs + offset, + priv->prepend_buf, priv->prepend_cnt); + } + + if (dout && data_bytes) { + /* copy tx data */ + offset += priv->prepend_cnt; + memcpy_toio(priv->regs + offset, dout, data_bytes); + } + + bcm63xx_hsspi_activate_cs(priv, plat); + if (dout && !din) { + /* all half-duplex write. merge to single write */ + data_bytes += priv->prepend_cnt; + opcode = HSSPI_FIFO_OP_CODE_W; + priv->prepend_cnt = 0; + } else if (!dout && din) { + /* half-duplex read with prepend write */ + opcode = HSSPI_FIFO_OP_CODE_R; + } else { + /* full duplex read/write */ + opcode = HSSPI_FIFO_OP_READ_WRITE; + } + + /* profile mode */ + val = SPI_PFL_MODE_FILL_MASK; + if (plat->mode & SPI_3WIRE) + val |= SPI_PFL_MODE_3WIRE_MASK; + + /* dual mode */ + if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || + (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { + opcode |= HSSPI_FIFO_OP_MBIT_MASK; + + if (plat->mode & SPI_RX_DUAL) { + val |= SPI_PFL_MODE_MDRDSZ_MASK; + val |= priv->prepend_cnt << SPI_PFL_MODE_MDRDST_SHIFT; + } + if (plat->mode & SPI_TX_DUAL) { + val |= SPI_PFL_MODE_MDWRSZ_MASK; + val |= priv->prepend_cnt << SPI_PFL_MODE_MDWRST_SHIFT; + } + } + val |= (priv->prepend_cnt << SPI_PFL_MODE_PREPCNT_SHIFT); + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + + /* set fifo operation */ + val = opcode | (data_bytes & HSSPI_FIFO_OP_BYTES_MASK); + writew(cpu_to_be16(val), + priv->regs + HSSPI_FIFO_OP_REG); + + /* issue the transfer */ + val = SPI_CMD_OP_START; + val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + SPI_CMD_PFL_MASK; + val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & + SPI_CMD_SLAVE_MASK; + writel(val, priv->regs + SPI_CMD_REG); + + /* wait for completion */ + ret = wait_for_bit_32(priv->regs + SPI_STAT_REG, + SPI_STAT_SRCBUSY_MASK, false, + 1000, false); + if (ret) { + bcm63xx_hsspi_deactivate_cs(priv); + printf("spi polling timeout\n"); + return ret; + } + + /* copy rx data */ + if (din) + memcpy_fromio(din, priv->regs + HSSPI_FIFO_BASE, + data_bytes); + bcm63xx_hsspi_deactivate_cs(priv); + } + + return 0; +} + +static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); + int ret; + u32 data_bytes = bitlen >> 3; + + if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) { + priv->xfer_mode = + bcm63xx_prepare_prepend_transfer(priv, data_bytes, dout, din, flags); + } + + /* if not prependable, fall back to dummy cs mode with safe clock */ + if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS) { + /* For pending prepend data from previous transfers, send it first */ + if (priv->prepend_cnt) { + bcm63xx_hsspi_xfer_dummy_cs(dev, priv->prepend_cnt, + priv->prepend_buf, NULL, + (flags & ~SPI_XFER_END) | SPI_XFER_BEGIN); + priv->prepend_cnt = 0; + } + ret = bcm63xx_hsspi_xfer_dummy_cs(dev, data_bytes, dout, din, flags); + } else { + ret = bcm63xx_hsspi_xfer_prepend(dev, data_bytes, dout, din, flags); + } + + if (flags & SPI_XFER_END) + priv->xfer_mode = HSSPI_XFER_MODE_PREPEND; + + return ret; +} + static const struct dm_spi_ops bcm63xx_hsspi_ops = { .cs_info = bcm63xx_hsspi_cs_info, .set_mode = bcm63xx_hsspi_set_mode, @@ -321,6 +535,7 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) { struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + struct spi_slave *slave = dev_get_parent_priv(dev);

/* check cs */ if (plat->cs >= priv->num_cs) { @@ -334,6 +549,13 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) else priv->cs_pols &= ~BIT(plat->cs);

+ /* + * set the max read/write size to make sure each xfer are within the + * prepend limit + */ + slave->max_read_size = HSSPI_MAX_DATA_SIZE; + slave->max_write_size = HSSPI_MAX_DATA_SIZE; + return 0; }

@@ -395,6 +617,9 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) priv->cs_pols = readl(priv->regs + SPI_CTL_REG) & SPI_CTL_CS_POL_MASK;

+ /* default in prepend mode */ + priv->xfer_mode = HSSPI_XFER_MODE_PREPEND; + return 0; }

-- 2.37.3

William Zhang

8:58 p.m.

New subject: [PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller

The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner.

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: None

arch/arm/mach-bcmbca/Kconfig | 15 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++++++++++++++++++++++++++++++++++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI

config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI

config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI

config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI

+config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 + default y if BCM6756 + default y if BCM6855 + default y if BCM6813 + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. + source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core.

+config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index 000000000000..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski jogo@openwrt.org + * Copyright (C) 2021 Broadcom Ltd + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <spi.h> +#include <reset.h> +#include <wait_bit.h> +#include <dm.h> +#include <dm/device_compat.h> + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 30000000 + +/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010 + +#define SPI_IR_CLEAR_ALL 0xff001f1f + +/* SPI Ping-Pong Command registers */ +#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START BIT(SPI_CMD_OP_SHIFT) +#define SPI_CMD_PFL_SHIFT 8 +#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 12 +#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT) + +/* SPI Ping-Pong Status registers */ +#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) +#define SPI_STAT_SRCBUSY_SHIFT 1 +#define SPI_STAT_SRCBUSY_MASK BIT(SPI_STAT_SRCBUSY_SHIFT) + +/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK BIT(SPI_PFL_CLK_RSTLOOP_SHIFT) + +/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK BIT(SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK BIT(SPI_PFL_SIG_ASYNCIN_SHIFT) + +/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK BIT(SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK BIT(SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK BIT(SPI_PFL_MODE_3WIRE_SHIFT) + +/* SPI Ping-Pong FIFO registers */ +#define HSSPI_FIFO_SIZE 0x200 +#define HSSPI_FIFO_BASE (0x200 + \ + (HSSPI_FIFO_SIZE * HSSPI_PP)) + +/* SPI Ping-Pong FIFO OP register */ +#define HSSPI_FIFO_OP_SIZE 0x2 +#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) +#define HSSPI_FIFO_OP_BYTES_SHIFT 0 +#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) +#define HSSPI_FIFO_OP_MBIT_SHIFT 11 +#define HSSPI_FIFO_OP_MBIT_MASK BIT(HSSPI_FIFO_OP_MBIT_SHIFT) +#define HSSPI_FIFO_OP_CODE_SHIFT 13 +#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT) + +#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE) + +#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0 +#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff +#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8 +#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff + +struct bcmbca_hsspi_priv { + void __iomem *regs; + void __iomem *spim_ctrl; + u32 clk_rate; + u8 num_cs; + u8 cs_pols; + u32 speed; +}; + +static int bcmbca_hsspi_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); + + if (cs >= priv->num_cs) { + dev_err(bus, "no cs %u\n", cs); + return -EINVAL; + } + + return 0; +} + +static int bcmbca_hsspi_set_mode(struct udevice *bus, uint mode) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); + + /* clock polarity */ + if (mode & SPI_CPOL) + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + else + clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); + + return 0; +} + +static int bcmbca_hsspi_set_speed(struct udevice *bus, uint speed) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(bus); + + priv->speed = speed; + + return 0; +} + +static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv, + struct dm_spi_slave_plat *plat) +{ + u32 clr, set; + + /* profile clock */ + set = DIV_ROUND_UP(priv->clk_rate, priv->speed); + set = DIV_ROUND_UP(2048, set); + set &= SPI_PFL_CLK_FREQ_MASK; + set |= SPI_PFL_CLK_RSTLOOP_MASK; + writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); + + /* profile signal */ + set = 0; + clr = SPI_PFL_SIG_LAUNCHRIS_MASK | + SPI_PFL_SIG_LATCHRIS_MASK | + SPI_PFL_SIG_ASYNCIN_MASK; + + /* latch/launch config */ + if (plat->mode & SPI_CPHA) + set |= SPI_PFL_SIG_LAUNCHRIS_MASK; + else + set |= SPI_PFL_SIG_LATCHRIS_MASK; + + /* async clk */ + if (priv->speed > SPI_MAX_SYNC_CLOCK) + set |= SPI_PFL_SIG_ASYNCIN_MASK; + + clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); + + /* global control */ + set = 0; + clr = 0; + + if (priv->cs_pols & BIT(plat->cs)) + set |= BIT(plat->cs); + else + clr |= BIT(plat->cs); + + clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set); +} + +static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv, + struct dm_spi_slave_plat *plat) +{ + u32 val; + + /* set the override bit */ + val = readl(priv->spim_ctrl); + val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + writel(val, priv->spim_ctrl); +} + +static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv, + struct dm_spi_slave_plat *plat) +{ + u32 val; + + /* clear the cs override bit */ + val = readl(priv->spim_ctrl); + val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT); + writel(val, priv->spim_ctrl); +} + +static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + size_t data_bytes = bitlen / 8; + size_t step_size = HSSPI_FIFO_SIZE; + u16 opcode = 0; + u32 val = SPI_PFL_MODE_FILL_MASK; + const u8 *tx = dout; + u8 *rx = din; + u32 cs_act = 0; + + if (flags & SPI_XFER_BEGIN) + bcmbca_hsspi_setup_clock(priv, plat); + + /* fifo operation */ + if (tx && rx) + opcode = HSSPI_FIFO_OP_READ_WRITE; + else if (rx) + opcode = HSSPI_FIFO_OP_CODE_R; + else if (tx) + opcode = HSSPI_FIFO_OP_CODE_W; + + if (opcode != HSSPI_FIFO_OP_CODE_R) + step_size -= HSSPI_FIFO_OP_SIZE; + + /* dual mode */ + if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) || + (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) { + opcode |= HSSPI_FIFO_OP_MBIT_MASK; + + /* profile mode */ + if (plat->mode & SPI_RX_DUAL) + val |= SPI_PFL_MODE_MDRDSZ_MASK; + if (plat->mode & SPI_TX_DUAL) + val |= SPI_PFL_MODE_MDWRSZ_MASK; + } + + if (plat->mode & SPI_3WIRE) + val |= SPI_PFL_MODE_3WIRE_MASK; + writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); + + /* transfer loop */ + while (data_bytes > 0) { + size_t curr_step = min(step_size, data_bytes); + int ret; + + /* copy tx data */ + if (tx) { + memcpy_toio(priv->regs + HSSPI_FIFO_BASE + + HSSPI_FIFO_OP_SIZE, tx, curr_step); + tx += curr_step; + } + + /* set fifo operation */ + writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)), + priv->regs + HSSPI_FIFO_OP_REG); + + /* make sure we keep cs active until spi transfer is done */ + if (!cs_act) { + bcmbca_hsspi_activate_cs(priv, plat); + cs_act = 1; + } + + /* issue the transfer */ + val = SPI_CMD_OP_START; + val |= (plat->cs << SPI_CMD_PFL_SHIFT) & + SPI_CMD_PFL_MASK; + val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & + SPI_CMD_SLAVE_MASK; + writel(val, priv->regs + SPI_CMD_REG); + + /* wait for completion */ + ret = wait_for_bit_32(priv->regs + SPI_STAT_REG, + SPI_STAT_SRCBUSY_MASK, false, + 1000, false); + if (ret) { + bcmbca_hsspi_deactivate_cs(priv, plat); + dev_err(dev, "interrupt timeout\n"); + return ret; + } + + data_bytes -= curr_step; + if ((flags & SPI_XFER_END) && !data_bytes) + bcmbca_hsspi_deactivate_cs(priv, plat); + + /* copy rx data */ + if (rx) { + memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE, + curr_step); + rx += curr_step; + } + } + + return 0; +} + +static const struct dm_spi_ops bcmbca_hsspi_ops = { + .cs_info = bcmbca_hsspi_cs_info, + .set_mode = bcmbca_hsspi_set_mode, + .set_speed = bcmbca_hsspi_set_speed, + .xfer = bcmbca_hsspi_xfer, +}; + +static const struct udevice_id bcmbca_hsspi_ids[] = { + { .compatible = "brcm,bcmbca-hsspi-v1.1", }, + { /* sentinel */ } +}; + +static int bcmbca_hsspi_child_pre_probe(struct udevice *dev) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent); + struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + u32 val; + + /* check cs */ + if (plat->cs >= priv->num_cs) { + dev_err(dev, "no cs %u\n", plat->cs); + return -EINVAL; + } + + /* cs polarity */ + if (plat->mode & SPI_CS_HIGH) + priv->cs_pols |= BIT(plat->cs); + else + priv->cs_pols &= ~BIT(plat->cs); + + /* set the polarity to spim cs register */ + val = readl(priv->spim_ctrl); + val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + if (priv->cs_pols & BIT(plat->cs)) + val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT); + writel(val, priv->spim_ctrl); + + return 0; +} + +static int bcmbca_hsspi_probe(struct udevice *dev) +{ + struct bcmbca_hsspi_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + priv->regs = dev_remap_addr_name(dev, "hsspi"); + if (!priv->regs) + return -EINVAL; + + priv->spim_ctrl = dev_remap_addr_name(dev, "spim-ctrl"); + if (!priv->spim_ctrl) { + dev_err(dev, "misc spim ctrl register not defined in dts!\n"); + return -EINVAL; + } + + priv->num_cs = dev_read_u32_default(dev, "num-cs", 8); + + /* enable clock */ + ret = clk_get_by_name(dev, "hsspi", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0 && ret != -ENOSYS) + return ret; + + clk_free(&clk); + + /* get clock rate */ + ret = clk_get_by_name(dev, "pll", &clk); + if (ret < 0 && ret != -ENOSYS) + return ret; + + priv->clk_rate = clk_get_rate(&clk); + + clk_free(&clk); + + /* initialize hardware */ + writel(0, priv->regs + SPI_IR_MASK_REG); + + /* clear pending interrupts */ + writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); + + /* enable clk gate */ + setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); + + /* read default cs polarities */ + priv->cs_pols = readl(priv->regs + SPI_CTL_REG) & + SPI_CTL_CS_POL_MASK; + + dev_info(dev, "Broadcom BCMBCA HS SPI bus driver\n"); + return 0; +} + +U_BOOT_DRIVER(bcmbca_hsspi) = { + .name = "bcmbca_hsspi", + .id = UCLASS_SPI, + .of_match = bcmbca_hsspi_ids, + .ops = &bcmbca_hsspi_ops, + .priv_auto = sizeof(struct bcmbca_hsspi_priv), + .child_pre_probe = bcmbca_hsspi_child_pre_probe, + .probe = bcmbca_hsspi_probe, +};

-- 2.37.3

Jagan Teki

2 Jun 2 Jun

7:54 a.m.

New subject: [PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...

The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner.

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com

Changes in v2: None

arch/arm/mach-bcmbca/Kconfig | 15 ++

Exclude this from spi driver patch. Driver has to be a separate patch.

...

drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++++++++++++++++++++++++++++++++++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
  help
    Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway
    SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753.
@@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI

+config HAVE_SPI_CS_CTRL
  bool "SoC supports SPI chip select control"
  default y if BCM4912
  default y if BCM6756
  default y if BCM6855
  default y if BCM6813

Use ||

...

  default n
  help
    Enable this option if SoC supports SPI chip select control explicitly
    through software.
source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core.

+config BCMBCA_HSSPI
  bool "BCMBCA HSSPI driver"
  depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL
  help
    This enables support for the High Speed SPI controller present on
    newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller
    that adds the capability to allow the driver to control chip select
    explicitly.
config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index 000000000000..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com

Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
Copyright (C) 2000-2010 Broadcom Corporation
Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
Copyright (C) 2021 Broadcom Ltd
*/
+#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <spi.h> +#include <reset.h> +#include <wait_bit.h> +#include <dm.h> +#include <dm/device_compat.h>

+#define HSSPI_PP 0

+#define SPI_MAX_SYNC_CLOCK 30000000

What is this clock? spi-max-frequency ? if yes pick it from DT.

...

+/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT)

+/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010

+#define SPI_IR_CLEAR_ALL 0xff001f1f

+/* SPI Ping-Pong Command registers */ +#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START BIT(SPI_CMD_OP_SHIFT) +#define SPI_CMD_PFL_SHIFT 8 +#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 12 +#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)

+/* SPI Ping-Pong Status registers */ +#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) +#define SPI_STAT_SRCBUSY_SHIFT 1 +#define SPI_STAT_SRCBUSY_MASK BIT(SPI_STAT_SRCBUSY_SHIFT)

+/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK BIT(SPI_PFL_CLK_RSTLOOP_SHIFT)

+/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK BIT(SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK BIT(SPI_PFL_SIG_ASYNCIN_SHIFT)

+/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK BIT(SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK BIT(SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK BIT(SPI_PFL_MODE_3WIRE_SHIFT)

+/* SPI Ping-Pong FIFO registers */ +#define HSSPI_FIFO_SIZE 0x200 +#define HSSPI_FIFO_BASE (0x200 + \
                                   (HSSPI_FIFO_SIZE * HSSPI_PP))
+/* SPI Ping-Pong FIFO OP register */ +#define HSSPI_FIFO_OP_SIZE 0x2 +#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) +#define HSSPI_FIFO_OP_BYTES_SHIFT 0 +#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) +#define HSSPI_FIFO_OP_MBIT_SHIFT 11 +#define HSSPI_FIFO_OP_MBIT_MASK BIT(HSSPI_FIFO_OP_MBIT_SHIFT) +#define HSSPI_FIFO_OP_CODE_SHIFT 13 +#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)

+#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)

+#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0 +#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff +#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8 +#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff

+struct bcmbca_hsspi_priv {
  void __iomem *regs;
  void __iomem *spim_ctrl;
  u32 clk_rate;
  u8 num_cs;
  u8 cs_pols;
  u32 speed;
+};

+static int bcmbca_hsspi_cs_info(struct udevice *bus, uint cs,
                          struct spi_cs_info *info)
+{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  if (cs >= priv->num_cs) {
          dev_err(bus, "no cs %u\n", cs);
          return -EINVAL;
  }
  return 0;
+}

+static int bcmbca_hsspi_set_mode(struct udevice *bus, uint mode) +{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  /* clock polarity */
  if (mode & SPI_CPOL)
          setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  else
          clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  return 0;
+}

+static int bcmbca_hsspi_set_speed(struct udevice *bus, uint speed) +{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  priv->speed = speed;
  return 0;
+}

+static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv,
                               struct dm_spi_slave_plat *plat)
+{
  u32 clr, set;
  /* profile clock */
  set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  set = DIV_ROUND_UP(2048, set);
  set &= SPI_PFL_CLK_FREQ_MASK;
  set |= SPI_PFL_CLK_RSTLOOP_MASK;
  writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  /* profile signal */
  set = 0;
  clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
        SPI_PFL_SIG_LATCHRIS_MASK |
        SPI_PFL_SIG_ASYNCIN_MASK;
  /* latch/launch config */
  if (plat->mode & SPI_CPHA)
          set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  else
          set |= SPI_PFL_SIG_LATCHRIS_MASK;
  /* async clk */
  if (priv->speed > SPI_MAX_SYNC_CLOCK)
          set |= SPI_PFL_SIG_ASYNCIN_MASK;
  clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);

I think this won't change every time cs changes, isn't it? if so mode code has to move set_mode and the speed code has to move set_speed.

...

```
  /* global control */
```
```
  set = 0;
```
```
  clr = 0;
```
```
  if (priv->cs_pols & BIT(plat->cs))
```
```
          set |= BIT(plat->cs);
```
```
  else
```
```
          clr |= BIT(plat->cs);
```

  clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);

+static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv,

                               struct dm_spi_slave_plat *plat)

```
  u32 val;
```
```
  /* set the override bit */
```
```
  val = readl(priv->spim_ctrl);
```

  val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

+static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv,

                                 struct dm_spi_slave_plat *plat)

```
  u32 val;
```
```
  /* clear the cs override bit */
```
```
  val = readl(priv->spim_ctrl);
```

  val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

+static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen,

                       const void *dout, void *din, unsigned long flags)

  struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);

  struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);

```
  size_t data_bytes = bitlen / 8;
```
```
  size_t step_size = HSSPI_FIFO_SIZE;
```
```
  u16 opcode = 0;
```
```
  u32 val = SPI_PFL_MODE_FILL_MASK;
```
```
  const u8 *tx = dout;
```
```
  u8 *rx = din;
```
```
  u32 cs_act = 0;
```
```
  if (flags & SPI_XFER_BEGIN)
```

          bcmbca_hsspi_setup_clock(priv, plat);

```
  /* fifo operation */
```
```
  if (tx && rx)
```

          opcode = HSSPI_FIFO_OP_READ_WRITE;

```
  else if (rx)
```

          opcode = HSSPI_FIFO_OP_CODE_R;

```
  else if (tx)
```

          opcode = HSSPI_FIFO_OP_CODE_W;

```
  if (opcode != HSSPI_FIFO_OP_CODE_R)
```

          step_size -= HSSPI_FIFO_OP_SIZE;

```
  /* dual mode */
```

  if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||

      (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {

          opcode |= HSSPI_FIFO_OP_MBIT_MASK;

```
          /* profile mode */
```

          if (plat->mode & SPI_RX_DUAL)

                  val |= SPI_PFL_MODE_MDRDSZ_MASK;

          if (plat->mode & SPI_TX_DUAL)

                  val |= SPI_PFL_MODE_MDWRSZ_MASK;

```
  }
```
```
  if (plat->mode & SPI_3WIRE)
```

          val |= SPI_PFL_MODE_3WIRE_MASK;

  writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));

```
  /* transfer loop */
```
```
  while (data_bytes > 0) {
```

          size_t curr_step = min(step_size, data_bytes);

```
          int ret;
```
```
          /* copy tx data */
```
```
          if (tx) {
```

                  memcpy_toio(priv->regs + HSSPI_FIFO_BASE +

                              HSSPI_FIFO_OP_SIZE, tx, curr_step);

```
                  tx += curr_step;
```
```
          }
```
```
          /* set fifo operation */
```

          writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),

                 priv->regs + HSSPI_FIFO_OP_REG);

          /* make sure we keep cs active until spi transfer is done */

```
          if (!cs_act) {
```

                  bcmbca_hsspi_activate_cs(priv, plat);

```
                  cs_act = 1;
```
```
          }
```
```
          /* issue the transfer */
```
```
          val = SPI_CMD_OP_START;
```

          val |= (plat->cs << SPI_CMD_PFL_SHIFT) &

```
                    SPI_CMD_PFL_MASK;
```

          val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &

                    SPI_CMD_SLAVE_MASK;

          writel(val, priv->regs + SPI_CMD_REG);

```
          /* wait for completion */
```

          ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,

                                SPI_STAT_SRCBUSY_MASK, false,

                                1000, false);

```
          if (ret) {
```

                  bcmbca_hsspi_deactivate_cs(priv, plat);

                  dev_err(dev, "interrupt timeout\n");

```
                  return ret;
```
```
          }
```
```
          data_bytes -= curr_step;
```

          if ((flags & SPI_XFER_END) && !data_bytes)

                  bcmbca_hsspi_deactivate_cs(priv, plat);

```
          /* copy rx data */
```
```
          if (rx) {
```

                  memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,

                                curr_step);

```
                  rx += curr_step;
```
```
          }
```
```
  }
```
```
  return 0;
```

+static const struct dm_spi_ops bcmbca_hsspi_ops = {

```
  .cs_info = bcmbca_hsspi_cs_info,
```
```
  .set_mode = bcmbca_hsspi_set_mode,
```
```
  .set_speed = bcmbca_hsspi_set_speed,
```
```
  .xfer = bcmbca_hsspi_xfer,
```

+};

+static const struct udevice_id bcmbca_hsspi_ids[] = {

  { .compatible = "brcm,bcmbca-hsspi-v1.1", },

```
  { /* sentinel */ }
```

+};

+static int bcmbca_hsspi_child_pre_probe(struct udevice *dev) +{

  struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);

  struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);

```
  u32 val;
```
```
  /* check cs */
```
```
  if (plat->cs >= priv->num_cs) {
```

          dev_err(dev, "no cs %u\n", plat->cs);

```
          return -EINVAL;
```
```
  }
```
```
  /* cs polarity */
```
```
  if (plat->mode & SPI_CS_HIGH)
```

          priv->cs_pols |= BIT(plat->cs);

```
  else
```

          priv->cs_pols &= ~BIT(plat->cs);

  /* set the polarity to spim cs register */

```
  val = readl(priv->spim_ctrl);
```

  val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);

```
  if (priv->cs_pols & BIT(plat->cs))
```

          val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

What is this code for cannot we handle this via set_mode or xfer?

Jagan.

William Zhang

8:53 p.m.

New subject: [PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller

Hi Jagan,

On 06/01/2023 10:54 PM, Jagan Teki wrote:

...

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner.

Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.co...

Signed-off-by: William Zhang william.zhang@broadcom.com

Changes in v2: None

arch/arm/mach-bcmbca/Kconfig | 15 ++

Exclude this from spi driver patch. Driver has to be a separate patch.

Sure

...

...
drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++++++++++++++++++++++++++++++++++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c

diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM63138 bool "Support for Broadcom 63138 Family"
@@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM6813 bool "Support for Broadcom 6813 Family"
@@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
config BCM6846 bool "Support for Broadcom 6846 Family"
@@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL
  select BCMBCA_HSSPI
   help
     Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway
     SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753.
@@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI

+config HAVE_SPI_CS_CTRL
  bool "SoC supports SPI chip select control"
  default y if BCM4912
  default y if BCM6756
  default y if BCM6855
  default y if BCM6813
Use ||

Will update

...

...
  default n
  help
    Enable this option if SoC supports SPI chip select control explicitly
    through software.
source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core.

+config BCMBCA_HSSPI
  bool "BCMBCA HSSPI driver"
  depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL
  help
    This enables support for the High Speed SPI controller present on
    newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller
    that adds the capability to allow the driver to control chip select
    explicitly.
config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index 000000000000..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com

Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
Copyright (C) 2000-2010 Broadcom Corporation
Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
Copyright (C) 2021 Broadcom Ltd
*/
+#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <spi.h> +#include <reset.h> +#include <wait_bit.h> +#include <dm.h> +#include <dm/device_compat.h>

+#define HSSPI_PP 0

+#define SPI_MAX_SYNC_CLOCK 30000000
What is this clock? spi-max-frequency ? if yes pick it from DT.

Not spi-max-frequency. This is the controller internal setting that determines if controller works in sync or async mode when clock is below or above this frequency.

...

...
+/* SPI Control register */ +#define SPI_CTL_REG 0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT)

+/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG 0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG 0x010

+#define SPI_IR_CLEAR_ALL 0xff001f1f

+/* SPI Ping-Pong Command registers */ +#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START BIT(SPI_CMD_OP_SHIFT) +#define SPI_CMD_PFL_SHIFT 8 +#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 12 +#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)

+/* SPI Ping-Pong Status registers */ +#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) +#define SPI_STAT_SRCBUSY_SHIFT 1 +#define SPI_STAT_SRCBUSY_MASK BIT(SPI_STAT_SRCBUSY_SHIFT)

+/* SPI Profile Clock registers */ +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) +#define SPI_PFL_CLK_FREQ_SHIFT 0 +#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) +#define SPI_PFL_CLK_RSTLOOP_SHIFT 15 +#define SPI_PFL_CLK_RSTLOOP_MASK BIT(SPI_PFL_CLK_RSTLOOP_SHIFT)

+/* SPI Profile Signal registers */ +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12 +#define SPI_PFL_SIG_LATCHRIS_MASK BIT(SPI_PFL_SIG_LATCHRIS_SHIFT) +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 +#define SPI_PFL_SIG_LAUNCHRIS_MASK BIT(SPI_PFL_SIG_LAUNCHRIS_SHIFT) +#define SPI_PFL_SIG_ASYNCIN_SHIFT 16 +#define SPI_PFL_SIG_ASYNCIN_MASK BIT(SPI_PFL_SIG_ASYNCIN_SHIFT)

+/* SPI Profile Mode registers */ +#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) +#define SPI_PFL_MODE_FILL_SHIFT 0 +#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) +#define SPI_PFL_MODE_MDRDSZ_SHIFT 16 +#define SPI_PFL_MODE_MDRDSZ_MASK BIT(SPI_PFL_MODE_MDRDSZ_SHIFT) +#define SPI_PFL_MODE_MDWRSZ_SHIFT 18 +#define SPI_PFL_MODE_MDWRSZ_MASK BIT(SPI_PFL_MODE_MDWRSZ_SHIFT) +#define SPI_PFL_MODE_3WIRE_SHIFT 20 +#define SPI_PFL_MODE_3WIRE_MASK BIT(SPI_PFL_MODE_3WIRE_SHIFT)

+/* SPI Ping-Pong FIFO registers */ +#define HSSPI_FIFO_SIZE 0x200 +#define HSSPI_FIFO_BASE (0x200 + \
                                   (HSSPI_FIFO_SIZE * HSSPI_PP))
+/* SPI Ping-Pong FIFO OP register */ +#define HSSPI_FIFO_OP_SIZE 0x2 +#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) +#define HSSPI_FIFO_OP_BYTES_SHIFT 0 +#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) +#define HSSPI_FIFO_OP_MBIT_SHIFT 11 +#define HSSPI_FIFO_OP_MBIT_MASK BIT(HSSPI_FIFO_OP_MBIT_SHIFT) +#define HSSPI_FIFO_OP_CODE_SHIFT 13 +#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) +#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)

+#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)

+#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0 +#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff +#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8 +#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff

+struct bcmbca_hsspi_priv {
  void __iomem *regs;
  void __iomem *spim_ctrl;
  u32 clk_rate;
  u8 num_cs;
  u8 cs_pols;
  u32 speed;
+};

+static int bcmbca_hsspi_cs_info(struct udevice *bus, uint cs,
                          struct spi_cs_info *info)
+{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  if (cs >= priv->num_cs) {
          dev_err(bus, "no cs %u\n", cs);
          return -EINVAL;
  }
  return 0;
+}

+static int bcmbca_hsspi_set_mode(struct udevice *bus, uint mode) +{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  /* clock polarity */
  if (mode & SPI_CPOL)
          setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  else
          clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
  return 0;
+}

+static int bcmbca_hsspi_set_speed(struct udevice *bus, uint speed) +{
  struct bcmbca_hsspi_priv *priv = dev_get_priv(bus);
  priv->speed = speed;
  return 0;
+}

+static void bcmbca_hsspi_setup_clock(struct bcmbca_hsspi_priv *priv,
                               struct dm_spi_slave_plat *plat)
+{
  u32 clr, set;
  /* profile clock */
  set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
  set = DIV_ROUND_UP(2048, set);
  set &= SPI_PFL_CLK_FREQ_MASK;
  set |= SPI_PFL_CLK_RSTLOOP_MASK;
  writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
  /* profile signal */
  set = 0;
  clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
        SPI_PFL_SIG_LATCHRIS_MASK |
        SPI_PFL_SIG_ASYNCIN_MASK;
  /* latch/launch config */
  if (plat->mode & SPI_CPHA)
          set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
  else
          set |= SPI_PFL_SIG_LATCHRIS_MASK;
  /* async clk */
  if (priv->speed > SPI_MAX_SYNC_CLOCK)
          set |= SPI_PFL_SIG_ASYNCIN_MASK;
  clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
I think this won't change every time cs changes, isn't it? if so mode code has to move set_mode and the speed code has to move set_speed.

The controller setting will change if different spi slave select has different settings. The set_mode and set_speed code in this driver do take care some of the settings but these settings need to be applied at the beginning of the transfer. This is same as the original bcm63xx driver.

...

```
  /* global control */
```
```
  set = 0;
```
```
  clr = 0;
```
```
  if (priv->cs_pols & BIT(plat->cs))
```
```
          set |= BIT(plat->cs);
```
```
  else
```
```
          clr |= BIT(plat->cs);
```

  clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);

+static void bcmbca_hsspi_activate_cs(struct bcmbca_hsspi_priv *priv,

                               struct dm_spi_slave_plat *plat)

```
  u32 val;
```
```
  /* set the override bit */
```
```
  val = readl(priv->spim_ctrl);
```

  val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

+static void bcmbca_hsspi_deactivate_cs(struct bcmbca_hsspi_priv *priv,

                                 struct dm_spi_slave_plat *plat)

```
  u32 val;
```
```
  /* clear the cs override bit */
```
```
  val = readl(priv->spim_ctrl);
```

  val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

+static int bcmbca_hsspi_xfer(struct udevice *dev, unsigned int bitlen,

                       const void *dout, void *din, unsigned long flags)

  struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);

  struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);

```
  size_t data_bytes = bitlen / 8;
```
```
  size_t step_size = HSSPI_FIFO_SIZE;
```
```
  u16 opcode = 0;
```
```
  u32 val = SPI_PFL_MODE_FILL_MASK;
```
```
  const u8 *tx = dout;
```
```
  u8 *rx = din;
```
```
  u32 cs_act = 0;
```
```
  if (flags & SPI_XFER_BEGIN)
```

          bcmbca_hsspi_setup_clock(priv, plat);

```
  /* fifo operation */
```
```
  if (tx && rx)
```

          opcode = HSSPI_FIFO_OP_READ_WRITE;

```
  else if (rx)
```

          opcode = HSSPI_FIFO_OP_CODE_R;

```
  else if (tx)
```

          opcode = HSSPI_FIFO_OP_CODE_W;

```
  if (opcode != HSSPI_FIFO_OP_CODE_R)
```

          step_size -= HSSPI_FIFO_OP_SIZE;

```
  /* dual mode */
```

  if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||

      (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {

          opcode |= HSSPI_FIFO_OP_MBIT_MASK;

```
          /* profile mode */
```

          if (plat->mode & SPI_RX_DUAL)

                  val |= SPI_PFL_MODE_MDRDSZ_MASK;

          if (plat->mode & SPI_TX_DUAL)

                  val |= SPI_PFL_MODE_MDWRSZ_MASK;

```
  }
```
```
  if (plat->mode & SPI_3WIRE)
```

          val |= SPI_PFL_MODE_3WIRE_MASK;

  writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));

```
  /* transfer loop */
```
```
  while (data_bytes > 0) {
```

          size_t curr_step = min(step_size, data_bytes);

```
          int ret;
```
```
          /* copy tx data */
```
```
          if (tx) {
```

                  memcpy_toio(priv->regs + HSSPI_FIFO_BASE +

                              HSSPI_FIFO_OP_SIZE, tx, curr_step);

```
                  tx += curr_step;
```
```
          }
```
```
          /* set fifo operation */
```

          writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),

                 priv->regs + HSSPI_FIFO_OP_REG);

          /* make sure we keep cs active until spi transfer is done */

```
          if (!cs_act) {
```

                  bcmbca_hsspi_activate_cs(priv, plat);

```
                  cs_act = 1;
```
```
          }
```
```
          /* issue the transfer */
```
```
          val = SPI_CMD_OP_START;
```

          val |= (plat->cs << SPI_CMD_PFL_SHIFT) &

```
                    SPI_CMD_PFL_MASK;
```

          val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &

                    SPI_CMD_SLAVE_MASK;

          writel(val, priv->regs + SPI_CMD_REG);

```
          /* wait for completion */
```

          ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,

                                SPI_STAT_SRCBUSY_MASK, false,

                                1000, false);

```
          if (ret) {
```

                  bcmbca_hsspi_deactivate_cs(priv, plat);

                  dev_err(dev, "interrupt timeout\n");

```
                  return ret;
```
```
          }
```
```
          data_bytes -= curr_step;
```

          if ((flags & SPI_XFER_END) && !data_bytes)

                  bcmbca_hsspi_deactivate_cs(priv, plat);

```
          /* copy rx data */
```
```
          if (rx) {
```

                  memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,

                                curr_step);

```
                  rx += curr_step;
```
```
          }
```
```
  }
```
```
  return 0;
```

+static const struct dm_spi_ops bcmbca_hsspi_ops = {

```
  .cs_info = bcmbca_hsspi_cs_info,
```
```
  .set_mode = bcmbca_hsspi_set_mode,
```
```
  .set_speed = bcmbca_hsspi_set_speed,
```
```
  .xfer = bcmbca_hsspi_xfer,
```

+};

+static const struct udevice_id bcmbca_hsspi_ids[] = {

  { .compatible = "brcm,bcmbca-hsspi-v1.1", },

```
  { /* sentinel */ }
```

+};

+static int bcmbca_hsspi_child_pre_probe(struct udevice *dev) +{

  struct bcmbca_hsspi_priv *priv = dev_get_priv(dev->parent);

  struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);

```
  u32 val;
```
```
  /* check cs */
```
```
  if (plat->cs >= priv->num_cs) {
```

          dev_err(dev, "no cs %u\n", plat->cs);

```
          return -EINVAL;
```
```
  }
```
```
  /* cs polarity */
```
```
  if (plat->mode & SPI_CS_HIGH)
```

          priv->cs_pols |= BIT(plat->cs);

```
  else
```

          priv->cs_pols &= ~BIT(plat->cs);

  /* set the polarity to spim cs register */

```
  val = readl(priv->spim_ctrl);
```

  val &= ~BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);

```
  if (priv->cs_pols & BIT(plat->cs))
```

          val |= BIT(plat->cs + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);

```
  writel(val, priv->spim_ctrl);
```

What is this code for cannot we handle this via set_mode or xfer?

This is the new register introduced in this controller to allow the driver to override the cs signal high and low from the controller so driver can control it directly. In the old controller, driver has no control over cs at all. Here we preset the OVERRIDE_VAL based on the cs_pols setting so the actually bcmbca_hsspi_activate/deactivate_cs function just need to set the OVERRIDE_SEL bit. The bcmbca_hsspi_activate/deactivate_cs functions has to be called right befer and after the controller start/finish the transation so can not be set via set_mode and xfer

...

Jagan.

William Zhang

2 May 2 May

8:58 p.m.

New subject: [PATCH v2 9/9] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Add entry for Broadcom Broadband SoC HS SPI drivers

Signed-off-by: William Zhang william.zhang@broadcom.com ---

Changes in v2: - Add Álvaro Fernández Rojas as another maintainer

MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS index 4c17c6cb9f1e..a1d490e66ed4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -823,6 +823,15 @@ F: include/bootstd.h F: net/eth_bootdevice.c F: test/boot/

+BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang william.zhang@broadcom.com +M: Kursad Oney kursad.oney@broadcom.com +M: Álvaro Fernández Rojas noltari@gmail.com +S: Maintained +F: doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/bcm63xx_hsspi.c +F: drivers/spi/bcmbca_hsspi.c + BTRFS M: Marek Behún kabel@kernel.org R: Qu Wenruo wqu@suse.com

-- 2.37.3

William Zhang

2 Jun 2 Jun

1:52 a.m.

Hi Jagan and Tom,

Any chance to get this patch series into the u-boot? I haven't heard any feedback and comments but they are largely based on patch series for linux that was accepted in kernel stable release 6.3 and verified on Broadcom reference boards.

Thanks, William

On 05/02/2023 11:58 AM, William Zhang wrote:

...

This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

MAINTAINERS | 9 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi | 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi | 18 + arch/arm/dts/bcm63146.dtsi | 19 + arch/arm/dts/bcm63148.dtsi | 18 + arch/arm/dts/bcm63158.dtsi | 15 +- arch/arm/dts/bcm63178.dtsi | 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts | 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts | 4 + arch/arm/dts/bcm963146.dts | 4 + arch/arm/dts/bcm963148.dts | 4 + arch/arm/dts/bcm963158.dts | 4 + arch/arm/dts/bcm963178.dts | 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 26 ++ .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++++++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++++++++++- drivers/spi/bcmbca_hsspi.c | 414 ++++++++++++++++++ 38 files changed, 1160 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c

Jagan Teki

8:01 a.m.

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...

This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting

This will fix for the upcoming release.

...

spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Patches send the patches related to SPI as separate series.

Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca.

Thanks, Jagan.

William Zhang

8:56 p.m.

Hi Jagan,

On 06/01/2023 11:01 PM, Jagan Teki wrote:

...

On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting

This will fix for the upcoming release.

...
spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Patches send the patches related to SPI as separate series.

Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca.

Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes

...

Thanks, Jagan.

William Zhang

6 Jun 6 Jun

10:19 p.m.

Hi Jagan,

On 06/02/2023 11:56 AM, William Zhang wrote:

...

Hi Jagan,

On 06/01/2023 11:01 PM, Jagan Teki wrote:

...
On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting

This will fix for the upcoming release.

...
spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Patches send the patches related to SPI as separate series.

Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca.

Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes

There is one issue in separating the patches to SPI only changes and arch/dts changes. The new BCMBCA HSSPI driver depends on a new config HAVE_SPI_CS_CTRL that is added to arch/arm/mach-bcmbca/Kconfig in the arch change patch series. So you will get build error on generating the .config and have to pick that change to avoid that issue. Will that be okay?

...

...
Thanks, Jagan.

Tom Rini

7 Jun 7 Jun

10:05 p.m.

On Tue, Jun 06, 2023 at 01:19:47PM -0700, William Zhang wrote:

...

Hi Jagan,

On 06/02/2023 11:56 AM, William Zhang wrote:

...
Hi Jagan,

On 06/01/2023 11:01 PM, Jagan Teki wrote:

...
On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting

This will fix for the upcoming release.

...
spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Patches send the patches related to SPI as separate series.

Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca.

Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes

There is one issue in separating the patches to SPI only changes and arch/dts changes. The new BCMBCA HSSPI driver depends on a new config HAVE_SPI_CS_CTRL that is added to arch/arm/mach-bcmbca/Kconfig in the arch change patch series. So you will get build error on generating the .config and have to pick that change to avoid that issue. Will that be okay?

Frankly I'd rather the whole series just come in via Jagan's tree, or if he's uncomfortable with that, I'll take the whole series if he's fine with the SPI side. We don't need to worry about which sub-tree is used so long as maintainers are happy with the contents, in U-Boot, imho.

-- Tom

William Zhang

10:31 p.m.

Hi Tom,

On 06/07/2023 01:05 PM, Tom Rini wrote:

...

On Tue, Jun 06, 2023 at 01:19:47PM -0700, William Zhang wrote:

...
Hi Jagan,

On 06/02/2023 11:56 AM, William Zhang wrote:

...
Hi Jagan,

On 06/01/2023 11:01 PM, Jagan Teki wrote:

...
On Wed, May 3, 2023 at 12:29 AM William Zhang william.zhang@broadcom.com wrote:

...
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly.

Changes in v2:

Add Álvaro Fernández Rojas as another maintainer

William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting

This will fix for the upcoming release.

...
spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers

Patches send the patches related to SPI as separate series.

Also please note that for arch patches, I have moved to tom since I'm unable to find the proper delate for bcmbca.

Thanks Jagan for the reviews. I will send out two patches series with updates based on the reviews: one for SPI driver changes and another for arch/dts/doc changes

There is one issue in separating the patches to SPI only changes and arch/dts changes. The new BCMBCA HSSPI driver depends on a new config HAVE_SPI_CS_CTRL that is added to arch/arm/mach-bcmbca/Kconfig in the arch change patch series. So you will get build error on generating the .config and have to pick that change to avoid that issue. Will that be okay?

Frankly I'd rather the whole series just come in via Jagan's tree, or if he's uncomfortable with that, I'll take the whole series if he's fine with the SPI side. We don't need to worry about which sub-tree is used so long as maintainers are happy with the contents, in U-Boot, imho.

Sounds good and thanks Tom! Let me send out the v3 of the whole series some time late today.

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Jagan Teki
Tom Rini
William Zhang