On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the rest of the pinctrl drivers, adjust the drivers so that support for each platform can be enabled/disabled individually and introduce platform specific configuration options.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/mach-snapdragon/Kconfig | 4 +++ arch/arm/mach-snapdragon/Makefile | 5 --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/qcom/Kconfig | 39 ++++++++++++++++++++++ drivers/pinctrl/qcom/Makefile | 9 +++++ .../pinctrl/qcom}/pinctrl-apq8016.c | 19 +++++++++-- .../pinctrl/qcom}/pinctrl-apq8096.c | 19 +++++++++-- .../pinctrl/qcom/pinctrl-qcom.c | 39 ++++++++++++---------- .../pinctrl/qcom/pinctrl-qcom.h | 11 +++--- .../pinctrl/qcom}/pinctrl-qcs404.c | 19 +++++++++-- .../pinctrl/qcom}/pinctrl-sdm845.c | 19 +++++++++-- 12 files changed, 148 insertions(+), 37 deletions(-)

Apart from nit below, feel free to add:

Reviewed-by: Sumit Garg sumit.garg@linaro.org

diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index eaf75abf4bd5..d12eb42ef9e2 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -17,6 +17,7 @@ config SDM845 default n select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_SDM845

•   imply PINCTRL_QCOM_SDM845
  
  

config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -29,6 +30,7 @@ config TARGET_DRAGONBOARD410C select BOARD_LATE_INIT select ENABLE_ARM_SOC_BOOT0_HOOK imply CLK_QCOM_APQ8016

•   imply PINCTRL_QCOM_APQ8016
    help
      Support for 96Boards Dragonboard 410C. This board complies with
      96Board Open Platform Specifications. Features:
  

@@ -43,6 +45,7 @@ config TARGET_DRAGONBOARD410C config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" imply CLK_QCOM_APQ8096

•   imply PINCTRL_QCOM_APQ8096
    help
      Support for 96Boards Dragonboard 820C. This board complies with
      96Board Open Platform Specifications. Features:
  

@@ -77,6 +80,7 @@ config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" select LINUX_KERNEL_IMAGE_HEADER imply CLK_QCOM_QCS404

•   imply PINCTRL_QCOM_QCS404
    help
      Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
      Features:
  

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 497ee35cf7d3..3a3a297c1768 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -8,9 +8,4 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o obj-y += misc.o obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 75b3ff47a2e8..53f32ea1612e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -355,6 +355,7 @@ source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" +source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fc1f01a02cbd..603c2e0a2da2 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_PINCTRL_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index 000000000000..412925c48788 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,39 @@ +if ARCH_SNAPDRAGON

+config PINCTRL_QCOM

•   depends on PINCTRL_GENERIC
  

•   def_bool n
  

+menu "Qualcomm pinctrl drivers"

+config PINCTRL_QCOM_APQ8016

•   bool "Qualcomm APQ8016 GCC"
  

•   select PINCTRL_QCOM
  

•   help
  

•     Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
  

•     Snapdragon 410 SoC, as well as the associated GPIO driver.
  

+config PINCTRL_QCOM_APQ8096

•   bool "Qualcomm APQ8096 GCC"
  

•   select PINCTRL_QCOM
  

•   help
  

•     Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
  

•     Snapdragon 820 SoC, as well as the associated GPIO driver.
  

+config PINCTRL_QCOM_QCS404

•   bool "Qualcomm QCS404 GCC"
  

•   select PINCTRL_QCOM
  

•   help
  

•     Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
  

•     as well as the associated GPIO driver.
  

+config PINCTRL_QCOM_SDM845

•   bool "Qualcomm SDM845 GCC"
  

•   select PINCTRL_QCOM
  

•   help
  

•     Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
  

•     as well as the associated GPIO driver.
  

+endmenu

+endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile new file mode 100644 index 000000000000..86f507427301 --- /dev/null +++ b/drivers/pinctrl/qcom/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Linaro Ltd.

+obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o +obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o +obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o +obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c similarity index 75% rename from arch/arm/mach-snapdragon/pinctrl-apq8016.c rename to drivers/pinctrl/qcom/pinctrl-apq8016.c index 70c0be0bca90..bcbc0df50715 100644 --- a/arch/arm/mach-snapdragon/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -6,8 +6,10 @@

*/

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>

+#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -52,10 +54,23 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data apq8016_data = { +static const struct msm_pinctrl_data apq8016_data = { .pin_count = 133, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8016_get_function_name, .get_function_mux = apq8016_get_function_mux, .get_pin_name = apq8016_get_pin_name, };

+static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
  

•   { /* Sentinal */ }
  

+};

+U_BOOT_DRIVER(pinctrl_apq8016) = {

•   .name           = "pinctrl_apq8016",
  

•   .id             = UCLASS_NOP,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

+}; diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c similarity index 74% rename from arch/arm/mach-snapdragon/pinctrl-apq8096.c rename to drivers/pinctrl/qcom/pinctrl-apq8096.c index 45462f01c2c7..525085617680 100644 --- a/arch/arm/mach-snapdragon/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -6,8 +6,10 @@

*/

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>

+#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -47,10 +49,23 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data apq8096_data = { +static const struct msm_pinctrl_data apq8096_data = { .pin_count = 157, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = apq8096_get_function_name, .get_function_mux = apq8096_get_function_mux, .get_pin_name = apq8096_get_pin_name, };

+static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
  

•   { /* Sentinal */ }
  

+};

+U_BOOT_DRIVER(pinctrl_apq8096) = {

•   .name           = "pinctrl_apq8096",
  

•   .id             = UCLASS_NOP,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

+}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/drivers/pinctrl/qcom/pinctrl-qcom.c similarity index 85% rename from arch/arm/mach-snapdragon/pinctrl-snapdragon.c rename to drivers/pinctrl/qcom/pinctrl-qcom.c index 826dc5148661..d41272ce9c95 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -11,10 +11,11 @@ #include <errno.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> -#include "pinctrl-snapdragon.h" +#include "pinctrl-qcom.h"

struct msm_pinctrl_priv { phys_addr_t base; @@ -109,7 +110,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; }

-static struct pinctrl_ops msm_pinctrl_ops = { +struct pinctrl_ops msm_pinctrl_ops = { .get_pins_count = msm_get_pins_count, .get_pin_name = msm_get_pin_name, .set_state = pinctrl_generic_set_state, @@ -121,12 +122,24 @@ static struct pinctrl_ops msm_pinctrl_ops = { .get_function_name = msm_get_function_name, };

-static int msm_pinctrl_bind(struct udevice *dev) +int msm_pinctrl_bind(struct udevice *dev) { ofnode node = dev_ofnode(dev);

•   struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
  

•   struct driver *drv;
  

•   struct udevice *pinctrl_dev;
    const char *name;
    int ret;
  
  

•   drv = lists_driver_lookup_name("qcom_pinctrl");
  

•   if (!drv)
  

•           return -ENOENT;
  

•   ret = device_bind_with_driver_data(dev_get_parent(dev), drv, ofnode_get_name(node), (ulong)data,
  

•                                      dev_ofnode(dev), &pinctrl_dev);
  

•   if (ret)
  

•           return ret;
  

•   ofnode_get_property(node, "gpio-controller", &ret);
    if (ret < 0)
            return 0;
  

@@ -139,28 +152,18 @@ static int msm_pinctrl_bind(struct udevice *dev) /* Bind gpio node */ ret = device_bind_driver_to_node(dev, "gpio_msm", name, node, NULL);

•   if (ret)
  

•   if (ret) {
  

•           device_unbind(pinctrl_dev);
            return ret;
  

•   dev_dbg(dev, "bind %s\n", name);
  

•   }
  
    return 0;
  

}

-static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
  

•   { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
  

•   { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
  

•   { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
  

•   { }
  

-};

-U_BOOT_DRIVER(pinctrl_snapdraon) = {

•   .name           = "pinctrl_msm",
  

+U_BOOT_DRIVER(qcom_pinctrl) = {

•   .name           = "qcom_pinctrl",
  

nit: I would prefer to rename driver as: pinctrl_qcom

-Sumit

    .id             = UCLASS_PINCTRL,

•   .of_match       = msm_pinctrl_ids,
    .priv_auto      = sizeof(struct msm_pinctrl_priv),
    .ops            = &msm_pinctrl_ops,
    .probe          = msm_pinctrl_probe,
  

•   .bind           = msm_pinctrl_bind,
  

}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/drivers/pinctrl/qcom/pinctrl-qcom.h similarity index 68% rename from arch/arm/mach-snapdragon/pinctrl-snapdragon.h rename to drivers/pinctrl/qcom/pinctrl-qcom.h index 178ee01a41f4..1edd9a43ffda 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -5,8 +5,8 @@

• (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com

*/ -#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H +#ifndef _PINCTRL_QCOM_H +#define _PINCTRL_QCOM_H

struct udevice;

@@ -25,9 +25,8 @@ struct pinctrl_function { int val; };

-extern struct msm_pinctrl_data apq8016_data; -extern struct msm_pinctrl_data apq8096_data; -extern struct msm_pinctrl_data sdm845_data; -extern struct msm_pinctrl_data qcs404_data; +extern struct pinctrl_ops msm_pinctrl_ops;

+int msm_pinctrl_bind(struct udevice *dev);

#endif diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c similarity index 78% rename from arch/arm/mach-snapdragon/pinctrl-qcs404.c rename to drivers/pinctrl/qcom/pinctrl-qcs404.c index a6e53c4412ec..272331c90b5c 100644 --- a/arch/arm/mach-snapdragon/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -5,8 +5,10 @@

• (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org

*/

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>

+#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -59,10 +61,23 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data qcs404_data = { +static struct msm_pinctrl_data qcs404_data = { .pin_count = 126, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = qcs404_get_function_name, .get_function_mux = qcs404_get_function_mux, .get_pin_name = qcs404_get_pin_name, };

+static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
  

•   { /* Sentinal */ }
  

+};

+U_BOOT_DRIVER(pinctrl_qcs404) = {

•   .name           = "pinctrl_qcs404",
  

•   .id             = UCLASS_NOP,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

+}; diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c similarity index 70% rename from arch/arm/mach-snapdragon/pinctrl-sdm845.c rename to drivers/pinctrl/qcom/pinctrl-sdm845.c index 40f2f012fa0d..1a09c5c81dc6 100644 --- a/arch/arm/mach-snapdragon/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -6,8 +6,10 @@

*/

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>

+#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); @@ -35,10 +37,23 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data sdm845_data = { +static struct msm_pinctrl_data sdm845_data = { .pin_count = 150, .functions_count = ARRAY_SIZE(msm_pinctrl_functions), .get_function_name = sdm845_get_function_name, .get_function_mux = sdm845_get_function_mux, .get_pin_name = sdm845_get_pin_name, };

+static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
  

•   { /* Sentinal */ }
  

+};

+U_BOOT_DRIVER(pinctrl_sdm845) = {

•   .name           = "pinctrl_sdm845",
  

•   .id             = UCLASS_NOP,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

+};

-- 2.42.0

On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver.

Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/dts/dragonboard845c-uboot.dtsi | 2 +- arch/arm/dts/sdm845.dtsi | 16 +++--------- arch/arm/dts/starqltechn-uboot.dtsi | 5 +--- arch/arm/dts/starqltechn.dts | 16 ++++++------ drivers/gpio/msm_gpio.c | 36 +++++++++++++++----------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 2 +- drivers/pinctrl/qcom/pinctrl-qcom.c | 31 +++++++++++++++-------- drivers/pinctrl/qcom/pinctrl-qcom.h | 5 +++- drivers/pinctrl/qcom/pinctrl-qcs404.c | 2 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 45 +++++++++++++++++++++++++++++++-- include/qcom-gpio.h | 28 ++++++++++++++++++++ 12 files changed, 133 insertions(+), 57 deletions(-)

diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi index 7106db8a7348..7728f4f4a3e5 100644 --- a/arch/arm/dts/dragonboard845c-uboot.dtsi +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi @@ -19,7 +19,7 @@ bootph-all; };

•           pinctrl_north@3900000 {
  

•           pinctrl@3400000 {
                    bootph-all;
            };
    };
  

diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 3b86b9328fc6..4798ace0ff8b 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -26,23 +26,13 @@ #power-domain-cells = <1>; };

•           gpio_north: gpio_north@3900000 {
  

•                   #gpio-cells = <2>;
  

•           tlmm: pinctrl@3400000 {
                    compatible = "qcom,sdm845-pinctrl";
  

•                   reg = <0x3900000 0x400000>;
  

•                   gpio-count = <150>;
  

•                   gpio-controller;
  

•                   gpio-ranges = <&gpio_north 0 0 150>;
  

•                   gpio-bank-name = "soc_north.";
  

•           };
  

•           tlmm_north: pinctrl_north@3900000 {
  

•                   compatible = "qcom,sdm845-pinctrl";
  

•                   reg = <0x3900000 0x400000>;
  

•                   reg = <0x3400000 0xc00000>;
                    gpio-count = <150>;
                    gpio-controller;
                    #gpio-cells = <2>;
  

•                   gpio-ranges = <&tlmm_north 0 0 150>;
  

•                   gpio-ranges = <&tlmm 0 0 150>;
  
                    /* DEBUG UART */
                    qup_uart9: qup-uart9-default {
  

diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi index d81a22ffe492..034d5c1c07ed 100644 --- a/arch/arm/dts/starqltechn-uboot.dtsi +++ b/arch/arm/dts/starqltechn-uboot.dtsi @@ -19,10 +19,7 @@ clock-controller@100000 { bootph-all; };

•           gpio_north@3900000 {
  

•                   bootph-all;
  

•           };
  

•           pinctrl_north@3900000 {
  

•           pinctrl@3400000 {
                    bootph-all;
            };
    };
  

diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index eec51d165f98..5b6372bee79a 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -65,15 +65,15 @@ serial@a84000 { status = "okay"; };

•   };
  

+};

•           pinctrl_north@3900000 {
  

•                   muic_i2c: muic_i2c {
  

•                           pins = "GPIO_33", "GPIO_34";
  

•                           drive-strength = <0x2>;
  

•                           function = "gpio";
  

•                           bias-disable;
  

•                   };
  

•           };
  

+&tlmm {

•   muic_i2c: muic-i2c-n {
  

•           pins = "GPIO_33", "GPIO_34";
  

•           drive-strength = <0x2>;
  

•           function = "gpio";
  

•           bias-disable;
    };
  

};

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 51670f263716..7d77776a25fd 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -11,13 +11,10 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> +#include <qcom-gpio.h>

DECLARE_GLOBAL_DATA_PTR;

-/* Register offsets */ -#define GPIO_CONFIG_OFF(no) ((no) * 0x1000) -#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)

/* OE */ #define GPIO_OE_DISABLE (0x0 << 9) #define GPIO_OE_ENABLE (0x1 << 9) @@ -29,15 +26,22 @@ DECLARE_GLOBAL_DATA_PTR;

struct msm_gpio_bank { phys_addr_t base;

•   const struct msm_pin_data *pin_data;
  

};

+#define GPIO_CONFIG_REG(dev, x) \

•   (qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x))
  

+#define GPIO_IN_OUT_REG(dev, x) \

•   (GPIO_CONFIG_REG(dev, x) + 0x4)
  

static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
  
    /* Disable OE bit */
  

•   clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
  

•   clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
  

•                   GPIO_OE_MASK, GPIO_OE_DISABLE);
  
    return 0;
  

} @@ -48,7 +52,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)

    value = !!value;
    /* set value */

•   writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
  

•   writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
  
    return 0;
  

} @@ -57,13 +61,13 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
  
    value = !!value;
    /* set value */
  

•   writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
  

•   writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
    /* switch direction */
  

•   clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
  

•   clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
  

•                   GPIO_OE_MASK, GPIO_OE_ENABLE);
  
    return 0;
  

} @@ -72,14 +76,14 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
  

•   return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
  

}

-static int msm_gpio_get_function(struct udevice *dev, unsigned offset) +static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
  

•   if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
            return GPIOF_OUTPUT;
  
    return GPIOF_INPUT;
  

@@ -98,6 +102,7 @@ static int msm_gpio_probe(struct udevice *dev) struct msm_gpio_bank *priv = dev_get_priv(dev);

    priv->base = dev_read_addr(dev);

•   priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
  
    return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  

} @@ -105,9 +110,10 @@ static int msm_gpio_probe(struct udevice *dev) static int msm_gpio_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

•   const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
  
  

•   uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  

•                                        "gpio-count", 0);
  

•   /* Get the pin count from the pinctrl driver */
  

•   uc_priv->gpio_count = pin_data->pin_count;
    uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
                                     "gpio-bank-name", NULL);
    if (uc_priv->bank_name == NULL)
  

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index bcbc0df50715..8149ffd83cc4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -55,7 +55,7 @@ static unsigned int apq8016_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8016_data = {

•   .pin_count = 133,
  

•   .pin_data = { .pin_count = 133, },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = apq8016_get_function_name,
    .get_function_mux = apq8016_get_function_mux,
  

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 525085617680..d64ab1ff7bee 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -50,7 +50,7 @@ static unsigned int apq8096_get_function_mux(unsigned int selector) }

static const struct msm_pinctrl_data apq8096_data = {

•   .pin_count = 157,
  

•   .pin_data = { .pin_count = 157, },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = apq8096_get_function_name,
    .get_function_mux = apq8096_get_function_mux,
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index d41272ce9c95..fb255f9572f4 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -13,8 +13,11 @@ #include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> +#include <qcom-gpio.h>

#include "pinctrl-qcom.h"

struct msm_pinctrl_priv { @@ -22,7 +25,9 @@ struct msm_pinctrl_priv { struct msm_pinctrl_data *data; };

-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define GPIO_CONFIG_REG(priv, x) \

•   (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
  

#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) @@ -45,7 +50,7 @@ static int msm_get_pins_count(struct udevice *dev) { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   return priv->data->pin_count;
  

•   return priv->data->pin_data.pin_count;
  

}

static const char *msm_get_function_name(struct udevice *dev, @@ -61,7 +66,7 @@ static int msm_pinctrl_probe(struct udevice *dev) struct msm_pinctrl_priv *priv = dev_get_priv(dev);

    priv->base = dev_read_addr(dev);

•   priv->data = (struct msm_pinctrl_data *)dev->driver_data;
  

•   priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
  
    return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  

} @@ -78,7 +83,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•   clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                    TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
                    priv->data->get_function_mux(func_selector) << 2);
    return 0;
  

@@ -92,15 +97,15 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: argument = (argument / 2) - 1;

•           clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•           clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                            TLMM_DRV_STRENGTH_MASK, argument << 6);
            break;
    case PIN_CONFIG_BIAS_DISABLE:
  

•           clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•           clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                         TLMM_GPIO_PULL_MASK);
            break;
    case PIN_CONFIG_BIAS_PULL_UP:
  

•           clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•           clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                            TLMM_GPIO_PULL_MASK, argument);
            break;
    default:
  

@@ -149,9 +154,15 @@ int msm_pinctrl_bind(struct udevice *dev) if (!name) return -EINVAL;

•   /* Bind gpio node */
  

•   ret = device_bind_driver_to_node(dev, "gpio_msm",
  

•                                    name, node, NULL);
  

•   drv = lists_driver_lookup_name("gpio_msm");
  

•   if (!drv) {
  

•           printf("Can't find gpio_msm driver\n");
  

•           return -ENODEV;
  

•   }
  

•   /* Bind gpio device as a child of the pinctrl device */
  

•   ret = device_bind_with_driver_data(pinctrl_dev, drv,
  

•                                      name, (ulong)&data->pin_data, node, NULL);
    if (ret) {
            device_unbind(pinctrl_dev);
            return ret;
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 1edd9a43ffda..efb6a44b1409 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -8,10 +8,13 @@ #ifndef _PINCTRL_QCOM_H #define _PINCTRL_QCOM_H

+#include <asm/types.h> +#include <qcom-gpio.h>

struct udevice;

struct msm_pinctrl_data {

•   int pin_count;
  

•   struct msm_pin_data pin_data;
    int functions_count;
    const char *(*get_function_name)(struct udevice *dev,
                                     unsigned int selector);
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 272331c90b5c..ac00afa2a1f4 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -62,7 +62,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data qcs404_data = {

•   .pin_count = 126,
  

•   .pin_data = { .pin_count = 126, },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = qcs404_get_function_name,
    .get_function_mux = qcs404_get_function_mux,
  

diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 1a09c5c81dc6..9f0f4085ce2d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -3,6 +3,7 @@

• Qualcomm SDM845 pinctrl
• (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com

• • (C) Copyright 2023 Linaro Ltd.
  */

@@ -11,6 +12,10 @@

#include "pinctrl-qcom.h"

+#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define EAST 0x00100000

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");

@@ -19,6 +24,39 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, };

+static const unsigned int sdm845_pin_offsets[] = {

•   [0] = EAST,    [1] = EAST,    [2] = EAST,    [3] = EAST,    [4] = NORTH,
  

•   [5] = NORTH,   [6] = NORTH,   [7] = NORTH,   [8] = EAST,    [9] = EAST,
  

•   [10] = EAST,   [11] = EAST,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
  

•   [15] = SOUTH,  [16] = SOUTH,  [17] = SOUTH,  [18] = SOUTH,  [19] = SOUTH,
  

•   [20] = SOUTH,  [21] = SOUTH,  [22] = SOUTH,  [23] = SOUTH,  [24] = SOUTH,
  

•   [25] = SOUTH,  [26] = SOUTH,  [27] = EAST,   [28] = EAST,   [29] = EAST,
  

•   [30] = EAST,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = NORTH,
  

•   [35] = SOUTH,  [36] = SOUTH,  [37] = SOUTH,  [38] = NORTH,  [39] = EAST,
  

•   [40] = SOUTH,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
  

•   [45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = NORTH,
  

•   [50] = NORTH,  [51] = NORTH,  [52] = NORTH,  [53] = NORTH,  [54] = NORTH,
  

•   [55] = NORTH,  [56] = NORTH,  [57] = NORTH,  [58] = NORTH,  [59] = NORTH,
  

•   [60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
  

•   [65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = EAST,
  

•   [70] = EAST,   [71] = EAST,   [72] = EAST,   [73] = EAST,   [74] = EAST,
  

•   [75] = EAST,   [76] = EAST,   [77] = EAST,   [78] = EAST,   [79] = NORTH,
  

•   [80] = NORTH,  [81] = NORTH,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
  

•   [85] = EAST,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = SOUTH,
  

•   [90] = SOUTH,  [91] = SOUTH,  [92] = SOUTH,  [93] = SOUTH,  [94] = SOUTH,
  

•   [95] = SOUTH,  [96] = SOUTH,  [97] = NORTH,  [98] = NORTH,  [99] = NORTH,
  

•   [100] = NORTH, [101] = NORTH, [102] = NORTH, [103] = NORTH, [104] = NORTH,
  

•   [105] = NORTH, [106] = NORTH, [107] = NORTH, [108] = NORTH, [109] = NORTH,
  

•   [110] = NORTH, [111] = NORTH, [112] = NORTH, [113] = NORTH, [114] = NORTH,
  

•   [115] = NORTH, [116] = NORTH, [117] = NORTH, [118] = NORTH, [119] = NORTH,
  

•   [120] = NORTH, [121] = NORTH, [122] = EAST,  [123] = EAST,  [124] = EAST,
  

•   [125] = EAST,  [126] = EAST,  [127] = NORTH, [128] = NORTH, [129] = NORTH,
  

•   [130] = NORTH, [131] = NORTH, [132] = NORTH, [133] = NORTH, [134] = NORTH,
  

•   [135] = NORTH, [136] = NORTH, [137] = NORTH, [138] = NORTH, [139] = NORTH,
  

•   [140] = NORTH, [141] = NORTH, [142] = NORTH, [143] = NORTH, [144] = NORTH,
  

•   [145] = NORTH, [146] = NORTH, [147] = NORTH, [148] = NORTH, [149] = NORTH,
  

+};

static const char *sdm845_get_function_name(struct udevice *dev, unsigned int selector) { @@ -28,7 +66,7 @@ static const char *sdm845_get_function_name(struct udevice *dev, static const char *sdm845_get_pin_name(struct udevice *dev, unsigned int selector) {

•   snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
  

•   snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
    return pin_name;
  

}

@@ -38,7 +76,10 @@ static unsigned int sdm845_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data sdm845_data = {

•   .pin_count = 150,
  

•   .pin_data = {
  

•           .pin_offsets = sdm845_pin_offsets,
  

•           .pin_count = ARRAY_SIZE(sdm845_pin_offsets),
  

•   },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = sdm845_get_function_name,
    .get_function_mux = sdm845_get_function_mux,
  

diff --git a/include/qcom-gpio.h b/include/qcom-gpio.h new file mode 100644 index 000000000000..8dac62f870b9 --- /dev/null +++ b/include/qcom-gpio.h

The header contents should rather move to ./arch/arm/mach-snapdragon/include/mach/gpio.h.

-Sumit

@@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Qualcomm common pin control data.
• • Copyright (C) 2023 Linaro Ltd.
• */

+#ifndef _QCOM_GPIO_H_ +#define _QCOM_GPIO_H_

+#include <asm/types.h> +#include <stdbool.h>

+struct msm_pin_data {

•   int pin_count;
  

•   const unsigned int *pin_offsets;
  

+};

+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector) +{

•   u32 out = (selector * 0x1000);
  

•   if (offs)
  

•           return out + offs[selector];
  

•   return out;
  

+}

+#endif /* _QCOM_GPIO_H_ */

-- 2.42.0

On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

Some Qualcomm boards feature reserved ranges of pins which are protected by firmware. Attempting to read or write any registers associated with these pins results the board resetting.

Does any of the current Qcom boards supported in u-boot require this feature? If not then you should introduce this feature alongside the new Qcom boards requiring this feature.

-Sumit

Add support for parsing these ranges from devicetree and ensure that the pinctrl and GPIO drivers don't try to interact with these pins.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/gpio/msm_gpio.c | 15 +++++++++ drivers/pinctrl/qcom/pinctrl-qcom.c | 64 +++++++++++++++++++++++++++++++++++++ include/qcom-gpio.h | 15 +++++++++ 3 files changed, 94 insertions(+)

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 7d77776a25fd..7a09abdafb2e 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -39,6 +39,9 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•           return 0;
  

•   /* Disable OE bit */
    clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
                    GPIO_OE_MASK, GPIO_OE_DISABLE);
  

@@ -50,6 +53,9 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•           return 0;
  

•   value = !!value;
    /* set value */
    writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
  

@@ -62,6 +68,9 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•           return 0;
  

•   value = !!value;
    /* set value */
    writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
  

@@ -76,6 +85,9 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•           return 0;
  

•   return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
  

}

@@ -83,6 +95,9 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•           return GPIOF_UNKNOWN;
  

•   if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
            return GPIOF_OUTPUT;
  
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index fb255f9572f4..92b35c198788 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -20,9 +20,13 @@

#include "pinctrl-qcom.h"

+#define MSM_PINCTRL_MAX_RESERVED_RANGES 32

struct msm_pinctrl_priv { phys_addr_t base; struct msm_pinctrl_data *data;

•   u32 reserved_ranges[MSM_PINCTRL_MAX_RESERVED_RANGES * 2];
  

•   int reserved_ranges_count;
  

};

#define GPIO_CONFIG_REG(priv, x) \ @@ -61,13 +65,53 @@ static const char *msm_get_function_name(struct udevice *dev, return priv->data->get_function_name(dev, selector); }

+static int msm_pinctrl_parse_ranges(struct udevice *dev) +{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   int count;
  

•   if (ofnode_read_prop(dev_ofnode(dev), "gpio-reserved-ranges",
  

•                        &count)) {
  

•           if (count % 2 == 1) {
  

•                   dev_err(dev, "gpio-reserved-ranges must be a multiple of 2\n");
  

•                   return -EINVAL;
  

•           }
  

•           /* Size is in bytes, but we're indexing by ints */
  

•           count /= 4;
  

•           if (count > MSM_PINCTRL_MAX_RESERVED_RANGES) {
  

•                   dev_err(dev, "gpio-reserved-ranges must be less than %d (got %d)\n",
  

•                           MSM_PINCTRL_MAX_RESERVED_RANGES, count);
  

•                   return -EINVAL;
  

•           }
  

•           priv->reserved_ranges_count = count;
  

•           for (count = 0; count < priv->reserved_ranges_count; count++) {
  

•                   if (ofnode_read_u32_index(dev_ofnode(dev), "gpio-reserved-ranges",
  

•                                             count, &priv->reserved_ranges[count])) {
  

•                           dev_err(dev, "failed to read gpio-reserved-ranges[%d]\n", count);
  

•                           return -EINVAL;
  

•                   }
  

•           }
  

•   }
  

•   return 0;
  

+}

static int msm_pinctrl_probe(struct udevice *dev) { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   int ret;
  
    priv->base = dev_read_addr(dev);
    priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
  
  

•   ret = msm_pinctrl_parse_ranges(dev);
  

•   if (ret) {
  

•           printf("Couldn't parse reserved GPIO ranges!\n");
  

•           return ret;
  

•   }
  

•   return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  

}

@@ -83,6 +127,9 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev, pin_selector))
  

•           return 0;
  

•   clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
                    TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
                    priv->data->get_function_mux(func_selector) << 2);
  

@@ -94,6 +141,9 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

•   if (msm_pinctrl_is_reserved(dev, pin_selector))
  

•           return 0;
  

•   switch (param) {
    case PIN_CONFIG_DRIVE_STRENGTH:
            argument = (argument / 2) - 1;
  

@@ -178,3 +228,17 @@ U_BOOT_DRIVER(qcom_pinctrl) = { .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, };

+bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin) +{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   unsigned int i, start;
  

•   for (i = 0; i < priv->reserved_ranges_count; i += 2) {
  

•           start = priv->reserved_ranges[i];
  

•           if (pin >= start && pin < start + priv->reserved_ranges[i + 1])
  

•                   return true;
  

•   }
  

•   return false;
  

+} diff --git a/include/qcom-gpio.h b/include/qcom-gpio.h index 8dac62f870b9..490a1de55f89 100644 --- a/include/qcom-gpio.h +++ b/include/qcom-gpio.h @@ -25,4 +25,19 @@ static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selecto return out; }

+struct udevice;

+/**

• • msm_pinctrl_is_reserved() - Check if a pin lies in a reserved range
• • @dev: pinctrl device
• • @pin: Pin number
• • Returns: true if pin is reserved, otherwise false
• • Call using dev_get_parent() from the GPIO device, it is a child of
• • the pinctrl device.
• */

+bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin);

#endif /* _QCOM_GPIO_H_ */

-- 2.42.0

On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

Replaces the uses of "unsigned" with "unsigned int".

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/gpio/msm_gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 7a09abdafb2e..7d01fecf46f2 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -49,7 +49,7 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) return 0; }

-static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);

@@ -63,7 +63,7 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value) return 0; }

-static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, +static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -81,7 +81,7 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio, return 0; }

-static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) +static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

@@ -91,7 +91,7 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned gpio) return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); }

-static int msm_gpio_get_function(struct udevice *dev, unsigned gpio) +static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

-- 2.42.0

On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add it to drivers/pinctrl/qcom.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 8 - arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 --------------------- arch/arm/mach-ipq40xx/pinctrl-snapdragon.h | 30 ---- drivers/pinctrl/qcom/Kconfig | 7 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom}/pinctrl-ipq4019.c | 25 +++- 7 files changed, 28 insertions(+), 210 deletions(-)

I would expect this to be the 2nd patch in this series. Apart from that feel free to add:

Acked-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index faccfaf720a8..23daed70aac9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -767,6 +767,7 @@ config ARCH_IPQ40XX select SMEM select OF_CONTROL select CLK_QCOM_IPQ4019

•   select PINCTRL_QCOM_IPQ4019
    imply CMD_DM
  
  

config ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile deleted file mode 100644 index b36a935c6f9f..000000000000 --- a/arch/arm/mach-ipq40xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2019 Sartura Ltd. -# -# Author: Robert Marko robert.marko@sartura.hr

-obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c deleted file mode 100644 index 036fec93d727..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • TLMM driver for Qualcomm IPQ40xx
• • (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com
• • Copyright (c) 2020 Sartura Ltd.
• • Author: Robert Marko robert.marko@sartura.hr
• */

-#include <common.h> -#include <dm.h> -#include <errno.h> -#include <asm/io.h> -#include <dm/device_compat.h> -#include <dm/lists.h> -#include <dm/pinctrl.h> -#include <linux/bitops.h> -#include "pinctrl-snapdragon.h"

-struct msm_pinctrl_priv {

•   phys_addr_t base;
  

•   struct msm_pinctrl_data *data;
  

-};

-#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9)

-static const struct pinconf_param msm_conf_params[] = {

•   { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
  

•   { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  

•   { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
  

-};

-static int msm_get_functions_count(struct udevice *dev) -{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   return priv->data->functions_count;
  

-}

-static int msm_get_pins_count(struct udevice *dev) -{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   return priv->data->pin_count;
  

-}

-static const char *msm_get_function_name(struct udevice *dev,

•                                    unsigned int selector)
  

-{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   return priv->data->get_function_name(dev, selector);
  

-}

-static int msm_pinctrl_probe(struct udevice *dev) -{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   priv->base = devfdt_get_addr(dev);
  

•   priv->data = (struct msm_pinctrl_data *)dev->driver_data;
  

•   return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  

-}

-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) -{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   return priv->data->get_pin_name(dev, selector);
  

-}

-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,

•                     unsigned int func_selector)
  

-{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•                   TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
  

•                   priv->data->get_function_mux(func_selector) << 2);
  

•   return 0;
  

-}

-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,

•                      unsigned int param, unsigned int argument)
  

-{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   switch (param) {
  

•   case PIN_CONFIG_DRIVE_STRENGTH:
  

•           clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•                           TLMM_DRV_STRENGTH_MASK, argument << 6);
  

•           break;
  

•   case PIN_CONFIG_BIAS_DISABLE:
  

•           clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•                        TLMM_GPIO_PULL_MASK);
  

•           break;
  

•   case PIN_CONFIG_BIAS_PULL_UP:
  

•           clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
  

•                        TLMM_GPIO_PULL_MASK, argument);
  

•           break;
  

•   default:
  

•           return 0;
  

•   }
  

•   return 0;
  

-}

-static int msm_pinctrl_bind(struct udevice *dev) -{

•   ofnode node = dev_ofnode(dev);
  

•   const char *name;
  

•   int ret;
  

•   ofnode_get_property(node, "gpio-controller", &ret);
  

•   if (ret < 0)
  

•           return 0;
  

•   /* Get the name of gpio node */
  

•   name = ofnode_get_name(node);
  

•   if (!name)
  

•           return -EINVAL;
  

•   /* Bind gpio node */
  

•   ret = device_bind_driver_to_node(dev, "gpio_msm",
  

•                                    name, node, NULL);
  

•   if (ret)
  

•           return ret;
  

•   dev_dbg(dev, "bind %s\n", name);
  

•   return 0;
  

-}

-static struct pinctrl_ops msm_pinctrl_ops = {

•   .get_pins_count = msm_get_pins_count,
  

•   .get_pin_name = msm_get_pin_name,
  

•   .set_state = pinctrl_generic_set_state,
  

•   .pinmux_set = msm_pinmux_set,
  

•   .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
  

•   .pinconf_params = msm_conf_params,
  

•   .pinconf_set = msm_pinconf_set,
  

•   .get_functions_count = msm_get_functions_count,
  

•   .get_function_name = msm_get_function_name,
  

-};

-static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
  

•   { }
  

-};

-U_BOOT_DRIVER(pinctrl_snapdraon) = {

•   .name           = "pinctrl_msm",
  

•   .id             = UCLASS_PINCTRL,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .priv_auto      = sizeof(struct msm_pinctrl_priv),
  

•   .ops            = &msm_pinctrl_ops,
  

•   .probe          = msm_pinctrl_probe,
  

•   .bind           = msm_pinctrl_bind,
  

-}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h deleted file mode 100644 index 2341a713495d..000000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Qualcomm Pin control
• • (C) Copyright 2018 Ramon Fried ramon.fried@gmail.com
• */

-#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H

-#include <common.h>

-struct msm_pinctrl_data {

•   int pin_count;
  

•   int functions_count;
  

•   const char *(*get_function_name)(struct udevice *dev,
  

•                                    unsigned int selector);
  

•   unsigned int (*get_function_mux)(unsigned int selector);
  

•   const char *(*get_pin_name)(struct udevice *dev,
  

•                               unsigned int selector);
  

-};

-struct pinctrl_function {

•   const char *name;
  

•   int val;
  

-};

-extern struct msm_pinctrl_data ipq4019_data;

-#endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 412925c48788..2fe639814785 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -20,6 +20,13 @@ config PINCTRL_QCOM_APQ8096 Say Y here to enable support for pinctrl on the MSM8996 / APQ8096 Snapdragon 820 SoC, as well as the associated GPIO driver.

+config PINCTRL_QCOM_IPQ4019

•   bool "Qualcomm IPQ4019 GCC"
  

•   select PINCTRL_QCOM
  

•   help
  

•     Say Y here to enable support for pinctrl on the IPQ4019 SoC,
  

•     as well as the associated GPIO driver.
  

config PINCTRL_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select PINCTRL_QCOM diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 86f507427301..6d9aca6d7b7e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -4,6 +4,7 @@

obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c similarity index 71% rename from arch/arm/mach-ipq40xx/pinctrl-ipq4019.c rename to drivers/pinctrl/qcom/pinctrl-ipq4019.c index 3e365f8cc86a..2d99f99e1e45 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -7,12 +7,13 @@

• Author: Robert Marko robert.marko@sartura.hr

*/

-#include "pinctrl-snapdragon.h" #include <common.h> +#include <dm.h>

+#include "pinctrl-qcom.h"

#define MAX_PIN_NAME_LEN 32 -static char pin_name[MAX_PIN_NAME_LEN];

+static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"gpio", 0}, {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ @@ -26,7 +27,6 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"mdc_0", 1}, /* Only for GPIO7 */ {"mdc_1", 2}, /* Only for GPIO52 */ };

static const char *ipq4019_get_function_name(struct udevice *dev, unsigned int selector) { @@ -45,10 +45,23 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector) return msm_pinctrl_functions[selector].val; }

-struct msm_pinctrl_data ipq4019_data = {

•   .pin_count = 100,
  

+static const struct msm_pinctrl_data ipq4019_data = {

•   .pin_data = { .pin_count = 100, },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = ipq4019_get_function_name,
    .get_function_mux = ipq4019_get_function_mux,
    .get_pin_name = ipq4019_get_pin_name,
  

};

+static const struct udevice_id msm_pinctrl_ids[] = {

•   { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
  

•   { /* Sentinal */ }
  

+};

+U_BOOT_DRIVER(pinctrl_ipq4019) = {

•   .name           = "pinctrl_ipq4019",
  

•   .id             = UCLASS_NOP,
  

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

+};

-- 2.42.0

On Tue, 31 Oct 2023 at 19:52, Caleb Connolly caleb.connolly@linaro.org wrote:

The "MSM" naming hasn't been correct for quite a while now, in line with Linux lets rename all these msm_* functions to qcom_* as well as ensure namespacing is consistent across the pinctrl and GPIO drivers.

Can we do it treewide for once such that there isn't any inconsistent naming? You can push that as a separate patch too.

-Sumit

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

configs/dragonboard410c_defconfig | 2 +- configs/dragonboard845c_defconfig | 2 +- configs/qcs404evb_defconfig | 2 +- configs/starqltechn_defconfig | 2 +- drivers/gpio/Kconfig | 6 +- drivers/gpio/Makefile | 2 +- drivers/gpio/{msm_gpio.c => qcom_gpio.c} | 72 ++++++++++++------------ drivers/pinctrl/qcom/pinctrl-apq8016.c | 22 ++++---- drivers/pinctrl/qcom/pinctrl-apq8096.c | 22 ++++---- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 18 +++--- drivers/pinctrl/qcom/pinctrl-qcom.c | 96 ++++++++++++++++---------------- drivers/pinctrl/qcom/pinctrl-qcom.h | 8 +-- drivers/pinctrl/qcom/pinctrl-qcs404.c | 22 ++++---- drivers/pinctrl/qcom/pinctrl-sdm845.c | 19 +++---- include/qcom-gpio.h | 6 +- 15 files changed, 149 insertions(+), 152 deletions(-)

diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index b338326e34c0..11c631799ccf 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -43,7 +43,7 @@ CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_MSM_GPIO=y +CONFIG_QCOM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig index a69d82761a8d..afbdc15d88b2 100644 --- a/configs/dragonboard845c_defconfig +++ b/configs/dragonboard845c_defconfig @@ -19,7 +19,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_CMD_GPIO=y # CONFIG_NET is not set CONFIG_CLK=y -CONFIG_MSM_GPIO=y +CONFIG_QCOM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig index 9e72f64f7849..545ee25b0e7d 100644 --- a/configs/qcs404evb_defconfig +++ b/configs/qcs404evb_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_NET is not set CONFIG_CLK=y -CONFIG_MSM_GPIO=y +CONFIG_QCOM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_MISC=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig index 5b85ce5fe96f..9962211d8ab7 100644 --- a/configs/starqltechn_defconfig +++ b/configs/starqltechn_defconfig @@ -23,7 +23,7 @@ CONFIG_CMD_BMP=y # CONFIG_NET is not set CONFIG_BUTTON=y CONFIG_CLK=y -CONFIG_MSM_GPIO=y +CONFIG_QCOM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 74baa98d3c15..2e57eedd466f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -259,7 +259,7 @@ config MSCC_SGPIO SIO controller is to connect control signals from SFP modules and to act as an LED controller.

-config MSM_GPIO +config QCOM_GPIO bool "Qualcomm GPIO driver" depends on DM_GPIO help @@ -268,9 +268,7 @@ config MSM_GPIO gpio has it's own set of registers. Only simple GPIO operations are supported (get/set, change of direction and checking pin function).

•     Supported devices:
  

•     - APQ8016
  

•     - MSM8916
  

•     See PINCTRL_QCOM for a list of supported platforms.
  
  

config MXC_GPIO bool "Freescale/NXP MXC GPIO driver" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c8b3fd78141a..b5ebcf75dbfa 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -58,7 +58,7 @@ obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o -obj-$(CONFIG_MSM_GPIO) += msm_gpio.o +obj-$(CONFIG_QCOM_GPIO) += qcom_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o obj-$(CONFIG_$(SPL_TPL_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/qcom_gpio.c similarity index 50% rename from drivers/gpio/msm_gpio.c rename to drivers/gpio/qcom_gpio.c index 7d01fecf46f2..a0b183eb0784 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/qcom_gpio.c @@ -24,22 +24,22 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_IN 0 #define GPIO_OUT 1

-struct msm_gpio_bank { +struct qcom_gpio_priv { phys_addr_t base;

•   const struct msm_pin_data *pin_data;
  

•   const struct qcom_pin_data *pin_data;
  

};

#define GPIO_CONFIG_REG(dev, x) \

•   (qcom_pin_offset(((struct msm_gpio_bank *)dev_get_priv(dev))->pin_data->pin_offsets, x))
  

•   (qcom_pin_offset(((struct qcom_gpio_priv *)dev_get_priv(dev))->pin_data->pin_offsets, x))
  
  

#define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4)

-static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +static int qcom_gpio_direction_input(struct udevice *dev, unsigned int gpio) {

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•   if (qcom_pinctrl_is_reserved(dev_get_parent(dev), gpio))
            return 0;
  
    /* Disable OE bit */
  

@@ -49,11 +49,11 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) return 0; }

-static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) +static int qcom_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) {

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•   if (qcom_pinctrl_is_reserved(dev_get_parent(dev), gpio))
            return 0;
  
    value = !!value;
  

@@ -63,12 +63,12 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) return 0; }

-static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio,

•                                int value)
  

+static int qcom_gpio_direction_output(struct udevice *dev, unsigned int gpio,

•                                 int value)
  

{

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•   if (qcom_pinctrl_is_reserved(dev_get_parent(dev), gpio))
            return 0;
  
    value = !!value;
  

@@ -81,21 +81,21 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, return 0; }

-static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) +static int qcom_gpio_get_value(struct udevice *dev, unsigned int gpio) {

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•   if (qcom_pinctrl_is_reserved(dev_get_parent(dev), gpio))
            return 0;
  
    return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
  

}

-static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) +static int qcom_gpio_get_function(struct udevice *dev, unsigned int gpio) {

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev_get_parent(dev), gpio))
  

•   if (qcom_pinctrl_is_reserved(dev_get_parent(dev), gpio))
            return GPIOF_UNKNOWN;
  
    if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
  

@@ -104,28 +104,28 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) return GPIOF_INPUT; }

-static const struct dm_gpio_ops gpio_msm_ops = {

•   .direction_input        = msm_gpio_direction_input,
  

•   .direction_output       = msm_gpio_direction_output,
  

•   .get_value              = msm_gpio_get_value,
  

•   .set_value              = msm_gpio_set_value,
  

•   .get_function           = msm_gpio_get_function,
  

+static const struct dm_gpio_ops qcom_gpio_ops = {

•   .direction_input        = qcom_gpio_direction_input,
  

•   .direction_output       = qcom_gpio_direction_output,
  

•   .get_value              = qcom_gpio_get_value,
  

•   .set_value              = qcom_gpio_set_value,
  

•   .get_function           = qcom_gpio_get_function,
  

};

-static int msm_gpio_probe(struct udevice *dev) +static int qcom_gpio_probe(struct udevice *dev) {

•   struct msm_gpio_bank *priv = dev_get_priv(dev);
  

•   struct qcom_gpio_priv *priv = dev_get_priv(dev);
  
    priv->base = dev_read_addr(dev);
  

•   priv->pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
  

•   priv->pin_data = (struct qcom_pin_data *)dev_get_driver_data(dev);
  
    return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
  

}

-static int msm_gpio_of_to_plat(struct udevice *dev) +static int qcom_gpio_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

•   const struct msm_pin_data *pin_data = (struct msm_pin_data *)dev_get_driver_data(dev);
  

•   const struct qcom_pin_data *pin_data = (struct qcom_pin_data *)dev_get_driver_data(dev);
  
    /* Get the pin count from the pinctrl driver */
    uc_priv->gpio_count = pin_data->pin_count;
  

@@ -137,12 +137,12 @@ static int msm_gpio_of_to_plat(struct udevice *dev) return 0; }

-U_BOOT_DRIVER(gpio_msm) = {

•   .name   = "gpio_msm",
  

+U_BOOT_DRIVER(qcom_gpio) = {

•   .name   = "qcom_gpio",
    .id     = UCLASS_GPIO,
  

•   .of_to_plat = msm_gpio_of_to_plat,
  

•   .probe  = msm_gpio_probe,
  

•   .ops    = &gpio_msm_ops,
  

•   .of_to_plat = qcom_gpio_of_to_plat,
  

•   .probe  = qcom_gpio_probe,
  

•   .ops    = &qcom_gpio_ops,
    .flags  = DM_UC_FLAG_SEQ_ALIAS,
  

•   .priv_auto      = sizeof(struct msm_gpio_bank),
  

•   .priv_auto      = sizeof(struct qcom_gpio_priv),
  

}; diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 8149ffd83cc4..652f8a51be60 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -13,7 +13,7 @@

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); -static const char * const msm_pinctrl_pins[] = { +static const char * const qcom_pinctrl_pins[] = { "SDC1_CLK", "SDC1_CMD", "SDC1_DATA", @@ -28,14 +28,14 @@ static const char * const msm_pinctrl_pins[] = { "QDSD_DATA3", };

-static const struct pinctrl_function msm_pinctrl_functions[] = { +static const struct pinctrl_function qcom_pinctrl_functions[] = { {"blsp1_uart", 2}, };

static const char *apq8016_get_function_name(struct udevice *dev, unsigned int selector) {

•   return msm_pinctrl_functions[selector].name;
  

•   return qcom_pinctrl_functions[selector].name;
  

}

static const char *apq8016_get_pin_name(struct udevice *dev, @@ -45,24 +45,24 @@ static const char *apq8016_get_pin_name(struct udevice *dev, snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); return pin_name; } else {

•           return msm_pinctrl_pins[selector - 122];
  

•           return qcom_pinctrl_pins[selector - 122];
    }
  

}

static unsigned int apq8016_get_function_mux(unsigned int selector) {

•   return msm_pinctrl_functions[selector].val;
  

•   return qcom_pinctrl_functions[selector].val;
  

}

-static const struct msm_pinctrl_data apq8016_data = { +static const struct qcom_pinctrl_data apq8016_data = { .pin_data = { .pin_count = 133, },

•   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  

•   .functions_count = ARRAY_SIZE(qcom_pinctrl_functions),
    .get_function_name = apq8016_get_function_name,
    .get_function_mux = apq8016_get_function_mux,
    .get_pin_name = apq8016_get_pin_name,
  

};

-static const struct udevice_id msm_pinctrl_ids[] = { +static const struct udevice_id qcom_pinctrl_ids[] = { { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data }, { /* Sentinal */ } }; @@ -70,7 +70,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { U_BOOT_DRIVER(pinctrl_apq8016) = { .name = "pinctrl_apq8016", .id = UCLASS_NOP,

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

•   .of_match       = qcom_pinctrl_ids,
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .bind           = qcom_pinctrl_bind,
  

}; diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index d64ab1ff7bee..d0c1424dff7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -13,7 +13,7 @@

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); -static const char * const msm_pinctrl_pins[] = { +static const char * const qcom_pinctrl_pins[] = { "SDC1_CLK", "SDC1_CMD", "SDC1_DATA", @@ -23,14 +23,14 @@ static const char * const msm_pinctrl_pins[] = { "SDC1_RCLK", };

-static const struct pinctrl_function msm_pinctrl_functions[] = { +static const struct pinctrl_function qcom_pinctrl_functions[] = { {"blsp_uart8", 2}, };

static const char *apq8096_get_function_name(struct udevice *dev, unsigned int selector) {

•   return msm_pinctrl_functions[selector].name;
  

•   return qcom_pinctrl_functions[selector].name;
  

}

static const char *apq8096_get_pin_name(struct udevice *dev, @@ -40,24 +40,24 @@ static const char *apq8096_get_pin_name(struct udevice *dev, snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); return pin_name; } else {

•           return msm_pinctrl_pins[selector - 150];
  

•           return qcom_pinctrl_pins[selector - 150];
    }
  

}

static unsigned int apq8096_get_function_mux(unsigned int selector) {

•   return msm_pinctrl_functions[selector].val;
  

•   return qcom_pinctrl_functions[selector].val;
  

}

-static const struct msm_pinctrl_data apq8096_data = { +static const struct qcom_pinctrl_data apq8096_data = { .pin_data = { .pin_count = 157, },

•   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  

•   .functions_count = ARRAY_SIZE(qcom_pinctrl_functions),
    .get_function_name = apq8096_get_function_name,
    .get_function_mux = apq8096_get_function_mux,
    .get_pin_name = apq8096_get_pin_name,
  

};

-static const struct udevice_id msm_pinctrl_ids[] = { +static const struct udevice_id qcom_pinctrl_ids[] = { { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data }, { /* Sentinal */ } }; @@ -65,7 +65,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { U_BOOT_DRIVER(pinctrl_apq8096) = { .name = "pinctrl_apq8096", .id = UCLASS_NOP,

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

•   .of_match       = qcom_pinctrl_ids,
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .bind           = qcom_pinctrl_bind,
  

}; diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 2d99f99e1e45..2081d6d86f82 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -14,7 +14,7 @@

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); -static const struct pinctrl_function msm_pinctrl_functions[] = { +static const struct pinctrl_function qcom_pinctrl_functions[] = { {"gpio", 0}, {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */ @@ -30,7 +30,7 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { static const char *ipq4019_get_function_name(struct udevice *dev, unsigned int selector) {

•   return msm_pinctrl_functions[selector].name;
  

•   return qcom_pinctrl_functions[selector].name;
  

}

static const char *ipq4019_get_pin_name(struct udevice *dev, @@ -42,18 +42,18 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,

static unsigned int ipq4019_get_function_mux(unsigned int selector) {

•   return msm_pinctrl_functions[selector].val;
  

•   return qcom_pinctrl_functions[selector].val;
  

}

-static const struct msm_pinctrl_data ipq4019_data = { +static const struct qcom_pinctrl_data ipq4019_data = { .pin_data = { .pin_count = 100, },

•   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  

•   .functions_count = ARRAY_SIZE(qcom_pinctrl_functions),
    .get_function_name = ipq4019_get_function_name,
    .get_function_mux = ipq4019_get_function_mux,
    .get_pin_name = ipq4019_get_pin_name,
  

};

-static const struct udevice_id msm_pinctrl_ids[] = { +static const struct udevice_id qcom_pinctrl_ids[] = { { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, { /* Sentinal */ } }; @@ -61,7 +61,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { U_BOOT_DRIVER(pinctrl_ipq4019) = { .name = "pinctrl_ipq4019", .id = UCLASS_NOP,

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

•   .of_match       = qcom_pinctrl_ids,
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .bind           = qcom_pinctrl_bind,
  

}; diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 92b35c198788..4f5ef5c14dd4 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -20,12 +20,12 @@

#include "pinctrl-qcom.h"

-#define MSM_PINCTRL_MAX_RESERVED_RANGES 32 +#define qcom_PINCTRL_MAX_RESERVED_RANGES 32

-struct msm_pinctrl_priv { +struct qcom_pinctrl_priv { phys_addr_t base;

•   struct msm_pinctrl_data *data;
  

•   u32 reserved_ranges[MSM_PINCTRL_MAX_RESERVED_RANGES * 2];
  

•   struct qcom_pinctrl_data *data;
  

•   u32 reserved_ranges[qcom_PINCTRL_MAX_RESERVED_RANGES * 2];
    int reserved_ranges_count;
  

};

@@ -37,37 +37,37 @@ struct msm_pinctrl_priv { #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) #define TLMM_GPIO_DISABLE BIT(9)

-static const struct pinconf_param msm_conf_params[] = { +static const struct pinconf_param qcom_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, };

-static int msm_get_functions_count(struct udevice *dev) +static int qcom_get_functions_count(struct udevice *dev) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
    return priv->data->functions_count;
  

}

-static int msm_get_pins_count(struct udevice *dev) +static int qcom_get_pins_count(struct udevice *dev) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
    return priv->data->pin_data.pin_count;
  

}

-static const char *msm_get_function_name(struct udevice *dev,

•                                    unsigned int selector)
  

+static const char *qcom_get_function_name(struct udevice *dev,

•                                     unsigned int selector)
  

{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
    return priv->data->get_function_name(dev, selector);
  

}

-static int msm_pinctrl_parse_ranges(struct udevice *dev) +static int qcom_pinctrl_parse_ranges(struct udevice *dev) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
    int count;
  
    if (ofnode_read_prop(dev_ofnode(dev), "gpio-reserved-ranges",
  

@@ -79,9 +79,9 @@ static int msm_pinctrl_parse_ranges(struct udevice *dev) /* Size is in bytes, but we're indexing by ints */ count /= 4;

•           if (count > MSM_PINCTRL_MAX_RESERVED_RANGES) {
  

•           if (count > qcom_PINCTRL_MAX_RESERVED_RANGES) {
                    dev_err(dev, "gpio-reserved-ranges must be less than %d (got %d)\n",
  

•                           MSM_PINCTRL_MAX_RESERVED_RANGES, count);
  

•                           qcom_PINCTRL_MAX_RESERVED_RANGES, count);
                    return -EINVAL;
            }
  
  

@@ -98,15 +98,15 @@ static int msm_pinctrl_parse_ranges(struct udevice *dev) return 0; }

-static int msm_pinctrl_probe(struct udevice *dev) +static int qcom_pinctrl_probe(struct udevice *dev) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
    int ret;
  
    priv->base = dev_read_addr(dev);
  

•   priv->data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
  

•   priv->data = (struct qcom_pinctrl_data *)dev_get_driver_data(dev);
  
  

•   ret = msm_pinctrl_parse_ranges(dev);
  

•   ret = qcom_pinctrl_parse_ranges(dev);
    if (ret) {
            printf("Couldn't parse reserved GPIO ranges!\n");
            return ret;
  

@@ -115,19 +115,19 @@ static int msm_pinctrl_probe(struct udevice *dev) return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; }

-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +static const char *qcom_get_pin_name(struct udevice *dev, unsigned int selector) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
    return priv->data->get_pin_name(dev, selector);
  

}

-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,

•                     unsigned int func_selector)
  

+static int qcom_pinmux_set(struct udevice *dev, unsigned int pin_selector,

•                      unsigned int func_selector)
  

{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev, pin_selector))
  

•   if (qcom_pinctrl_is_reserved(dev, pin_selector))
            return 0;
  
    clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
  

@@ -136,12 +136,12 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; }

-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,

•                      unsigned int param, unsigned int argument)
  

+static int qcom_pinconf_set(struct udevice *dev, unsigned int pin_selector,

•                       unsigned int param, unsigned int argument)
  

{

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
  
  

•   if (msm_pinctrl_is_reserved(dev, pin_selector))
  

•   if (qcom_pinctrl_is_reserved(dev, pin_selector))
            return 0;
  
    switch (param) {
  

@@ -165,22 +165,22 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; }

-struct pinctrl_ops msm_pinctrl_ops = {

•   .get_pins_count = msm_get_pins_count,
  

•   .get_pin_name = msm_get_pin_name,
  

+struct pinctrl_ops qcom_pinctrl_ops = {

•   .get_pins_count = qcom_get_pins_count,
  

•   .get_pin_name = qcom_get_pin_name,
    .set_state = pinctrl_generic_set_state,
  

•   .pinmux_set = msm_pinmux_set,
  

•   .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
  

•   .pinconf_params = msm_conf_params,
  

•   .pinconf_set = msm_pinconf_set,
  

•   .get_functions_count = msm_get_functions_count,
  

•   .get_function_name = msm_get_function_name,
  

•   .pinmux_set = qcom_pinmux_set,
  

•   .pinconf_num_params = ARRAY_SIZE(qcom_conf_params),
  

•   .pinconf_params = qcom_conf_params,
  

•   .pinconf_set = qcom_pinconf_set,
  

•   .get_functions_count = qcom_get_functions_count,
  

•   .get_function_name = qcom_get_function_name,
  

};

-int msm_pinctrl_bind(struct udevice *dev) +int qcom_pinctrl_bind(struct udevice *dev) { ofnode node = dev_ofnode(dev);

•   struct msm_pinctrl_data *data = (struct msm_pinctrl_data *)dev_get_driver_data(dev);
  

•   struct qcom_pinctrl_data *data = (struct qcom_pinctrl_data *)dev_get_driver_data(dev);
    struct driver *drv;
    struct udevice *pinctrl_dev;
    const char *name;
  

@@ -204,9 +204,9 @@ int msm_pinctrl_bind(struct udevice *dev) if (!name) return -EINVAL;

•   drv = lists_driver_lookup_name("gpio_msm");
  

•   drv = lists_driver_lookup_name("qcom_gpio");
    if (!drv) {
  

•           printf("Can't find gpio_msm driver\n");
  

•           printf("Can't find qcom_gpio driver\n");
            return -ENODEV;
    }
  
  

@@ -224,14 +224,14 @@ int msm_pinctrl_bind(struct udevice *dev) U_BOOT_DRIVER(qcom_pinctrl) = { .name = "qcom_pinctrl", .id = UCLASS_PINCTRL,

•   .priv_auto      = sizeof(struct msm_pinctrl_priv),
  

•   .ops            = &msm_pinctrl_ops,
  

•   .probe          = msm_pinctrl_probe,
  

•   .priv_auto      = sizeof(struct qcom_pinctrl_priv),
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .probe          = qcom_pinctrl_probe,
  

};

-bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin) +bool qcom_pinctrl_is_reserved(struct udevice *dev, unsigned int pin) {

•   struct msm_pinctrl_priv *priv = dev_get_priv(dev);
  

•   struct qcom_pinctrl_priv *priv = dev_get_priv(dev);
    unsigned int i, start;
  
    for (i = 0; i < priv->reserved_ranges_count; i += 2) {
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index efb6a44b1409..2aa8c80c696f 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -13,8 +13,8 @@

struct udevice;

-struct msm_pinctrl_data {

•   struct msm_pin_data pin_data;
  

+struct qcom_pinctrl_data {

•   struct qcom_pin_data pin_data;
    int functions_count;
    const char *(*get_function_name)(struct udevice *dev,
                                     unsigned int selector);
  

@@ -28,8 +28,8 @@ struct pinctrl_function { int val; };

-extern struct pinctrl_ops msm_pinctrl_ops; +extern struct pinctrl_ops qcom_pinctrl_ops;

-int msm_pinctrl_bind(struct udevice *dev); +int qcom_pinctrl_bind(struct udevice *dev);

#endif diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index ac00afa2a1f4..410cdbb23925 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -12,7 +12,7 @@

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); -static const char * const msm_pinctrl_pins[] = { +static const char * const qcom_pinctrl_pins[] = { "SDC1_RCLK", "SDC1_CLK", "SDC1_CMD", @@ -22,7 +22,7 @@ static const char * const msm_pinctrl_pins[] = { "SDC2_DATA", };

-static const struct pinctrl_function msm_pinctrl_functions[] = { +static const struct pinctrl_function qcom_pinctrl_functions[] = { {"blsp_uart2", 1}, {"rgmii_int", 1}, {"rgmii_ck", 1}, @@ -42,7 +42,7 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { static const char *qcs404_get_function_name(struct udevice *dev, unsigned int selector) {

•   return msm_pinctrl_functions[selector].name;
  

•   return qcom_pinctrl_functions[selector].name;
  

}

static const char *qcs404_get_pin_name(struct udevice *dev, @@ -52,24 +52,24 @@ static const char *qcs404_get_pin_name(struct udevice *dev, snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); return pin_name; } else {

•           return msm_pinctrl_pins[selector - 120];
  

•           return qcom_pinctrl_pins[selector - 120];
    }
  

}

static unsigned int qcs404_get_function_mux(unsigned int selector) {

•   return msm_pinctrl_functions[selector].val;
  

•   return qcom_pinctrl_functions[selector].val;
  

}

-static struct msm_pinctrl_data qcs404_data = { +static struct qcom_pinctrl_data qcs404_data = { .pin_data = { .pin_count = 126, },

•   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  

•   .functions_count = ARRAY_SIZE(qcom_pinctrl_functions),
    .get_function_name = qcs404_get_function_name,
    .get_function_mux = qcs404_get_function_mux,
    .get_pin_name = qcs404_get_pin_name,
  

};

-static const struct udevice_id msm_pinctrl_ids[] = { +static const struct udevice_id qcom_pinctrl_ids[] = { { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, { /* Sentinal */ } }; @@ -77,7 +77,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { U_BOOT_DRIVER(pinctrl_qcs404) = { .name = "pinctrl_qcs404", .id = UCLASS_NOP,

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

•   .of_match       = qcom_pinctrl_ids,
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .bind           = qcom_pinctrl_bind,
  

}; diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 9f0f4085ce2d..08cca602e94a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -3,7 +3,6 @@

• Qualcomm SDM845 pinctrl
• (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com

• • (C) Copyright 2023 Linaro Ltd.
  */

@@ -19,7 +18,7 @@ #define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data");

-static const struct pinctrl_function msm_pinctrl_functions[] = { +static const struct pinctrl_function qcom_pinctrl_functions[] = { {"qup9", 1}, {"gpio", 0}, }; @@ -60,7 +59,7 @@ static const unsigned int sdm845_pin_offsets[] = { static const char *sdm845_get_function_name(struct udevice *dev, unsigned int selector) {

•   return msm_pinctrl_functions[selector].name;
  

•   return qcom_pinctrl_functions[selector].name;
  

}

static const char *sdm845_get_pin_name(struct udevice *dev, @@ -72,21 +71,21 @@ static const char *sdm845_get_pin_name(struct udevice *dev,

static unsigned int sdm845_get_function_mux(unsigned int selector) {

•   return msm_pinctrl_functions[selector].val;
  

•   return qcom_pinctrl_functions[selector].val;
  

}

-static struct msm_pinctrl_data sdm845_data = { +static struct qcom_pinctrl_data sdm845_data = { .pin_data = { .pin_offsets = sdm845_pin_offsets, .pin_count = ARRAY_SIZE(sdm845_pin_offsets), },

•   .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
  

•   .functions_count = ARRAY_SIZE(qcom_pinctrl_functions),
    .get_function_name = sdm845_get_function_name,
    .get_function_mux = sdm845_get_function_mux,
    .get_pin_name = sdm845_get_pin_name,
  

};

-static const struct udevice_id msm_pinctrl_ids[] = { +static const struct udevice_id qcom_pinctrl_ids[] = { { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, { /* Sentinal */ } }; @@ -94,7 +93,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { U_BOOT_DRIVER(pinctrl_sdm845) = { .name = "pinctrl_sdm845", .id = UCLASS_NOP,

•   .of_match       = msm_pinctrl_ids,
  

•   .ops            = &msm_pinctrl_ops,
  

•   .bind           = msm_pinctrl_bind,
  

•   .of_match       = qcom_pinctrl_ids,
  

•   .ops            = &qcom_pinctrl_ops,
  

•   .bind           = qcom_pinctrl_bind,
  

}; diff --git a/include/qcom-gpio.h b/include/qcom-gpio.h index 490a1de55f89..758a6ad9234f 100644 --- a/include/qcom-gpio.h +++ b/include/qcom-gpio.h @@ -10,7 +10,7 @@ #include <asm/types.h> #include <stdbool.h>

-struct msm_pin_data { +struct qcom_pin_data { int pin_count; const unsigned int *pin_offsets; }; @@ -28,7 +28,7 @@ static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selecto struct udevice;

/**

• • msm_pinctrl_is_reserved() - Check if a pin lies in a reserved range

• • qcom_pinctrl_is_reserved() - Check if a pin lies in a reserved range
  • @dev: pinctrl device
  • @pin: Pin number

@@ -38,6 +38,6 @@ struct udevice;

• Call using dev_get_parent() from the GPIO device, it is a child of
• the pinctrl device.

*/ -bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin); +bool qcom_pinctrl_is_reserved(struct udevice *dev, unsigned int pin);

#endif /* _QCOM_GPIO_H_ */

-- 2.42.0