pá 25. 11. 2022 v 15:00 odesílatel Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com napsal:

When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address.

Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com

drivers/spi/zynqmp_gqspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 48eff777df..10f6b85cd3 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -662,7 +662,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) {

•   u32 addr;
  

•   unsigned long addr;
    u32 size;
    u32 actuallen = priv->len;
    u32 totallen = priv->len;
  

@@ -678,7 +678,9 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, totallen -= priv->len; /* Save remaining bytes length to read */ actuallen = priv->len; /* Actual number of bytes reading */

•           writel((unsigned long)buf, &dma_regs->dmadst);
  

•           writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst);
  

•           writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0),
  

•                                                   &dma_regs->dmadstmsb);
            writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
            writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
            addr = (unsigned long)buf;
  

-- 2.17.1

Applied. M