RE: [U-Boot-Users] omap2420h4 u-boot debugging CCS JTAG
Hello Komal,
Get an updated u-boot, a pull from the main head will result in something better in this regard.
I removed all the semi-confusing CONFIG_PARTIAL_SRAM references in the current images. I replaced it with much friendlier run time checks (is_running_in_sram, is_running_from_flash, is_running_in_sdram). This allows much easier debugging, and more understandable code.
As to your exact failure, I expect your problem is procedural at this stage. This bit of code when from the bin file, is expected to be running in flash, your disasm shows you already running in SDRAM, this is fine, but you would have had to load the elf file to get there...and this would imply your sdr and gel files have everything setup ok, and I bet this is not the case.
Regards, Richard W.
-----Original Message----- From: u-boot-users-admin@lists.sourceforge.net [mailto:u-boot-users- admin@lists.sourceforge.net] On Behalf Of Komal Shah Sent: Tuesday, February 01, 2005 11:18 PM To: u-boot-users@lists.sourceforge.net Subject: [U-Boot-Users] omap2420h4 u-boot debugging CCS JTAG
Richard,
I am trying to debug the omap2420h4 board u-boot through Code Composer Studio and xds560 JTAG.
I have compiled u-boot with CONFIG_PARTIAL_SRAM option.
CCS unable to debug after the STR instruction as "sp" becomes zero:
file: board/omap2420h4/platform.S:
#ifdef CONFIG_PARTIAL_SRAM ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ ...
SRAM_STACK: .word LOW_LEVEL_SRAM_STACK
Where LOW_LEVEL_SRAM_STACK equals to 0x4020FFFC .
As per the observation of registers and assembly code in CCS: ---------------snip------------------- 80E80570 01832100 ORREQ R2, R3, R0, LSL #2 80E80574 E1A03000 MOV R3, R0, R0 80E80578 E59FD028 LDR R13, 0x80E805A8 80E8057C E58DC000 STR R12, [R13] 80E80580 E1A0C00E MOV R12, R0, R14 ---------------snip-------------------
Where value of R13 becomes zero. And due to that it is failing at "STR R12, [R13]".
This seems to me the problem in accessing SRAM. Any hints on debugging the u-boot on the above case would be usefull for me on porting this code to the board based on similar core (omap2420).
===== ---Komal Shah
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--- "Woodruff, Richard" r-woodruff2@ti.com wrote:
Get an updated u-boot, a pull from the main head will result in something better in this regard.
Ok. I have checked out this code and using it for the debugging.
As to your exact failure, I expect your problem is procedural at this stage. This bit of code when
from > the bin file, is expected to be
running in flash, your disasm shows you already running in SDRAM, this is fine, but you would have had to load the elf file to get there...and
Yes. I am running from SDRAM. And loading the "elf" through CCS.
this would imply your sdr and gel files have everything setup ok, and I bet this is not the case.
This is the clock configuration I am using: ----------snip------------ APLLs clock input is 12MHz DPLL settings is 300 CORE_CLK_SRC is 600.0 MPU_FCLK is 300.0 DSP_FCLK is 200.0 DSP_ICLK is 100.0 DSP SYNC is DISABLE(BYPASS) IVA_FCLK is 200.0 IVA SYNC is DISABLE(BYPASS) GFX_FCLK is 50.0 L3_CLK is 100.0 L4_CLK is 100.0 Clock Configuration II ----------snip------------
Is there anything specific you are expecting for the gel files to do it?
And in debugging the new cvs code, it gives me following values for the registers after executing the following instruction:
80E80554 E59FD024 LDR R13, 0x80E80580
SP(R13) : 0x00000000 R13_SVC : 0x4020FFFC
value at 0x80E80580 is 0x4020FFFC.
But the next instruction
80E80558 E58DC000 STR R12, [R13]
is executed then CCS crashes with the following error:
"Can't single step Target Program: Error 0x00001821/-1025 Error during: command, execution, timeout, target, and error was encountered within the emulation driver (PTI), but the precise context is unknow".
So, I think it was the first access to SRAM, and it might had generated the exception ??
===== ---Komal Shah
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participants (2)
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Komal Shah -
Woodruff, Richard