[U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
---
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 5 +- 4 files changed, 388 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/pic32_flash.c
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c58841e..e3c6b9f 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -30,6 +30,12 @@ config ALTERA_QSPI
endmenu
+config FLASH_PIC32 + bool "Microchip PIC32 Flash driver" + help + This enables access to Microchip PIC32 internal non-CFI flash + chips through PIC32 Non-Volatile-Memory Controller. + source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 7f018a4..9380085 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c new file mode 100644 index 0000000..9a226b1 --- /dev/null +++ b/drivers/mtd/pic32_flash.c @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2015 + * Cristian Birsan cristian.birsan@microchip.com + * Purna Chandra Mandal purna.mandal@microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <flash.h> +#include <mach/pic32.h> +#include <wait_bit.h> + +/* NVM Controller registers */ +struct pic32_reg_nvm { + struct pic32_reg_atomic ctrl; + struct pic32_reg_atomic key; + struct pic32_reg_atomic addr; + struct pic32_reg_atomic data; +}; + +/* NVM operations */ +#define NVMOP_NOP 0 +#define NVMOP_WORD_WRITE 1 +#define NVMOP_PAGE_ERASE 4 + +/* NVM control bits */ +#define NVM_WR BIT(15) +#define NVM_WREN BIT(14) +#define NVM_WRERR BIT(13) +#define NVM_LVDERR BIT(12) + +/* NVM programming unlock register */ +#define LOCK_KEY 0x0 +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa + +/* PIC32 flash banks consist of number of pages, each page + * into number of row and rows are into number of words. + * Here we will maintain page information instead of sector. + */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static struct pic32_reg_nvm *nvm_regs_p; + +static inline void flash_initiate_operation(u32 nvmop) +{ + /* set operation */ + writel(nvmop, &nvm_regs_p->ctrl.raw); + + /* enable flash write */ + writel(NVM_WREN, &nvm_regs_p->ctrl.set); + + /* unlock sequence */ + writel(LOCK_KEY, &nvm_regs_p->key.raw); + writel(UNLOCK_KEY1, &nvm_regs_p->key.raw); + writel(UNLOCK_KEY2, &nvm_regs_p->key.raw); + + /* initiate operation */ + writel(NVM_WR, &nvm_regs_p->ctrl.set); +} + +static int flash_wait_till_busy(const char *func, ulong timeout) +{ + int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw, + NVM_WR, false, timeout, false); + + return ret ? ERR_TIMOUT : ERR_OK; +} + +static inline int flash_complete_operation(void) +{ + u32 v; + + v = readl(&nvm_regs_p->ctrl.raw); + if (v & NVM_WRERR) { + printf("Error in Block Erase - Lock Bit may be set!\n"); + flash_initiate_operation(NVMOP_NOP); + return ERR_PROTECTED; + } + + if (v & NVM_LVDERR) { + printf("Error in Block Erase - low-vol detected!\n"); + flash_initiate_operation(NVMOP_NOP); + return ERR_NOT_ERASED; + } + + /* disable flash write or erase operation */ + writel(NVM_WREN, &nvm_regs_p->ctrl.clr); + + return ERR_OK; +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ulong sect_start, sect_end, flags; + int prot, sect; + int rc; + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) { + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return ERR_UNKNOWN_FLASH_VENDOR; + } + + if ((s_first < 0) || (s_first > s_last)) { + printf("- no sectors to erase\n"); + return ERR_INVAL; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + /* erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + continue; + + /* disable interrupts */ + flags = disable_interrupts(); + + /* write destination page address (physical) */ + sect_start = virt_to_phys((void *)info->start[sect]); + writel(sect_start, &nvm_regs_p->addr.raw); + + /* page erase */ + flash_initiate_operation(NVMOP_PAGE_ERASE); + + /* wait */ + rc = flash_wait_till_busy(__func__, + CONFIG_SYS_FLASH_ERASE_TOUT); + + /* re-enable interrupts if necessary */ + if (flags) + enable_interrupts(); + + if (rc != ERR_OK) + return rc; + + rc = flash_complete_operation(); + if (rc != ERR_OK) + return rc; + + /* flash content is updated but cache might contain stale + * data, so invalidate dcache. + */ + sect_end = info->start[sect] + info->size / info->sector_count; + invalidate_dcache_range(info->start[sect], sect_end); + } + + printf(" done\n"); + return ERR_OK; +} + +int page_erase(flash_info_t *info, int sect) +{ + return 0; +} + +/* Write a word to flash */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong flags; + int rc; + + /* check if flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("Error, Flash not erased!\n"); + return ERR_NOT_ERASED; + } + + /* disable interrupts */ + flags = disable_interrupts(); + + /* update destination page address (physical) */ + writel(virt_to_phys(addr), &nvm_regs_p->addr.raw); + writel(data, &nvm_regs_p->data.raw); + + /* word write */ + flash_initiate_operation(NVMOP_WORD_WRITE); + + /* wait for operation to complete */ + rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT); + + /* re-enable interrupts if necessary */ + if (flags) + enable_interrupts(); + + if (rc != ERR_OK) + return rc; + + return flash_complete_operation(); +} + +/* Copy memory to flash, returns: + * ERR_OK - OK + * ERR_TIMOUT - write timeout + * ERR_NOT_ERASED - Flash not erased + */ +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, data, len = cnt; + int i, l, rc; + uchar *cp; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + l = addr - wp; + if (l != 0) { + data = 0; + for (i = 0, cp = (uchar *)wp; i < l; ++i, ++cp) + data = (data << 8) | *cp; + + for (; (i < 4) && (cnt > 0); ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; (cnt == 0) && (i < 4); ++i, ++cp) + data = (data << 8) | *cp; + + rc = write_word(info, wp, __swab32(data)); + if (rc) + goto out; + + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) + data = (data << 8) | *src++; + + rc = write_word(info, wp, __swab32(data)); + if (rc) + goto out; + + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + rc = ERR_OK; + goto out; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = (uchar *)wp; (i < 4) && (cnt > 0); ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + + for (; i < 4; ++i, ++cp) + data = (data << 8) | *cp; + + rc = write_word(info, wp, __swab32(data)); + +out: + /* flash content updated by nvm controller, + * but cache might have stale, so invalidate dcache. + */ + invalidate_dcache_range(addr, addr + len); + + printf(" done\n"); + return rc; +} + +void flash_print_info(flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_MCHP: + printf("Microchip Technology"); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_MCHP100T: + printf("Internal (8 Mbit, 64 x 16k)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +unsigned long flash_init(void) +{ + phys_addr_t flash_banks[] = CONFIG_SYS_FLASH_BANKS_LIST; + flash_info_t *info = &flash_info[0]; + ulong total_size = 0; + ulong sect_size; + ulong base; + int bank, sect; + + sect_size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT; + for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { + /* combined device & manufacturer code */ + info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + info->size = CONFIG_SYS_FLASH_SIZE; + + /* update sector (i.e page) info */ + base = (ulong)phys_to_virt(flash_banks[bank]); + for (sect = 0; sect < info->sector_count; sect++) { + info->start[sect] = base; + /* protect each sector by default */ + info->protect[sect] = 1; + base += sect_size; + } + total_size += info->size; + } + + /* NVM controller iobase */ + nvm_regs_p = ioremap(PIC32_NVM_BASE, sizeof(*nvm_regs_p)); + + /* disable flash write/erase operations */ + writel(NVM_WREN, &nvm_regs_p->ctrl.clr); + +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + return total_size; +} diff --git a/include/flash.h b/include/flash.h index f53ace7..c9aacd5 100644 --- a/include/flash.h +++ b/include/flash.h @@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
+#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */ + #define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000 - +#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ #define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Can you please add some more description to understand bit more, which kind of flash it is, parallel NOR?
thanks! -- Jagan.
On 03/10/2016 07:11 PM, Jagan Teki wrote:
On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Can you please add some more description to understand bit more, which kind of flash it is, parallel NOR?
Jagan,
These are parallel NOR flash divided into number of banks to allow erase/programming in one while fetch/execution continues from other. As the flash is memory-mapped code stored can be directly executed from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve code execution. These flash can also be used to store user data.
In PIC32 there are two sets of embedded flash memory of same type - boot flash, and program flash; early-boot-code executes from boot-flash and one bank of program-flash is used for u-boot, other bank for environment.
thanks!
Jagan.
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 5 +- 4 files changed, 388 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/pic32_flash.c
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c58841e..e3c6b9f 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -30,6 +30,12 @@ config ALTERA_QSPI
endmenu
+config FLASH_PIC32
bool "Microchip PIC32 Flash driver"
you should add: depends on MACH_PIC32
helpThis enables access to Microchip PIC32 internal non-CFI flashchips through PIC32 Non-Volatile-Memory Controller.source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 7f018a4..9380085 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c new file mode 100644 index 0000000..9a226b1 --- /dev/null +++ b/drivers/mtd/pic32_flash.c @@ -0,0 +1,377 @@ +/*
- Copyright (C) 2015
- Cristian Birsan cristian.birsan@microchip.com
- Purna Chandra Mandal purna.mandal@microchip.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <flash.h> +#include <mach/pic32.h> +#include <wait_bit.h>
+/* NVM Controller registers */ +struct pic32_reg_nvm {
struct pic32_reg_atomic ctrl;struct pic32_reg_atomic key;struct pic32_reg_atomic addr;struct pic32_reg_atomic data;+};
+/* NVM operations */ +#define NVMOP_NOP 0 +#define NVMOP_WORD_WRITE 1 +#define NVMOP_PAGE_ERASE 4
+/* NVM control bits */ +#define NVM_WR BIT(15) +#define NVM_WREN BIT(14) +#define NVM_WRERR BIT(13) +#define NVM_LVDERR BIT(12)
+/* NVM programming unlock register */ +#define LOCK_KEY 0x0 +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa
+/* PIC32 flash banks consist of number of pages, each page
- into number of row and rows are into number of words.
- Here we will maintain page information instead of sector.
- */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static struct pic32_reg_nvm *nvm_regs_p;
+static inline void flash_initiate_operation(u32 nvmop) +{
/* set operation */writel(nvmop, &nvm_regs_p->ctrl.raw);/* enable flash write */writel(NVM_WREN, &nvm_regs_p->ctrl.set);/* unlock sequence */writel(LOCK_KEY, &nvm_regs_p->key.raw);writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);/* initiate operation */writel(NVM_WR, &nvm_regs_p->ctrl.set);+}
+static int flash_wait_till_busy(const char *func, ulong timeout) +{
int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,NVM_WR, false, timeout, false);return ret ? ERR_TIMOUT : ERR_OK;+}
+static inline int flash_complete_operation(void) +{
u32 v;v = readl(&nvm_regs_p->ctrl.raw);if (v & NVM_WRERR) {printf("Error in Block Erase - Lock Bit may be set!\n");flash_initiate_operation(NVMOP_NOP);return ERR_PROTECTED;}if (v & NVM_LVDERR) {printf("Error in Block Erase - low-vol detected!\n");flash_initiate_operation(NVMOP_NOP);return ERR_NOT_ERASED;}/* disable flash write or erase operation */writel(NVM_WREN, &nvm_regs_p->ctrl.clr);return ERR_OK;+}
+int flash_erase(flash_info_t *info, int s_first, int s_last) +{
ulong sect_start, sect_end, flags;int prot, sect;int rc;if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {printf("Can't erase unknown flash type %08lx - aborted\n",info->flash_id);return ERR_UNKNOWN_FLASH_VENDOR;}if ((s_first < 0) || (s_first > s_last)) {printf("- no sectors to erase\n");return ERR_INVAL;}prot = 0;for (sect = s_first; sect <= s_last; ++sect) {if (info->protect[sect])prot++;}if (prot)printf("- Warning: %d protected sectors will not be erased!\n",prot);elseprintf("\n");/* erase on unprotected sectors */for (sect = s_first; sect <= s_last; sect++) {if (info->protect[sect])continue;/* disable interrupts */flags = disable_interrupts();/* write destination page address (physical) */sect_start = virt_to_phys((void *)info->start[sect]);writel(sect_start, &nvm_regs_p->addr.raw);/* page erase */flash_initiate_operation(NVMOP_PAGE_ERASE);/* wait */rc = flash_wait_till_busy(__func__,CONFIG_SYS_FLASH_ERASE_TOUT);/* re-enable interrupts if necessary */if (flags)enable_interrupts();if (rc != ERR_OK)return rc;rc = flash_complete_operation();if (rc != ERR_OK)return rc;/* flash content is updated but cache might contain stale* data, so invalidate dcache.*/
incorrect multi-line comment
sect_end = info->start[sect] + info->size / info->sector_count;invalidate_dcache_range(info->start[sect], sect_end);}printf(" done\n");return ERR_OK;+}
+int page_erase(flash_info_t *info, int sect) +{
return 0;+}
+/* Write a word to flash */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{
vu_long *addr = (vu_long *)dest;
you don't need a volatile pointer. Also virt_to_phys() is not meant to be used in a driver. An alternative is:
void *addr = (void *)CPHYSADDR(dest);
ulong flags;int rc;/* check if flash is (sufficiently) erased */if ((*addr & data) != data) {printf("Error, Flash not erased!\n");return ERR_NOT_ERASED;}/* disable interrupts */flags = disable_interrupts();/* update destination page address (physical) */writel(virt_to_phys(addr), &nvm_regs_p->addr.raw);writel(data, &nvm_regs_p->data.raw);/* word write */flash_initiate_operation(NVMOP_WORD_WRITE);/* wait for operation to complete */rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);/* re-enable interrupts if necessary */if (flags)enable_interrupts();if (rc != ERR_OK)return rc;return flash_complete_operation();+}
+/* Copy memory to flash, returns:
- ERR_OK - OK
- ERR_TIMOUT - write timeout
- ERR_NOT_ERASED - Flash not erased
- */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{
ulong wp, data, len = cnt;int i, l, rc;uchar *cp;wp = (addr & ~3); /* get lower word aligned address *//** handle unaligned start bytes*/l = addr - wp;if (l != 0) {data = 0;for (i = 0, cp = (uchar *)wp; i < l; ++i, ++cp)data = (data << 8) | *cp;for (; (i < 4) && (cnt > 0); ++i) {data = (data << 8) | *src++;--cnt;++cp;}for (; (cnt == 0) && (i < 4); ++i, ++cp)data = (data << 8) | *cp;rc = write_word(info, wp, __swab32(data));
why do you need to swap the data? Is the endianess of the flash controller or chip different from the one of the CPU? If so, you should explicitely state this with cpu_to_be32() or cpu_to_le32(). Also shouldn't the swapping be done in write_word()?
if (rc)goto out;wp += 4;}/** handle word aligned part*/while (cnt >= 4) {data = 0;for (i = 0; i < 4; ++i)data = (data << 8) | *src++;rc = write_word(info, wp, __swab32(data));if (rc)goto out;wp += 4;cnt -= 4;}if (cnt == 0) {rc = ERR_OK;goto out;}/** handle unaligned tail bytes*/
should be a single-line comment
data = 0;for (i = 0, cp = (uchar *)wp; (i < 4) && (cnt > 0); ++i, ++cp) {data = (data << 8) | *src++;--cnt;}for (; i < 4; ++i, ++cp)data = (data << 8) | *cp;rc = write_word(info, wp, __swab32(data));+out:
/* flash content updated by nvm controller,* but cache might have stale, so invalidate dcache.*/
incorrect multi-line comment
invalidate_dcache_range(addr, addr + len);printf(" done\n");return rc;+}
+void flash_print_info(flash_info_t *info) +{
int i;if (info->flash_id == FLASH_UNKNOWN) {printf("missing or unknown FLASH type\n");return;}switch (info->flash_id & FLASH_VENDMASK) {case FLASH_MAN_MCHP:printf("Microchip Technology");break;default:printf("Unknown Vendor ");break;}switch (info->flash_id & FLASH_TYPEMASK) {case FLASH_MCHP100T:printf("Internal (8 Mbit, 64 x 16k)\n");break;default:printf("Unknown Chip Type\n");break;}printf(" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);printf(" Sector Start Addresses:");for (i = 0; i < info->sector_count; ++i) {if ((i % 5) == 0)printf("\n ");printf(" %08lX%s", info->start[i],info->protect[i] ? " (RO)" : " ");}printf("\n");+}
+unsigned long flash_init(void) +{
phys_addr_t flash_banks[] = CONFIG_SYS_FLASH_BANKS_LIST;flash_info_t *info = &flash_info[0];ulong total_size = 0;ulong sect_size;ulong base;int bank, sect;sect_size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT;for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {/* combined device & manufacturer code */info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;info->size = CONFIG_SYS_FLASH_SIZE;/* update sector (i.e page) info */base = (ulong)phys_to_virt(flash_banks[bank]);for (sect = 0; sect < info->sector_count; sect++) {info->start[sect] = base;/* protect each sector by default */info->protect[sect] = 1;base += sect_size;}total_size += info->size;}/* NVM controller iobase */nvm_regs_p = ioremap(PIC32_NVM_BASE, sizeof(*nvm_regs_p));/* disable flash write/erase operations */writel(NVM_WREN, &nvm_regs_p->ctrl.clr);+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
/* monitor protection ON by default */flash_protect(FLAG_PROTECT_SET,CONFIG_SYS_MONITOR_BASE,CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,&flash_info[0]);+#endif
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */flash_protect(FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,&flash_info[0]);+#endif
return total_size;+} diff --git a/include/flash.h b/include/flash.h index f53ace7..c9aacd5 100644 --- a/include/flash.h +++ b/include/flash.h @@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
+#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */
#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000
+#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
1.8.3.1
adding new flash ID's should be done in a separate patch
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 5 +- 4 files changed, 388 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/pic32_flash.c
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c58841e..e3c6b9f 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -30,6 +30,12 @@ config ALTERA_QSPI
endmenu
+config FLASH_PIC32
bool "Microchip PIC32 Flash driver"you should add: depends on MACH_PIC32
ack. Will add,
helpThis enables access to Microchip PIC32 internal non-CFI flashchips through PIC32 Non-Volatile-Memory Controller.source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 7f018a4..9380085 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c new file mode 100644 index 0000000..9a226b1 --- /dev/null +++ b/drivers/mtd/pic32_flash.c @@ -0,0 +1,377 @@ +/*
- Copyright (C) 2015
- Cristian Birsan cristian.birsan@microchip.com
- Purna Chandra Mandal purna.mandal@microchip.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <flash.h> +#include <mach/pic32.h> +#include <wait_bit.h>
+/* NVM Controller registers */ +struct pic32_reg_nvm {
struct pic32_reg_atomic ctrl;struct pic32_reg_atomic key;struct pic32_reg_atomic addr;struct pic32_reg_atomic data;+};
+/* NVM operations */ +#define NVMOP_NOP 0 +#define NVMOP_WORD_WRITE 1 +#define NVMOP_PAGE_ERASE 4
+/* NVM control bits */ +#define NVM_WR BIT(15) +#define NVM_WREN BIT(14) +#define NVM_WRERR BIT(13) +#define NVM_LVDERR BIT(12)
+/* NVM programming unlock register */ +#define LOCK_KEY 0x0 +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa
+/* PIC32 flash banks consist of number of pages, each page
- into number of row and rows are into number of words.
- Here we will maintain page information instead of sector.
- */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static struct pic32_reg_nvm *nvm_regs_p;
+static inline void flash_initiate_operation(u32 nvmop) +{
/* set operation */writel(nvmop, &nvm_regs_p->ctrl.raw);/* enable flash write */writel(NVM_WREN, &nvm_regs_p->ctrl.set);/* unlock sequence */writel(LOCK_KEY, &nvm_regs_p->key.raw);writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);/* initiate operation */writel(NVM_WR, &nvm_regs_p->ctrl.set);+}
+static int flash_wait_till_busy(const char *func, ulong timeout) +{
int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,NVM_WR, false, timeout, false);return ret ? ERR_TIMOUT : ERR_OK;+}
+static inline int flash_complete_operation(void) +{
u32 v;v = readl(&nvm_regs_p->ctrl.raw);if (v & NVM_WRERR) {printf("Error in Block Erase - Lock Bit may be set!\n");flash_initiate_operation(NVMOP_NOP);return ERR_PROTECTED;}if (v & NVM_LVDERR) {printf("Error in Block Erase - low-vol detected!\n");flash_initiate_operation(NVMOP_NOP);return ERR_NOT_ERASED;}/* disable flash write or erase operation */writel(NVM_WREN, &nvm_regs_p->ctrl.clr);return ERR_OK;+}
+int flash_erase(flash_info_t *info, int s_first, int s_last) +{
ulong sect_start, sect_end, flags;int prot, sect;int rc;if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {printf("Can't erase unknown flash type %08lx - aborted\n",info->flash_id);return ERR_UNKNOWN_FLASH_VENDOR;}if ((s_first < 0) || (s_first > s_last)) {printf("- no sectors to erase\n");return ERR_INVAL;}prot = 0;for (sect = s_first; sect <= s_last; ++sect) {if (info->protect[sect])prot++;}if (prot)printf("- Warning: %d protected sectors will not be erased!\n",prot);elseprintf("\n");/* erase on unprotected sectors */for (sect = s_first; sect <= s_last; sect++) {if (info->protect[sect])continue;/* disable interrupts */flags = disable_interrupts();/* write destination page address (physical) */sect_start = virt_to_phys((void *)info->start[sect]);writel(sect_start, &nvm_regs_p->addr.raw);/* page erase */flash_initiate_operation(NVMOP_PAGE_ERASE);/* wait */rc = flash_wait_till_busy(__func__,CONFIG_SYS_FLASH_ERASE_TOUT);/* re-enable interrupts if necessary */if (flags)enable_interrupts();if (rc != ERR_OK)return rc;rc = flash_complete_operation();if (rc != ERR_OK)return rc;/* flash content is updated but cache might contain stale* data, so invalidate dcache.*/incorrect multi-line comment
ack.
sect_end = info->start[sect] + info->size / info->sector_count;invalidate_dcache_range(info->start[sect], sect_end);}printf(" done\n");return ERR_OK;+}
+int page_erase(flash_info_t *info, int sect) +{
return 0;+}
+/* Write a word to flash */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{
vu_long *addr = (vu_long *)dest;you don't need a volatile pointer. Also virt_to_phys() is not meant to be used in a driver. An alternative is:
void *addr = (void *)CPHYSADDR(dest);
ack.
ulong flags;int rc;/* check if flash is (sufficiently) erased */if ((*addr & data) != data) {printf("Error, Flash not erased!\n");return ERR_NOT_ERASED;}/* disable interrupts */flags = disable_interrupts();/* update destination page address (physical) */writel(virt_to_phys(addr), &nvm_regs_p->addr.raw);writel(data, &nvm_regs_p->data.raw);/* word write */flash_initiate_operation(NVMOP_WORD_WRITE);/* wait for operation to complete */rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);/* re-enable interrupts if necessary */if (flags)enable_interrupts();if (rc != ERR_OK)return rc;return flash_complete_operation();+}
+/* Copy memory to flash, returns:
- ERR_OK - OK
- ERR_TIMOUT - write timeout
- ERR_NOT_ERASED - Flash not erased
- */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{
ulong wp, data, len = cnt;int i, l, rc;uchar *cp;wp = (addr & ~3); /* get lower word aligned address *//** handle unaligned start bytes*/l = addr - wp;if (l != 0) {data = 0;for (i = 0, cp = (uchar *)wp; i < l; ++i, ++cp)data = (data << 8) | *cp;for (; (i < 4) && (cnt > 0); ++i) {data = (data << 8) | *src++;--cnt;++cp;}for (; (cnt == 0) && (i < 4); ++i, ++cp)data = (data << 8) | *cp;rc = write_word(info, wp, __swab32(data));why do you need to swap the data? Is the endianess of the flash controller or chip different from the one of the CPU? If so, you should explicitely state this with cpu_to_be32() or cpu_to_le32(). Also shouldn't the swapping be done in write_word()?
Good catch. Please note, both MIPS and flash controller is little-endian.
If you see, though not very obvious, char-byte-stream to word-data formatting is generating big-endian word. So to revert that __swab is used. Will fix the conversion so that generated word-data is little-endian itself at first hand.
if (rc)goto out;wp += 4;}/** handle word aligned part*/while (cnt >= 4) {data = 0;for (i = 0; i < 4; ++i)data = (data << 8) | *src++;rc = write_word(info, wp, __swab32(data));if (rc)goto out;wp += 4;cnt -= 4;}if (cnt == 0) {rc = ERR_OK;goto out;}/** handle unaligned tail bytes*/should be a single-line comment
ack.
data = 0;for (i = 0, cp = (uchar *)wp; (i < 4) && (cnt > 0); ++i, ++cp) {data = (data << 8) | *src++;--cnt;}for (; i < 4; ++i, ++cp)data = (data << 8) | *cp;rc = write_word(info, wp, __swab32(data));+out:
/* flash content updated by nvm controller,* but cache might have stale, so invalidate dcache.*/incorrect multi-line comment
ack.
invalidate_dcache_range(addr, addr + len);printf(" done\n");return rc;+}
+void flash_print_info(flash_info_t *info) +{
int i;if (info->flash_id == FLASH_UNKNOWN) {printf("missing or unknown FLASH type\n");return;}switch (info->flash_id & FLASH_VENDMASK) {case FLASH_MAN_MCHP:printf("Microchip Technology");break;default:printf("Unknown Vendor ");break;}switch (info->flash_id & FLASH_TYPEMASK) {case FLASH_MCHP100T:printf("Internal (8 Mbit, 64 x 16k)\n");break;default:printf("Unknown Chip Type\n");break;}printf(" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);printf(" Sector Start Addresses:");for (i = 0; i < info->sector_count; ++i) {if ((i % 5) == 0)printf("\n ");printf(" %08lX%s", info->start[i],info->protect[i] ? " (RO)" : " ");}printf("\n");+}
+unsigned long flash_init(void) +{
phys_addr_t flash_banks[] = CONFIG_SYS_FLASH_BANKS_LIST;flash_info_t *info = &flash_info[0];ulong total_size = 0;ulong sect_size;ulong base;int bank, sect;sect_size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT;for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) {/* combined device & manufacturer code */info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;info->size = CONFIG_SYS_FLASH_SIZE;/* update sector (i.e page) info */base = (ulong)phys_to_virt(flash_banks[bank]);for (sect = 0; sect < info->sector_count; sect++) {info->start[sect] = base;/* protect each sector by default */info->protect[sect] = 1;base += sect_size;}total_size += info->size;}/* NVM controller iobase */nvm_regs_p = ioremap(PIC32_NVM_BASE, sizeof(*nvm_regs_p));/* disable flash write/erase operations */writel(NVM_WREN, &nvm_regs_p->ctrl.clr);+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
/* monitor protection ON by default */flash_protect(FLAG_PROTECT_SET,CONFIG_SYS_MONITOR_BASE,CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,&flash_info[0]);+#endif
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */flash_protect(FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,&flash_info[0]);+#endif
return total_size;+} diff --git a/include/flash.h b/include/flash.h index f53ace7..c9aacd5 100644 --- a/include/flash.h +++ b/include/flash.h @@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
+#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */
#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
@@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000
+#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
1.8.3.1
adding new flash ID's should be done in a separate patch
ack. Will separate.
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++
BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help.
Jagan.
On 03/14/2016 07:16 PM, Jagan Teki wrote:
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++
BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help.
Will take up this activity [of supporting MTD] later on. For the time-being we are not using mtd on embedded flash, mainly using for environment and bootcode which are at well-known offset, size defined in include/configs/<board.h>.
On 14 March 2016 at 19:37, Purna Chandra Mandal purna.mandal@microchip.com wrote:
Jagan.
On 03/14/2016 07:16 PM, Jagan Teki wrote:
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++
BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help.
Will take up this activity [of supporting MTD] later on. For the time-being we are not using mtd on embedded flash, mainly using for environment and bootcode which are at well-known offset, size defined in include/configs/<board.h>.
I understand your concern, but It look very hard to maintain the new drivers with non-dm model.
My suggestions are better to add this on existing mtd(cfi or something) I guess ie "not possible" or move this driver to your soc or board code for time being till mtd uclass addition or write a fresh mtd dm driver.
thanks!
On 03/15/2016 05:35 PM, Jagan Teki wrote:
On 14 March 2016 at 19:37, Purna Chandra Mandal purna.mandal@microchip.com wrote:
Jagan.
On 03/14/2016 07:16 PM, Jagan Teki wrote:
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com:
PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com
drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++
BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help.
Will take up this activity [of supporting MTD] later on. For the time-being we are not using mtd on embedded flash, mainly using for environment and bootcode which are at well-known offset, size defined in include/configs/<board.h>.
I understand your concern, but It look very hard to maintain the new drivers with non-dm model.
If issue is only non-dm model I can add DM support with exception that it will not implement MTD functionality.
My suggestions are better to add this on existing mtd(cfi or something) I guess ie "not possible" or move this driver to your soc or board code for time being till mtd uclass addition or write a fresh mtd dm driver.
PIC32 flash devices are non CFI/JEDEC compliant so no way we can separate one flash chip from other. Even though flash devices are parallel erase and program on these flash chips are performed through NVM controller (serial interface). So we can't directly port the functionality on CFI driver.
I like the idea of adding this driver under arch/soc/ or board/. But that is where it was initially added, but based on review comment it is moved to drivers/mtd/.
Please suggest me a way!
thanks!
On 16 March 2016 at 16:37, Purna Chandra Mandal purna.mandal@microchip.com wrote:
On 03/15/2016 05:35 PM, Jagan Teki wrote:
On 14 March 2016 at 19:37, Purna Chandra Mandal purna.mandal@microchip.com wrote:
Jagan.
On 03/14/2016 07:16 PM, Jagan Teki wrote:
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal purna.mandal@microchip.com: > PIC32 embedded flash banks are memory mapped, directly read by CPU, > and programming (erase followed by write) operation on them are > handled by on-chip NVM controller. > Signed-off-by: Purna Chandra Mandal purna.mandal@microchip.com > --- > drivers/mtd/Kconfig | 6 + > drivers/mtd/Makefile | 1 + > drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++
BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help.
Will take up this activity [of supporting MTD] later on. For the time-being we are not using mtd on embedded flash, mainly using for environment and bootcode which are at well-known offset, size defined in include/configs/<board.h>.
I understand your concern, but It look very hard to maintain the new drivers with non-dm model.
If issue is only non-dm model I can add DM support with exception that it will not implement MTD functionality.
OK, Adding mtd dm is straight forward with registering MTD_UCLASS and mtd_info ops please check drivers/mtd/altera_qspi.c for more info.
Mean while I will come back again for my inputs.
My suggestions are better to add this on existing mtd(cfi or something) I guess ie "not possible" or move this driver to your soc or board code for time being till mtd uclass addition or write a fresh mtd dm driver.
PIC32 flash devices are non CFI/JEDEC compliant so no way we can separate one flash chip from other. Even though flash devices are parallel erase and program on these flash chips are performed through NVM controller (serial interface). So we can't directly port the functionality on CFI driver.
I like the idea of adding this driver under arch/soc/ or board/. But that is where it was initially added, but based on review comment it is moved to drivers/mtd/.
Please suggest me a way!
participants (4)
-
Daniel Schwierzeck -
Jagan Teki -
Jagan Teki -
Purna Chandra Mandal