[U-Boot] [PATCH v2 00/16] rk3399: Add redundant boot support
Boot redundancy is one of the key criteria for switch recovery or golden partition based on the bootcount value, which indeed very much needed in production systems on the fields.
This patchset support redundant boot on Rockchip rk3399.
To make full functional redundancy below features would require from U-Boot level. - bootcount, for counting number reboots - altboot - watchdog support, if SPL or U-Boot reset because of WDT - add CPUINFO for more understanding about how SoC and reset reason.
Changes for v2: - Handle TPL build for watchdog, if TPL won't enable - Fix comments for dw_wdt driver-model comments from Andy - Add Kconfig items for WDT_TPL - Support WDT on TPL as well - Use SYS_SOC for cpu-info
I would like, not to merge watchdog and bootcount on Mainline devboards since these features will mostly required on production devices but any comments, please share.
Any inputs? Jagan.
Jagan Teki (16): rockchip: Add cpu-info rockchip: rk3288/rk3399: Enable DISPLAY_CPUINFO arm: rockchip: Add common cru.h rockchip: Add rk3399 reset cause wdt: designware: Simplify is_enabled function wdt: designware: Simplify enable function wdt: dw: Add driver-model support wdt: dw: Rename to dw_wdt.c rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for watchdog wdt: Kconfig: Add WDT_DW entry wdt: Kconfig: Add TPL_WDT entry spl: Add watchdog support fot TPL watchdog: Handle TPL build with watchdog disabled [DO NOT MERGE] rk3399: rockpro64: Enable watchdog rockchip: rk3399: Add bootcount support [DO NOT MERGE] rk3399: rockpro64: Enable bootcount
arch/arm/dts/rk3399-u-boot.dtsi | 6 + arch/arm/include/asm/arch-rockchip/cru.h | 26 +++ .../include/asm/arch-rockchip/cru_rk3399.h | 10 +- arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 59 ++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 + arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- common/board_f.c | 2 +- common/spl/Kconfig | 9 + configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 4 +- configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - drivers/Makefile | 2 +- drivers/clk/rockchip/clk_rk3399.c | 36 ++-- drivers/ram/rockchip/sdram_rk3399.c | 10 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- drivers/watchdog/Kconfig | 15 ++ drivers/watchdog/Makefile | 2 +- drivers/watchdog/designware_wdt.c | 73 ------- drivers/watchdog/dw_wdt.c | 188 ++++++++++++++++++ include/configs/rk3399_common.h | 5 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_stratix10_socdk.h | 2 +- include/watchdog.h | 7 +- scripts/config_whitelist.txt | 1 - 46 files changed, 364 insertions(+), 136 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h create mode 100644 arch/arm/mach-rockchip/cpu-info.c delete mode 100644 drivers/watchdog/designware_wdt.c create mode 100644 drivers/watchdog/dw_wdt.c
Add cpu information for rockchip soc.
This would help to print the SoC family number, with associated temparature, clock and reason for reset etc.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/mach-rockchip/cpu-info.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 207f900011..76fc4942ee 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -20,6 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c new file mode 100644 index 0000000000..90ce65d9ff --- /dev/null +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> + +int print_cpuinfo(void) +{ + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + + /* TODO print operating temparature and clock */ + + return 0; +}
On 2019/8/27 上午2:20, Jagan Teki wrote:
Add cpu information for rockchip soc.
This would help to print the SoC family number, with associated temparature, clock and reason for reset etc.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/mach-rockchip/cpu-info.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 207f900011..76fc4942ee 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -20,6 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c new file mode 100644 index 0000000000..90ce65d9ff --- /dev/null +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
- (C) Copyright 2019 Amarula Solutions.
- Author: Jagan Teki jagan@amarulasolutions.com
- */
+#include <common.h>
+int print_cpuinfo(void) +{
- printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
- /* TODO print operating temparature and clock */
- return 0;
+}
RK3288 and RK3399 are now support cpu-info, so enable them by default.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 21 files changed, 21 deletions(-)
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 405fde0c80..68791cb417 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -12,7 +12,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0 CONFIG_CMD_GPIO=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index a0d215a5f1..2dae9e86b7 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 8b3692cdf0..4d05e0eb31 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 7ca522b479..1ebaf0dd72 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index d022631465..6b5a43219e 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index acfd91dbe7..b2bdc7c032 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index b71fd3a286..c3e3933d12 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 0a789872dc..394c60f076 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 1fee1be58a..2424711f6d 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 1d4c8f8a02..3571a7bccc 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 7375b758a2..69bf290a66 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 874ee5efb6..f51b908dd9 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 7b02c59f08..4896bb3070 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 7cfbd50c1e..8d49677e60 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index efa20d0800..34f6eb139d 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5d2a28a72d..1065d2d8fd 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 91e60da803..e0a35d8539 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index abcc53fc8e..99b18cf8f2 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 40ebad5abb..e05ea3e186 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 443f4d88b9..88e43c6d62 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -13,7 +13,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0 CONFIG_CMD_GPIO=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index c74c1457a7..68b680a417 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error.
So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-rockchip/cru.h | 14 ++++++++ .../include/asm/arch-rockchip/cru_rk3399.h | 10 +++--- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 36 +++++++++---------- drivers/ram/rockchip/sdram_rk3399.c | 10 +++--- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- 8 files changed, 46 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h new file mode 100644 index 0000000000..3d1927580f --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#ifndef _ROCKCHIP_CLOCK_H +#define _ROCKCHIP_CLOCK_H + +#if defined(CONFIG_ROCKCHIP_RK3399) +# include <asm/arch-rockchip/cru_rk3399.h> +#endif + +#endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 15eeb9c440..33ce190434 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -10,7 +10,7 @@
/* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { - struct rk3399_cru *cru; + struct rockchip_cru *cru; };
struct rk3399_pmuclk_priv { @@ -33,7 +33,7 @@ struct rk3399_pmucru { }; check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
-struct rk3399_cru { +struct rockchip_cru { u32 apll_l_con[6]; u32 reserved[2]; u32 apll_b_con[6]; @@ -65,7 +65,7 @@ struct rk3399_cru { u32 sdio0_con[2]; u32 sdio1_con[2]; }; -check_member(rk3399_cru, sdio1_con[1], 0x594); +check_member(rockchip_cru, sdio1_con[1], 0x594); #define MHz 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) @@ -107,9 +107,9 @@ enum apll_b_frequencies { APLL_B_600_MHZ, };
-void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq); -void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq);
#endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index f0411c0a21..a80a46f1db 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -8,7 +8,7 @@ #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h>
static int rockchip_get_cruclk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 863024d071..dafa142824 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void) void spl_board_init(void) { #if defined(SPL_GPIO_SUPPORT) - struct rk3399_cru *cru = rockchip_get_cru(); + struct rockchip_cru *cru = rockchip_get_cru();
/* * The RK3399 resets only 'almost all logic' (see also in the TRM diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index d9950c159b..b79935c774 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -14,7 +14,7 @@ #include <bitfield.h> #include <asm/io.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3399-cru.h> @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; }
-void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru, atclk_div << ATCLK_CORE_L_DIV_SHIFT); }
-void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq) { u32 aclkm_div; @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru, #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
-static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id) { u32 div, con;
@@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); }
-static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { int src_clk_div;
@@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = { .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, };
-static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id) { const struct spi_clkreg *spiclk = NULL; u32 div, val; @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); }
-static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { const struct spi_clkreg *spiclk = NULL; int src_clk_div; @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return rk3399_spi_get_clk(cru, clk_id); }
-static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; int aclk_vop = 198 * MHz; @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) return hz; }
-static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id) { u32 div, con;
@@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) return DIV_TO_RATE(GPLL_HZ, div); }
-static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru, ulong clk_id, ulong set_rate) { int src_clk_div; @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, return rk3399_mmc_get_clk(cru, clk_id); }
-static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate) { ulong ret;
@@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) }
#define PMUSGRF_DDR_RGN_CON16 0xff330040 -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, ulong set_rate) { struct pll_div dpll_cfg; @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, return set_rate; }
-static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val;
@@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) return DIV_TO_RATE(OSC_HZ, div); }
-static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) { int src_clk_div;
@@ -1108,7 +1108,7 @@ static struct clk_ops rk3399_clk_ops = { };
#ifdef CONFIG_SPL_BUILD -static void rkclk_init(struct rk3399_cru *cru) +static void rkclk_init(struct rockchip_cru *cru) { u32 aclk_div; u32 hclk_div; @@ -1225,15 +1225,15 @@ static int rk3399_clk_bind(struct udevice *dev) debug("Warning: No sysreset driver: ret=%d\n", ret); } else { priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3399_cru, + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3399_cru, + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, glb_srst_snd_value); sys_child->priv = priv; }
#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) - ret = offsetof(struct rk3399_cru, softrst_con[0]); + ret = offsetof(struct rockchip_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 21); if (ret) debug("Warning: software reset driver bind faile\n"); diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index ed70137ce7..2b5d51feb8 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,7 +14,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/pmu_rk3399.h> #include <asm/arch-rockchip/hardware.h> @@ -61,7 +61,7 @@ struct dram_info { u32 pwrup_srefresh_exit[2]; struct chan_info chan[2]; struct clk ddr_clk; - struct rk3399_cru *cru; + struct rockchip_cru *cru; struct rk3399_grf_regs *grf; struct rk3399_pmu_regs *pmu; struct rk3399_pmucru *pmucru; @@ -251,7 +251,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } }
-static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, u32 phy) { channel &= 0x1; @@ -262,7 +262,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, &cru->softrst_con[4]); }
-static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) { rkclk_ddr_reset(cru, channel, 1, 1); udelay(10); @@ -2498,7 +2498,7 @@ static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_cru *cru = dram->cru; + struct rockchip_cru *cru = dram->cru; struct rk3399_ddr_publ_regs *publ = chan->publ;
phy_pctrl_reset(cru, channel); diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index a93b73400b..a5b7ba69a8 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -18,7 +18,7 @@ #include <dm/uclass-internal.h> #include <linux/kernel.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/rockchip_mipi_dsi.h> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index bcd039b7bc..f9280e8607 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -18,7 +18,7 @@ #include <dm/uclass-internal.h> #include <linux/kernel.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
Add reset cause for rk3399 in common cpu-info file.
This would help to print the reset cause for various resets.
Common code for various rockchip reset cause will add it in future.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++++ arch/arm/mach-rockchip/cpu-info.c | 43 ++++++++++++++++++++++++ 2 files changed, 55 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 3d1927580f..e267a71ca6 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -11,4 +11,16 @@ # include <asm/arch-rockchip/cru_rk3399.h> #endif
+/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 90ce65d9ff..63d867fe78 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -5,10 +5,53 @@ */
#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru.h> +#include <asm/arch-rockchip/hardware.h> +#include <linux/err.h> + +static char *get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + char *cause = NULL; + + if (IS_ERR(cru)) + return cause; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + cause = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + cause = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + cause = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + cause = "WDOG"; + break; + default: + cause = "unknown reset"; + } + + /* + * Clear glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK); + + return cause; +}
int print_cpuinfo(void) { printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */
Right now the designware is_enabled function is using numeric number to check whether watchdog is enabled or not, so use register macro and check the same.
Cc: Chin Liang See clsee@altera.com Cc: Andy Shevchenko andriy.shevchenko@linux.intel.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/watchdog/designware_wdt.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index c668567c66..bd858f0608 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -45,9 +45,7 @@ static void designware_wdt_enable(void)
static unsigned int designware_wdt_is_enabled(void) { - unsigned long val; - val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); - return val & 0x1; + return readl(CONFIG_DW_WDT_BASE + DW_WDT_CR) & DW_WDT_CR_RMOD_OFFSET; }
#if defined(CONFIG_HW_WATCHDOG)
Simplify dw watchdog enable function by using proper macro and drop unwanted macros.
Cc: Chin Liang See clsee@altera.com Cc: Andy Shevchenko andriy.shevchenko@linux.intel.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/watchdog/designware_wdt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index bd858f0608..2979fda44e 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -14,7 +14,6 @@
#define DW_WDT_CR_EN_OFFSET 0x00 #define DW_WDT_CR_RMOD_OFFSET 0x01 -#define DW_WDT_CR_RMOD_VAL 0x00 #define DW_WDT_CRR_RESTART_VAL 0x76
/* @@ -38,9 +37,11 @@ static int designware_wdt_settimeout(unsigned int timeout)
static void designware_wdt_enable(void) { - writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | - (0x1 << DW_WDT_CR_EN_OFFSET)), - (CONFIG_DW_WDT_BASE + DW_WDT_CR)); + u32 val = readl(CONFIG_DW_WDT_BASE + DW_WDT_CR); + + /* Enable watchdog */ + val |= DW_WDT_CR_RMOD_OFFSET; + writel(val, CONFIG_DW_WDT_BASE + DW_WDT_CR); }
static unsigned int designware_wdt_is_enabled(void)
Add driver-model code for designware watchdog.
Cc: Chin Liang See clsee@altera.com Cc: Andy Shevchenko andriy.shevchenko@linux.intel.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/watchdog/designware_wdt.c | 118 +++++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index 2979fda44e..c822b1e36b 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -4,7 +4,6 @@ */
#include <common.h> -#include <watchdog.h> #include <asm/io.h> #include <asm/utils.h>
@@ -16,6 +15,121 @@ #define DW_WDT_CR_RMOD_OFFSET 0x01 #define DW_WDT_CRR_RESTART_VAL 0x76
+#define DW_WDT_MIN_TOP 0 +#define DW_WDT_MAX_TOP 15 +#define DW_WDT_TOPINIT_SHIFT 4 + +#ifdef CONFIG_WDT + +#include <dm.h> +#include <wdt.h> +#include <clk.h> + +struct dw_wdt { + void __iomem *regs; + unsigned long clk_rate; +}; + +static inline int dw_wdt_is_enabled(struct dw_wdt *dw) +{ + return readl(dw->regs + DW_WDT_CR) & DW_WDT_CR_RMOD_OFFSET; +} + +/* + * Set the watchdog time interval. + * Counter is 32 bit. + */ +static int dw_wdt_set_timeout(struct dw_wdt *dw, unsigned int timeout) +{ + int i, top_val; + + /* calculate the timeout range value */ + i = log_2_n_round_up(timeout * dw->clk_rate) - 16; + top_val = clamp_t(int, i, DW_WDT_MIN_TOP, DW_WDT_MAX_TOP); + + writel((top_val | (top_val << DW_WDT_TOPINIT_SHIFT)), + dw->regs + DW_WDT_TORR); + + return 0; +} + +static void dw_wdt_enable(struct dw_wdt *dw) +{ + u32 val = readl(dw->regs + DW_WDT_CR); + + /* Enable watchdog */ + val |= DW_WDT_CR_RMOD_OFFSET; + writel(val, dw->regs + DW_WDT_CR); +} + +static int dw_wdt_reset(struct udevice *dev) +{ + struct dw_wdt *dw = dev_get_priv(dev); + + if (dw_wdt_is_enabled(dw)) + writel(DW_WDT_CRR_RESTART_VAL, dw->regs + DW_WDT_CRR); + else + dw_wdt_enable(dw); + + return 0; +} + +static int dw_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct dw_wdt *dw = dev_get_priv(dev); + + dw_wdt_set_timeout(dw, timeout); + dw_wdt_enable(dw); + + return 0; +} + +static int dw_wdt_probe(struct udevice *dev) +{ + struct dw_wdt *dw = dev_get_priv(dev); + struct clk clk; + int ret; + + dw->regs = dev_remap_addr(dev); + if (!dw->regs) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + dw->clk_rate = clk_get_rate(&clk); + if (!dw->clk_rate) + return -EINVAL; + + dw_wdt_reset(dev); + + return 0; +} + +static const struct wdt_ops dw_wdt_ops = { + .reset = dw_wdt_reset, + .start = dw_wdt_start, +}; + +static const struct udevice_id dw_wdt_ids[] = { + { .compatible = "snps,dw-wdt" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dw_wdt) = { + .name = "dw_wdt", + .id = UCLASS_WDT, + .of_match = dw_wdt_ids, + .ops = &dw_wdt_ops, + .priv_auto_alloc_size = sizeof(struct dw_wdt), + .probe = dw_wdt_probe, +}; + +#else + +#include <watchdog.h> + /* * Set the watchdog time interval. * Counter is 32 bit. @@ -70,3 +184,5 @@ void hw_watchdog_init(void) hw_watchdog_reset(); } #endif + +#endif /* CONFIG_WDT */
- use dw instead of designware for driver file since Linux following the same. - add CONFIG macro start with CONFIG_WDT since the driver mode wdt drivers follow this.
Cc: Dinh Nguyen dinguyen@kernel.org Cc: Chin-Liang See clsee@altera.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- common/board_f.c | 2 +- drivers/watchdog/Makefile | 2 +- drivers/watchdog/{designware_wdt.c => dw_wdt.c} | 0 include/configs/socfpga_common.h | 2 +- include/configs/socfpga_stratix10_socdk.h | 2 +- scripts/config_whitelist.txt | 2 +- 6 files changed, 5 insertions(+), 5 deletions(-) rename drivers/watchdog/{designware_wdt.c => dw_wdt.c} (100%)
diff --git a/common/board_f.c b/common/board_f.c index 31181a9dc4..33e69c645a 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -97,7 +97,7 @@ static int init_func_watchdog_init(void) # if defined(CONFIG_HW_WATCHDOG) && \ (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || \ - defined(CONFIG_DESIGNWARE_WATCHDOG) || \ + defined(CONFIG_WDT_DW) || \ defined(CONFIG_IMX_WATCHDOG)) hw_watchdog_init(); puts(" Watchdog enabled\n"); diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef815..ecdc1ce54f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -13,7 +13,6 @@ endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o -obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o @@ -22,6 +21,7 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_DW) += dw_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/dw_wdt.c similarity index 100% rename from drivers/watchdog/designware_wdt.c rename to drivers/watchdog/dw_wdt.c diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 36b0ed5459..902909216d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -105,7 +105,7 @@ * L4 Watchdog */ #ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_WDT_DW #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 90ad8172e2..5d03bfd061 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -162,7 +162,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #ifdef CONFIG_SPL_BUILD #define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_WDT_DW #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 661c8b6427..35c56262ed 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -321,7 +321,7 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_DESIGNWARE_WATCHDOG +CONFIG_WDT_DW CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT
Add u-boot,dm-pre-reloc property for watchdog in rk3399-u-boot.dtsi so-that SPL can access watchdog.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2738a3889e..54286b585b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -3,6 +3,12 @@ * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com */
+/ { + watchdog@ff848000 { + u-boot,dm-pre-reloc; + }; +}; + &pmu { u-boot,dm-pre-reloc; };
Add Kconfig entry for CONFIG_WDT_DW, and it indeed depends on DM WDT.
So, it can be avialable on particular board defconfig only if they switch to use DW driver model code.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/watchdog/Kconfig | 8 ++++++++ scripts/config_whitelist.txt | 1 - 2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index a66a9bcbe2..8674633b90 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -90,6 +90,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_DW + bool "Synopsys DesignWare watchdog" + depends on WDT + default y if ROCKCHIP_RK3399 + help + Say Y here if to include support for the Synopsys DesignWare + watchdog timer found in many chips. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 35c56262ed..0618cb9047 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -321,7 +321,6 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_WDT_DW CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT
Add missing Kconfig entry for TPL_WDT.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/watchdog/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8674633b90..7c7f0c67a0 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -182,4 +182,11 @@ config SPL_WDT Enable driver model for watchdog timer in SPL. This is similar to CONFIG_WDT in U-Boot.
+config TPL_WDT + bool "Enable driver model for watchdog timer drivers in TPL" + depends on TPL_DM + help + Enable driver model for watchdog timer in TPL. + This is similar to CONFIG_WDT in U-Boot. + endmenu
Add support to build watchdog for TPL.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 660aa66d84..d4c5956b18 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1370,6 +1370,15 @@ config TPL_YMODEM_SUPPORT means of transmitting U-Boot over a serial line for using in TPL, with a checksum to ensure correctness.
+config TPL_WATCHDOG_SUPPORT + bool "Support watchdog drivers" + imply TPL_WDT if !HW_WATCHDOG + help + Enable support for watchdog drivers in TPL. A watchdog is + typically a hardware peripheral which can reset the system when it + detects no activity for a while (such as a software crash). This + enables the drivers in drivers/watchdog as part of an TPL build. + endif # TPL
config SPL_AT91_MCK_BYPASS diff --git a/drivers/Makefile b/drivers/Makefile index a4bb5e4975..82f9ac4445 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ +obj-$(CONFIG_$(SPL_TPL_)WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ @@ -53,7 +54,6 @@ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ -obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
This patch handle a checks to not enable watchdog in TPL, if TPL won't require to enable that.
This is useful, in rockchip platforms where watchdog would require in SPL and U-Boot proper and optional to have it in TPL. So, without this check, the TPL build failed to get the watchdog_reset function even though the watchdog is not enable for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- include/watchdog.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/watchdog.h b/include/watchdog.h index a4a4e8e614..f04e3e7c4d 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -51,9 +51,10 @@ int init_func_watchdog_reset(void); #if defined(__ASSEMBLY__) #define WATCHDOG_RESET bl watchdog_reset #else - /* Don't require the watchdog to be enabled in SPL */ - #if defined(CONFIG_SPL_BUILD) && \ - !defined(CONFIG_SPL_WATCHDOG_SUPPORT) + /* Don't require the watchdog to be enabled in TPL/SPL */ + #if ((defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_BUILD)) && \ + (!defined(CONFIG_TPL_WATCHDOG_SUPPORT) || \ + !defined(CONFIG_SPL_WATCHDOG_SUPPORT))) #define WATCHDOG_RESET() {} #else extern void watchdog_reset(void);
Enable watchdog in SPL and U-Boot proper for Rockpro64.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/rockpro64-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index e05ea3e186..5ff38efa53 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_WDT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y
Add bootcount support for Rockchip rk3399.
The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot.
Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-rockchip/Kconfig | 2 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++ include/configs/rk3399_common.h | 5 ++++- 3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5a80b4f0c..f3e4d72203 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -197,6 +197,8 @@ config ROCKCHIP_RK3399 imply TPL_CLK imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 6660d05349..68ac913bcb 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -91,6 +91,16 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000
+if BOOTCOUNT_LIMIT + +config BOOTCOUNT_BOOTLIMIT + default 3 + +config SYS_BOOTCOUNT_ADDR + default 0xff3100f0 # PMU_SYS_REG0 + +endif # BOOTCOUNT_LIMIT + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index a5e69b26ad..724ea4cbfc 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -64,7 +64,10 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + BOOTENV \ + "altbootcmd=" \ + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ + "run distro_bootcmd\0"
#endif
Enable bootcount support for Rockpro64 boards, this would help to use it for redundent boot.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/rockpro64-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 5ff38efa53..84d050d743 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -57,3 +57,4 @@ CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_WDT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_BOOTCOUNT_LIMIT=y
participants (2)
-
Jagan Teki -
Kever Yang