[U-Boot] [PATCH v5 00/11] Rewrite ARMv8 layerscape MMU
A recent debug revealed MMU for DDR shouldn't be enabled before DDR is initialized. Otherwise, a "normal memory" mapping may cause speculative access which may hang the system if accessing to DDR is not allowed at time. For Layerscape platforms, we have early MMU setup to speed up execution on emulators. The solution is to update MMU after DDR is ready. The same idea goes to final MMU as well. Actual DDR size is used to create the mappings. Non-exist address should be marked as "fault", i.e. invalid to avoid unwanted speculative access. Break-before-make process is followed when change is made for MMU.
Aside from the DDR size, reserved memory used for secure RAM and Management Complex (MC) makes things more complicated. To simplify it, a new global is added to track the reserved RAM. Secure RAM is excluded from U-Boot MMU. The reserved RAM is still mapped under U-Boot since we will need to copy data into it. Reserved RAM is excluded when device tree is fixed up so OS won't see it. An SoC level efi_add_known_memory() is implemented to add valid memory banks. DP-DDR is not added as memory.
Some MC configurations are moved to Kconfig.
Verified on LS2080ARDB with regular Linux boot and distro boot from USB.
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM in Kconfig Revise "help" message and add comment to explain how RESV_RAM is used.
Changes in v4: Revert the change of C bit in v3 patch.
Changes in v3: Instead of flushing d-cache, following the break-before-make process to change MMU table. Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: Add change to efi mapping Implement SoC level efi_add_known_memory(). DP-DDR is skipped so no need to add it as reserved memory later.
York Sun (11): armv8: Add global variable resv_ram armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig efi: Add a hook to allow adding memory mapping armv8: layerscape: Rewrite memory reservation driver: net: fsl-mc: Update calculation of MC RAM armv8: layerscape: Update MMU mapping with actual DDR size armv8: layerscape: Fix the sequence of changing MMU table armv8: ls2080a: Drop early MMU for SPL build armv8: mmu: Add a function to change mapping attributes armv8: layerscape: Update early MMU for DDR after initialization
arch/arm/cpu/armv8/cache_v8.c | 72 ++++- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 26 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 331 ++++++++++++++++++++-- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 - arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 2 +- arch/arm/include/asm/armv8/mmu.h | 5 + arch/arm/include/asm/global_data.h | 7 + arch/arm/include/asm/system.h | 1 + board/freescale/ls1012afrdm/ls1012afrdm.c | 34 +-- board/freescale/ls1012aqds/ls1012aqds.c | 34 +-- board/freescale/ls1012ardb/ls1012ardb.c | 34 +-- board/freescale/ls1043aqds/ddr.c | 29 -- board/freescale/ls1043aqds/ls1043aqds.c | 5 + board/freescale/ls1043ardb/ddr.c | 29 -- board/freescale/ls1043ardb/ls1043ardb.c | 7 - board/freescale/ls1046aqds/ddr.c | 29 -- board/freescale/ls1046aqds/ls1046aqds.c | 5 + board/freescale/ls1046ardb/ddr.c | 29 -- board/freescale/ls1046ardb/ls1046ardb.c | 7 - board/freescale/ls2080a/ddr.c | 55 ---- board/freescale/ls2080a/ls2080a.c | 17 +- board/freescale/ls2080aqds/ddr.c | 55 ---- board/freescale/ls2080aqds/ls2080aqds.c | 17 +- board/freescale/ls2080ardb/ddr.c | 55 ---- board/freescale/ls2080ardb/ls2080ardb.c | 26 +- cmd/bdinfo.c | 4 + common/board_f.c | 32 +-- drivers/net/fsl-mc/mc.c | 75 +---- include/configs/ls2080a_common.h | 2 - lib/efi_loader/efi_memory.c | 14 +- scripts/config_whitelist.txt | 2 - 33 files changed, 519 insertions(+), 540 deletions(-)
Use gd->arch.resv_ram to track reserved memory allocation.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM in Kconfig Revise "help" message and add comment to explain how RESV_RAM is used.
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 ++++++++++ arch/arm/include/asm/global_data.h | 7 +++++++ cmd/bdinfo.c | 4 ++++ 3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index adccdf1..3f3ccc7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -273,6 +273,16 @@ config SYS_FSL_SDHC_CLK_DIV clock, in another word SDHC_clk = Platform_clk / this_divider. endmenu
+config RESV_RAM + bool + help + Reserve memory from the top, tracked by gd->arch.resv_ram. This + reserved RAM can be used by special driver that resides in memory + after U-Boot exits. It's up to implementation to allocate and allow + access to this reserved memory. For example, the reserved RAM can + be at the high end of physical memory. The reserve RAM may be + excluded from memory bank(s) passed to OS, or marked as reserved. + config SYS_FSL_ERRATUM_A008336 bool
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index aee87cd..dfcbcce 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -59,6 +59,13 @@ struct arch_global_data { phys_addr_t secure_ram; unsigned long tlb_allocated; #endif +#ifdef CONFIG_RESV_RAM + /* + * Reserved RAM for memory resident, eg. Management Complex (MC) + * driver which continues to run after U-Boot exits. + */ + phys_addr_t resv_ram; +#endif
#ifdef CONFIG_ARCH_OMAP2 u32 omap_boot_device; diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ae3027a..19b8fd8 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -392,6 +392,10 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK); } #endif +#ifdef CONFIG_RESV_RAM + if (gd->arch.resv_ram) + print_num("Reserved ram", gd->arch.resv_ram); +#endif #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif
On 6 March 2017 at 10:02, York Sun york.sun@nxp.com wrote:
Use gd->arch.resv_ram to track reserved memory allocation.
Signed-off-by: York Sun york.sun@nxp.com
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM in Kconfig Revise "help" message and add comment to explain how RESV_RAM is used.
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 ++++++++++ arch/arm/include/asm/global_data.h | 7 +++++++ cmd/bdinfo.c | 4 ++++ 3 files changed, 21 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Use Kconfig option instead of config macro in header file. Clean up existing usage.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM.
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 3f3ccc7..df7c5ec 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -85,6 +85,14 @@ config FSL_LSCH3 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES
+config FSL_MC_ENET + bool "Management Complex network" + depends on ARCH_LS2080A + default y + select RESV_RAM + help + Enable Management Complex (MC) network + menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4bfd0ac..7719224 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -143,7 +143,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */ -#define CONFIG_FSL_MC_ENET /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f6c9101..ca3667d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1194,7 +1194,6 @@ CONFIG_FSL_LAYERSCAPE CONFIG_FSL_LBC CONFIG_FSL_LINFLEXUART CONFIG_FSL_MC9SDZ60 -CONFIG_FSL_MC_ENET CONFIG_FSL_MEMAC CONFIG_FSL_NFC_CHIPS CONFIG_FSL_NFC_SPARE_SIZE
Use Kconfig option instead of config macro in header file.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM.
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index df7c5ec..619e4cf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -311,3 +311,11 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929 bool + +config SYS_MC_RSV_MEM_ALIGN + hex "Management Complex reserved memory alignment" + depends on RESV_RAM + default 0x20000000 + help + Reserved memory needs to be aligned for MC to use. Default value + is 512MB. diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 7719224..4173d9a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -160,7 +160,6 @@ unsigned long long get_qixis_addr(void); */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) -#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif
/* Command line configuration */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ca3667d..66900e6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5043,7 +5043,6 @@ CONFIG_SYS_MCKR_VAL CONFIG_SYS_MCLINK_MAX CONFIG_SYS_MCMEM0_VAL CONFIG_SYS_MCMEM1_VAL -CONFIG_SYS_MC_RSV_MEM_ALIGN CONFIG_SYS_MDC1_PIN CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDC_PIN
Instead of adding all memory banks, add a hook so individual SoC/board can has its own implementation.
Signed-off-by: York Sun york.sun@nxp.com CC: Alexander Graf agraf@suse.de Reviewed-by: Alexander Graf agraf@suse.de
---
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: Add change to efi mapping
lib/efi_loader/efi_memory.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 95aa590..db2ae19 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -431,11 +431,8 @@ efi_status_t efi_get_memory_map(unsigned long *memory_map_size, return EFI_SUCCESS; }
-int efi_memory_init(void) +__weak void efi_add_known_memory(void) { - unsigned long runtime_start, runtime_end, runtime_pages; - unsigned long uboot_start, uboot_pages; - unsigned long uboot_stack_size = 16 * 1024 * 1024; int i;
/* Add RAM */ @@ -448,6 +445,15 @@ int efi_memory_init(void) efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, false); } +} + +int efi_memory_init(void) +{ + unsigned long runtime_start, runtime_end, runtime_pages; + unsigned long uboot_start, uboot_pages; + unsigned long uboot_stack_size = 16 * 1024 * 1024; + + efi_add_known_memory();
/* Add U-Boot */ uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM.
Changes in v4: None Changes in v3: None Changes in v2: Implement SoC level efi_add_known_memory(). DP-DDR is skipped so no need to add it as reserved memory later.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 198 +++++++++++++++++++++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 29 ---- board/freescale/ls1012aqds/ls1012aqds.c | 29 ---- board/freescale/ls1012ardb/ls1012ardb.c | 29 ---- board/freescale/ls1043aqds/ddr.c | 29 ---- board/freescale/ls1043ardb/ddr.c | 29 ---- board/freescale/ls1046aqds/ddr.c | 29 ---- board/freescale/ls1046ardb/ddr.c | 29 ---- board/freescale/ls2080a/ddr.c | 55 ------ board/freescale/ls2080a/ls2080a.c | 10 ++ board/freescale/ls2080aqds/ddr.c | 55 ------ board/freescale/ls2080aqds/ls2080aqds.c | 10 ++ board/freescale/ls2080ardb/ddr.c | 55 ------ board/freescale/ls2080ardb/ls2080ardb.c | 18 +- common/board_f.c | 32 +--- drivers/net/fsl-mc/mc.c | 16 +- 17 files changed, 233 insertions(+), 423 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..d0be335 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -524,15 +524,201 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size;
-#ifdef CONFIG_SYS_MEM_TOP_HIDE -#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ #ifdef CONFIG_FSL_MC_ENET + /* The start address of MC reserved memory needs to be aligned. */ ram_top -= mc_get_dram_block_size(); ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); #endif
- return ram_top; + return ram_size - ram_top; +} + +phys_size_t get_effective_memsize(void) +{ + phys_size_t ea_size, rem = 0; + + /* + * For ARMv8 SoCs, DDR memory is split into two or three regions. The + * first region is 2GB space at 0x8000_0000. If the memory extends to + * the second region (or the third region if applicable), the secure + * memory and Management Complex (MC) memory should be put into the + * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED + * is set to the size of first region so U-Boot doesn't relocate itself + * into higher address. Should DDR be configured to skip the first + * region, this function needs to be adjusted. + */ + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + ea_size = CONFIG_MAX_MEM_MAPPED; + rem = gd->ram_size - ea_size; + } else { + ea_size = gd->ram_size; + } + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* Check if we have enough space for secure memory */ + if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { + rem -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else { + if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { + ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + rem = 0; /* Presume MC requires more memory */ + } else { + printf("Error: No enough space for secure memory.\n"); + } + } +#endif + /* Check if we have enough memory for MC */ + if (rem < board_reserve_ram_top(rem)) { + /* Not enough memory in high region to reserve */ + if (ea_size > board_reserve_ram_top(rem)) + ea_size -= board_reserve_ram_top(rem); + else + printf("Error: No enough space for reserved memory.\n"); + } + + return ea_size; +} + +void dram_init_banksize(void) +{ +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + + /* + * gd->ram_size has the total size of DDR memory, less reserved secure + * memory. The DDR extends from low region to high region(s) presuming + * no hole is created with DDR configuration. gd->arch.secure_ram tracks + * the location of secure memory. gd->arch.resv_ram tracks the location + * of reserved memory for Management Complex (MC). + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + } +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else +#endif + { + if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[1].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else if (gd->bd->bi_dram[0].size > + CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[0].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } + } +#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ + +#ifdef CONFIG_FSL_MC_ENET + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } + } +#endif +} + +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) +void efi_add_known_memory(void) +{ + int i; + phys_addr_t ram_start, start; + phys_size_t ram_size; + u64 pages; + + /* Add RAM */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (i == 2) + continue; /* skip DP-DDR */ +#endif + ram_start = gd->bd->bi_dram[i].start; + ram_size = gd->bd->bi_dram[i].size; +#ifdef CONFIG_RESV_RAM + if (gd->arch.resv_ram >= ram_start && + gd->arch.resv_ram < ram_start + ram_size) + ram_size = gd->arch.resv_ram - ram_start; +#endif + start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, + false); + } } +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 83f5501..20b5c78 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */ -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_CCSR_SCFG_LE diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 789cae2..1f3adc1 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -91,32 +91,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 4281790..fbda504 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -166,32 +166,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index e3a8a76..2a85a1f 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -165,32 +165,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 7882a9a..c740062 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -127,32 +127,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 849f1d1..f90b85d 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -188,32 +188,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 4ea8b23..dc4d689 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index dd3b5d0..efe2ba6 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index e6130ec..5ed9e14 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 4f9b9c8..21ea70b 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -123,6 +123,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 9c6f477..0408c0f 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 73a61fd..ec53992 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -313,6 +313,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 959dfeb..2851d5b 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -172,58 +172,3 @@ phys_size_t initdram(int board_type)
return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 02954ef..7a4c6a3 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -202,14 +202,6 @@ int misc_init_r(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n");
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - efi_add_memory_map(gd->bd->bi_dram[2].start, - gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -#endif - return 0; }
@@ -286,6 +278,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/common/board_f.c b/common/board_f.c index ae6cd85..7d1ede0 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -325,15 +325,6 @@ __weak ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top; }
-__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size) -{ -#ifdef CONFIG_SYS_MEM_TOP_HIDE - return ram_size - CONFIG_SYS_MEM_TOP_HIDE; -#else - return ram_size; -#endif -} - static int setup_dest_addr(void) { debug("Monitor len: %08lX\n", gd->mon_len); @@ -341,26 +332,19 @@ static int setup_dest_addr(void) * Ram is setup, size stored in gd !! */ debug("Ram size: %08lX\n", (ulong)gd->ram_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - /* Reserve memory for secure MMU tables, and/or security monitor */ - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; - /* - * Record secure memory location. Need recalcuate if memory splits - * into banks, or the ram base is not zero. - */ - gd->arch.secure_ram = gd->ram_size; -#endif +#if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This has been used - * by arch/powerpc exclusively. Now ARMv8 takes advantage of - * thie mechanism. If memory is split into banks, addresses - * need to be calculated. + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. */ - gd->ram_size = board_reserve_ram_top(gd->ram_size); - + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 079082a..231a6d5 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -714,21 +714,7 @@ int get_dpl_apply_status(void) */ u64 mc_get_dram_addr(void) { - u64 mc_ram_addr; - - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } - - return mc_ram_addr; + return gd->arch.resv_ram; }
/**
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation of MC memory blocks can be simplified. The MC RAM is guaranteed to be aligned by the reservation process.
Signed-off-by: York Sun york.sun@nxp.com CC: Priyanka Jain priyanka.jain@nxp.com ---
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
drivers/net/fsl-mc/mc.c | 59 +++++++------------------------------------------ 1 file changed, 8 insertions(+), 51 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 231a6d5..9f69d75 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -154,48 +154,6 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr, } #endif
-/* - * Calculates the values to be used to specify the address range - * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. - * It returns the highest 512MB-aligned address within the given - * address range, in '*aligned_base_addr', and the number of 256 MiB - * blocks in it, in 'num_256mb_blocks'. - */ -static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, - size_t mc_ram_size, - u64 *aligned_base_addr, - u8 *num_256mb_blocks) -{ - u64 addr; - u16 num_blocks; - - if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (num_blocks < 1 || num_blocks > 0xff) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - addr = (mc_private_ram_start_addr + mc_ram_size - 1) & - MC_RAM_BASE_ADDR_ALIGNMENT_MASK; - - if (addr < mc_private_ram_start_addr) { - printf("fsl-mc: ERROR: bad start address %#llx\n", - mc_private_ram_start_addr); - return -EFAULT; - } - - *aligned_base_addr = addr; - *num_256mb_blocks = num_blocks; - return 0; -} - static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id, struct eth_device *eth_dev) { @@ -550,17 +508,16 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t raw_image_size = 0; #endif struct mc_version mc_ver_info; - u64 mc_ram_aligned_base_addr; u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size();
- - error = calculate_mc_private_ram_params(mc_ram_addr, - mc_ram_size, - &mc_ram_aligned_base_addr, - &mc_ram_num_256mb_blocks); - if (error != 0) + mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; + if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + error = -EINVAL; + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); goto out; + }
/* * Management Complex cores should be held at reset out of POR. @@ -602,11 +559,11 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_aligned_base_addr | + reg_mcfbalr = (u32)mc_ram_addr | (mc_ram_num_256mb_blocks - 1); out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, - (u32)(mc_ram_aligned_base_addr >> 32)); + (u32)(mc_ram_addr >> 32)); out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
/*
On Mon, Mar 6, 2017 at 11:02 AM, York Sun york.sun@nxp.com wrote:
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation of MC memory blocks can be simplified. The MC RAM is guaranteed to be aligned by the reservation process.
Signed-off-by: York Sun york.sun@nxp.com CC: Priyanka Jain priyanka.jain@nxp.com
Seems reasonable.
Acked-by: Joe Hershberger joe.hershberger@ni.com
Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access.
Signed-off-by: York Sun york.sun@nxp.com ---
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 42 +++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d0be335..368bdcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -101,12 +101,50 @@ static inline void final_mmu_setup(void) { u64 tlb_addr_save = gd->arch.tlb_addr; unsigned int el = current_el(); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE int index; -#endif
mem_map = final_map;
+ /* Update mapping for DDR to actual size */ + for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { + /* + * Find the entry for DDR mapping and update the address and + * size. Zero-sized mapping will be skipped when creating MMU + * table. + */ + switch (final_map[index].virt) { + case CONFIG_SYS_FSL_DRAM_BASE1: + final_map[index].virt = gd->bd->bi_dram[0].start; + final_map[index].phys = gd->bd->bi_dram[0].start; + final_map[index].size = gd->bd->bi_dram[0].size; + break; +#ifdef CONFIG_SYS_FSL_DRAM_BASE2 + case CONFIG_SYS_FSL_DRAM_BASE2: +#if (CONFIG_NR_DRAM_BANKS >= 2) + final_map[index].virt = gd->bd->bi_dram[1].start; + final_map[index].phys = gd->bd->bi_dram[1].start; + final_map[index].size = gd->bd->bi_dram[1].size; +#else + final_map[index].size = 0; +#endif + break; +#endif +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + case CONFIG_SYS_FSL_DRAM_BASE3: +#if (CONFIG_NR_DRAM_BANKS >= 3) + final_map[index].virt = gd->bd->bi_dram[2].start; + final_map[index].phys = gd->bd->bi_dram[2].start; + final_map[index].size = gd->bd->bi_dram[2].size; +#else + final_map[index].size = 0; +#endif + break; +#endif + default: + break; + } + } + #ifdef CONFIG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) {
This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: None Changes in v4: Revert the change of C bit in v3 patch.
Changes in v3: Instead of flushing d-cache, following the break-before-make process to change MMU table.
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 368bdcd..d82f6d1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -181,21 +181,14 @@ static inline void final_mmu_setup(void) setup_pgtables(); gd->arch.tlb_addr = tlb_addr_save;
- /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + /* Disable cache and MMU */ + dcache_disable(); /* TLBs are invalidated */ + invalidate_icache_all();
/* point TTBR to the new table */ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); - /* - * EL3 MMU is already enabled, just need to invalidate TLB to load the - * new table. The new table is compatible with the current table, if - * MMU somehow walks through the new table before invalidation TLB, - * it still works. So we don't need to turn off MMU here. - * When EL2 MMU table is created by calling this function, MMU needs - * to be enabled. - */ + set_sctlr(get_sctlr() | CR_M); }
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: None Changes in v4: None Changes in v3: Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1dabdbb..73a8680 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -45,9 +45,6 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A - arch_cpu_init(); -#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
This looks stupid. Why don't you just keep it enabled between SPL and U-Boot ? That'd be much more logical and sensible ...
Changes in v5: None Changes in v4: None Changes in v3: Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1dabdbb..73a8680 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -45,9 +45,6 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A
- arch_cpu_init();
-#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A
On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
This looks stupid. Why don't you just keep it enabled between SPL and U-Boot ? That'd be much more logical and sensible ...
Mark,
We are probably the only one using early MMU to speed up execution on emulators. I only noticed recently the cache/MMU wasn't enabled for most ARMv8 layerscape SoCs for SPL, except LS2080A (which is where we started). During recent debug, I learned the process of break-before-make process should be strictly followed when changing MMU. The normal boot part surely creates MMU tables. If the SPL also creates MMU table and enables cache, then we need to flush cache and disable MMU before the normal boot part begins to run. Instead of dealing all these steps just for LS2080A, I figure it would be a lot easier to drop it as I proposed in this patch.
York
Changes in v5: None Changes in v4: None Changes in v3: Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1dabdbb..73a8680 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -45,9 +45,6 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A
- arch_cpu_init();
-#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A
On 03/07/2017 05:31 AM, york sun wrote:
On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
This looks stupid. Why don't you just keep it enabled between SPL and U-Boot ? That'd be much more logical and sensible ...
Mark,
We are probably the only one using early MMU to speed up execution on emulators. I only noticed recently the cache/MMU wasn't enabled for most ARMv8 layerscape SoCs for SPL, except LS2080A (which is where we started). During recent debug, I learned the process of break-before-make process should be strictly followed when changing MMU.
I don't think I understand this part.
The normal boot part surely creates MMU tables. If the SPL also creates MMU table and enables cache, then we need to flush cache and disable MMU before the normal boot part begins to run. Instead of dealing all these steps just for LS2080A, I figure it would be a lot easier to drop it as I proposed in this patch.
But then this is a step back and makes the whole platform slower, right?
York
Changes in v5: None Changes in v4: None Changes in v3: Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1dabdbb..73a8680 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -45,9 +45,6 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A
- arch_cpu_init();
-#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A
On 03/06/2017 10:36 PM, Marek Vasut wrote:
On 03/07/2017 05:31 AM, york sun wrote:
On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
This looks stupid. Why don't you just keep it enabled between SPL and U-Boot ? That'd be much more logical and sensible ...
Mark,
We are probably the only one using early MMU to speed up execution on emulators. I only noticed recently the cache/MMU wasn't enabled for most ARMv8 layerscape SoCs for SPL, except LS2080A (which is where we started). During recent debug, I learned the process of break-before-make process should be strictly followed when changing MMU.
I don't think I understand this part.
Marek,
Let me explain in detail. When we started to port U-Boot to the very first ARMv8 Layerscape SoC, we use hardware emulator (we still use emulator today) which runs very very slow, like 800KHz slow. It takes long long time to see the first message on the console. So we enabled MMU and cache very early to dramatically improve the booting speed. We are talking about booting up U-Boot in minutes vs 20~30 minutes. It improves productivity a lot. Since we are still using emulators for new SoCs, I think we should keep this feature.
That being said, the early MMU table is small and simple, residing in internal SRAM. It is necessary to create a new complete table after U-Boot relocates to DDR. Switching MMU table requires the cache to be flushed and disabling and re-enabling MMU at some point to avoid a race condition. I only learned this break-before-make rule should be strictly enforced recently.
For SPL boot, if the MMU/cache is enabled in SPL build, the normal boot part still goes through creating an early MMU, the same steps as booting from NOR flash. We have to deal with changing early MMU table with the same setup. This is troublesome and unnecessary.
The normal boot part surely creates MMU tables. If the SPL also creates MMU table and enables cache, then we need to flush cache and disable MMU before the normal boot part begins to run. Instead of dealing all these steps just for LS2080A, I figure it would be a lot easier to drop it as I proposed in this patch.
But then this is a step back and makes the whole platform slower, right?
Yes, but not noticeable on the real hardware. The most time we spend on the SPL is to initialize DDR. It can take up to seconds with ECC enabled. Dropping the MMU/cache does slow down a little bit, but not a lot. For Layerscape SoCs, the SPL image is loaded into internal SRAM which runs pretty fast.
Beside, LS2080A is the only SoC with MMU/cache enabled for SPL. We have many other SoCs in the same Layerscape family not enabling MMU/cache for SPL and we didn't notice the performance impact. It is actually cleaner to make all of them consistent.
York
On 03/07/2017 05:45 PM, york sun wrote:
On 03/06/2017 10:36 PM, Marek Vasut wrote:
On 03/07/2017 05:31 AM, york sun wrote:
On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators.
Signed-off-by: York Sun york.sun@nxp.com
This looks stupid. Why don't you just keep it enabled between SPL and U-Boot ? That'd be much more logical and sensible ...
Mark,
We are probably the only one using early MMU to speed up execution on emulators. I only noticed recently the cache/MMU wasn't enabled for most ARMv8 layerscape SoCs for SPL, except LS2080A (which is where we started). During recent debug, I learned the process of break-before-make process should be strictly followed when changing MMU.
I don't think I understand this part.
Marek,
Let me explain in detail. When we started to port U-Boot to the very first ARMv8 Layerscape SoC, we use hardware emulator (we still use emulator today) which runs very very slow, like 800KHz slow. It takes long long time to see the first message on the console. So we enabled MMU and cache very early to dramatically improve the booting speed. We are talking about booting up U-Boot in minutes vs 20~30 minutes. It improves productivity a lot. Since we are still using emulators for new SoCs, I think we should keep this feature.
That being said, the early MMU table is small and simple, residing in internal SRAM. It is necessary to create a new complete table after U-Boot relocates to DDR. Switching MMU table requires the cache to be flushed and disabling and re-enabling MMU at some point to avoid a race condition. I only learned this break-before-make rule should be strictly enforced recently.
For SPL boot, if the MMU/cache is enabled in SPL build, the normal boot part still goes through creating an early MMU, the same steps as booting from NOR flash. We have to deal with changing early MMU table with the same setup. This is troublesome and unnecessary.
Ha, OK, thanks for the explanation.
The normal boot part surely creates MMU tables. If the SPL also creates MMU table and enables cache, then we need to flush cache and disable MMU before the normal boot part begins to run. Instead of dealing all these steps just for LS2080A, I figure it would be a lot easier to drop it as I proposed in this patch.
But then this is a step back and makes the whole platform slower, right?
Yes, but not noticeable on the real hardware. The most time we spend on the SPL is to initialize DDR. It can take up to seconds with ECC enabled. Dropping the MMU/cache does slow down a little bit, but not a lot. For Layerscape SoCs, the SPL image is loaded into internal SRAM which runs pretty fast.
Beside, LS2080A is the only SoC with MMU/cache enabled for SPL. We have many other SoCs in the same Layerscape family not enabling MMU/cache for SPL and we didn't notice the performance impact. It is actually cleaner to make all of them consistent.
OK
Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set.
Signed-off-by: York Sun york.sun@nxp.com ---
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/cache_v8.c | 72 +++++++++++++++++++++++++++++++++++++--- arch/arm/include/asm/armv8/mmu.h | 5 +++ arch/arm/include/asm/system.h | 1 + 3 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c5630c..bd1c3e0 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -501,7 +501,8 @@ static bool is_aligned(u64 addr, u64 size, u64 align) return !(addr & (align - 1)) && !(size & (align - 1)); }
-static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) +/* Use flag to indicate if attrs has more than d-cache attributes */ +static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) { int levelshift = level2shift(level); u64 levelsize = 1ULL << levelshift; @@ -509,8 +510,13 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
/* Can we can just modify the current level block PTE? */ if (is_aligned(start, size, levelsize)) { - *pte &= ~PMD_ATTRINDX_MASK; - *pte |= attrs; + if (flag) { + *pte &= ~PMD_ATTRMASK; + *pte |= attrs & PMD_ATTRMASK; + } else { + *pte &= ~PMD_ATTRINDX_MASK; + *pte |= attrs & PMD_ATTRINDX_MASK; + } debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
return levelsize; @@ -560,7 +566,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, u64 r;
for (level = 1; level < 4; level++) { - r = set_one_region(start, size, attrs, level); + /* Set d-cache attributes only */ + r = set_one_region(start, size, attrs, false, level); if (r) { /* PTE successfully replaced */ size -= r; @@ -581,6 +588,63 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(real_start, real_start + real_size); }
+/* + * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. + * The procecess is break-before-make. The target region will be marked as + * invalid during the process of changing. + */ +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +{ + int level; + u64 r, size, start; + + start = addr; + size = siz; + /* + * Loop through the address range until we find a page granule that fits + * our alignment constraints, then set it to "invalid". + */ + while (size > 0) { + for (level = 1; level < 4; level++) { + /* Set PTE to fault */ + r = set_one_region(start, size, PTE_TYPE_FAULT, true, + level); + if (r) { + /* PTE successfully invalidated */ + size -= r; + start += r; + break; + } + } + } + + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + __asm_invalidate_tlb_all(); + + /* + * Loop through the address range until we find a page granule that fits + * our alignment constraints, then set it to the new cache attributes + */ + start = addr; + size = siz; + while (size > 0) { + for (level = 1; level < 4; level++) { + /* Set PTE to new attributes */ + r = set_one_region(start, size, attrs, true, level); + if (r) { + /* PTE successfully updated */ + size -= r; + start += r; + break; + } + } + } + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + __asm_invalidate_tlb_all(); +} + #else /* CONFIG_SYS_DCACHE_OFF */
/* diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index e9b4cdb..a349903 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -53,6 +53,7 @@ #define PTE_TYPE_FAULT (0 << 0) #define PTE_TYPE_TABLE (3 << 0) #define PTE_TYPE_BLOCK (1 << 0) +#define PTE_TYPE_VALID (1 << 0)
#define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) @@ -77,6 +78,10 @@ */ #define PMD_ATTRINDX(t) ((t) << 2) #define PMD_ATTRINDX_MASK (7 << 2) +#define PMD_ATTRMASK (PTE_BLOCK_PXN | \ + PTE_BLOCK_UXN | \ + PMD_ATTRINDX_MASK | \ + PTE_TYPE_VALID)
/* * TCR flags. diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 766e929..9c3261c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -226,6 +226,7 @@ void protect_secure_region(void); void smp_kick_all_cpus(void);
void flush_l3_cache(void); +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
/* *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun york.sun@nxp.com
---
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 76 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +++- arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 2 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 5 ++ board/freescale/ls1012aqds/ls1012aqds.c | 5 ++ board/freescale/ls1012ardb/ls1012ardb.c | 5 ++ board/freescale/ls1043aqds/ls1043aqds.c | 5 ++ board/freescale/ls1043ardb/ls1043ardb.c | 7 --- board/freescale/ls1046aqds/ls1046aqds.c | 5 ++ board/freescale/ls1046ardb/ls1046ardb.c | 7 --- board/freescale/ls2080a/ls2080a.c | 7 --- board/freescale/ls2080aqds/ls2080aqds.c | 7 --- board/freescale/ls2080ardb/ls2080ardb.c | 8 +-- 13 files changed, 113 insertions(+), 38 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d82f6d1..7e66ee0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -753,3 +753,79 @@ void efi_add_known_memory(void) } } #endif + +/* + * Before DDR size is known, early MMU table have DDR mapped as device memory + * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" + * needs to be set for these mappings. + * If a special case configures DDR with holes in the mapping, the holes need + * to be marked as invalid. This is not implemented in this function. + */ +void update_early_mmu_table(void) +{ + if (!gd->arch.tlb_addr) + return; + + if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { + mmu_change_region_attr( + CONFIG_SYS_SDRAM_BASE, + gd->ram_size, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } else { + mmu_change_region_attr( + CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_DDR_BLOCK1_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE +#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" +#endif + if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + CONFIG_SYS_DDR_BLOCK2_SIZE) { + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK2_BASE, + CONFIG_SYS_DDR_BLOCK2_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK3_BASE, + gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE - + CONFIG_SYS_DDR_BLOCK2_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } else +#endif + { + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK2_BASE, + gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } + } +} + +__weak int dram_init(void) +{ + gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4ea4aea..bcf3e38 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -115,7 +115,11 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ @@ -130,7 +134,7 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #elif defined(CONFIG_FSL_LSCH2) @@ -158,12 +162,16 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h index d54eacd..d232bec 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h @@ -6,5 +6,5 @@
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ -#include <asm/arch-armv8/mmu.h> +void update_early_mmu_table(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 1f3adc1..25d22d2 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -12,6 +12,7 @@ #ifdef CONFIG_FSL_LS_PPA #include <asm/arch/ppa.h> #endif +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <hwconfig.h> #include <environment.h> @@ -48,6 +49,10 @@ int dram_init(void) mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif
return 0; } diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index fbda504..97ab340 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -14,6 +14,7 @@ #include <asm/arch/ppa.h> #endif #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -76,6 +77,10 @@ int dram_init(void) mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif
return 0; } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 2a85a1f..a23a23b 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -12,6 +12,7 @@ #ifdef CONFIG_FSL_LS_PPA #include <asm/arch/ppa.h> #endif +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> @@ -80,6 +81,10 @@ int dram_init(void) mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif
return 0; } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 8835a49..6507c09 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -153,6 +154,10 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif
return 0; } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index e213128..2333843 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -67,13 +67,6 @@ int checkboard(void) return 0; }
-int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 552365b..af3f70a 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -149,6 +150,10 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif
return 0; } diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 33a58cf..02b6c4c 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -56,13 +56,6 @@ int checkboard(void) return 0; }
-int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 21ea70b..9e7701d 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -49,13 +49,6 @@ void detail_board_ddr_info(void) #endif }
-int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index ec53992..8abf64a 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -254,13 +254,6 @@ void detail_board_ddr_info(void) #endif }
-int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 7a4c6a3..4c01f56 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -17,6 +17,7 @@ #include <environment.h> #include <efi_loader.h> #include <i2c.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <fsl_sec.h>
@@ -219,13 +220,6 @@ void detail_board_ddr_info(void) #endif }
-int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) {
On 03/06/2017 09:03 AM, York Sun wrote:
A recent debug revealed MMU for DDR shouldn't be enabled before DDR is initialized. Otherwise, a "normal memory" mapping may cause speculative access which may hang the system if accessing to DDR is not allowed at time. For Layerscape platforms, we have early MMU setup to speed up execution on emulators. The solution is to update MMU after DDR is ready. The same idea goes to final MMU as well. Actual DDR size is used to create the mappings. Non-exist address should be marked as "fault", i.e. invalid to avoid unwanted speculative access. Break-before-make process is followed when change is made for MMU.
Aside from the DDR size, reserved memory used for secure RAM and Management Complex (MC) makes things more complicated. To simplify it, a new global is added to track the reserved RAM. Secure RAM is excluded from U-Boot MMU. The reserved RAM is still mapped under U-Boot since we will need to copy data into it. Reserved RAM is excluded when device tree is fixed up so OS won't see it. An SoC level efi_add_known_memory() is implemented to add valid memory banks. DP-DDR is not added as memory.
Some MC configurations are moved to Kconfig.
Verified on LS2080ARDB with regular Linux boot and distro boot from USB.
Changes in v5: Rename RESV_RAM_TOP to RESV_RAM in Kconfig Revise "help" message and add comment to explain how RESV_RAM is used.
Changes in v4: Revert the change of C bit in v3 patch.
Changes in v3: Instead of flushing d-cache, following the break-before-make process to change MMU table. Add a patch to drop early MMU setup for LS2080A SPL build.
Changes in v2: Add change to efi mapping Implement SoC level efi_add_known_memory(). DP-DDR is skipped so no need to add it as reserved memory later.
York Sun (11): armv8: Add global variable resv_ram armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig efi: Add a hook to allow adding memory mapping armv8: layerscape: Rewrite memory reservation driver: net: fsl-mc: Update calculation of MC RAM armv8: layerscape: Update MMU mapping with actual DDR size armv8: layerscape: Fix the sequence of changing MMU table armv8: ls2080a: Drop early MMU for SPL build armv8: mmu: Add a function to change mapping attributes armv8: layerscape: Update early MMU for DDR after initialization
Applied to u-boot-fsl-qoriq master, awaiting upstream.
York
participants (5)
-
Joe Hershberger -
Marek Vasut -
Simon Glass -
York Sun -
york sun