There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image.

Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Jagan Teki jagan@edgeble.ai --- v3: - No change

v2: - Pre-req patch picked from [1] - Collect r-b tag

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230228213822.3583989-1-jo...

arch/arm/mach-rockchip/Kconfig | 2 +- configs/neu6a-io-rk3588_defconfig | 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/rock5b-rk3588_defconfig | 1 - doc/board/rockchip/rockchip.rst | 9 +++++++++ 5 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 0390431601f9..e5ac58ae60b5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -428,7 +428,7 @@ config TPL_ROCKCHIP_COMMON_BOARD

config ROCKCHIP_EXTERNAL_TPL bool "Use external TPL binary" - default y if ROCKCHIP_RK3568 + default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588 help Some Rockchip SoCs require an external TPL to initialize DRAM. Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index c9b22525315a..fb1ce4c1746f 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -62,5 +62,4 @@ CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y -# CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index e75383218320..af1374549ddc 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -69,5 +69,4 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y -# CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index f3026c7ea166..66199387195a 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -68,5 +68,4 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYSRESET=y -# CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b5563b8f7f9e..1f88d15aad2a 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -185,6 +185,15 @@ To build rk3568 boards: make evb-rk3568_defconfig make CROSS_COMPILE=aarch64-linux-gnu-

+To build rk3588 boards: + +.. code-block:: bash + + export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.27.elf + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin + make rock5b-rk3588_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- + Flashing --------

The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf v2.3. Mainline atf v2.3 contains an issue that could lead to a crash when it fails to parse the fdt blob being passed as the platform param. An issue that was fixed in atf v2.4.

The vendor TF-A seem to suffer from a similar issue, and this prevents booting when fdt blob is large enough to trigger this condition.

Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a NULL pointer instead of the fdt blob as the platform param.

This fixes booting Radxa ROCK 3A after recent sync of device tree.

Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v3: - No change

v2: - New patch

arch/arm/mach-rockchip/Kconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e5ac58ae60b5..d7e3784ba113 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -288,6 +288,7 @@ config ROCKCHIP_RK3568 select BOARD_LATE_INIT select DM_REGULATOR_FIXED select DM_RESET + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP imply MISC_INIT_R @@ -309,6 +310,7 @@ config ROCKCHIP_RK3588 select REGMAP select SYSCON select BOARD_LATE_INIT + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP imply MISC_INIT_R

Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay and kernel compression.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Simon Glass sjg@chromium.org --- v3: - No change

v2: - Drop parts that convert to use bootstd - Collect r-b tag

arch/arm/mach-rockchip/Kconfig | 2 ++ include/configs/rk3568_common.h | 7 ++++++- include/configs/rk3588_common.h | 7 ++++++- 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d7e3784ba113..517326c8c5be 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -290,6 +290,7 @@ config ROCKCHIP_RK3568 select DM_RESET imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply ROCKCHIP_COMMON_BOARD + imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R help @@ -312,6 +313,7 @@ config ROCKCHIP_RK3588 select BOARD_LATE_INIT imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply ROCKCHIP_COMMON_BOARD + imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R help diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index a5e1dde50888..d6b5e7d89022 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -17,10 +17,15 @@

#define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ "fdt_addr_r=0x0a100000\0" \ + "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "kernel_comp_size=0x2000000\0"

#include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index abd20139aaf3..b9f42717b751 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -16,10 +16,15 @@

#define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ "fdt_addr_r=0x0a100000\0" \ + "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "kernel_comp_size=0x2000000\0"

#include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \

Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM.

The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started.

This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL.

Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v3: - Patch picked from [1] - Collect r-b tag

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230317191638.2558279-3-jo...

arch/arm/include/asm/arch-rockchip/clock.h | 1 - .../include/asm/arch-rockchip/cru_rk3588.h | 19 ++- drivers/clk/rockchip/clk_rk3588.c | 125 ++++++++++++++++++ 3 files changed, 143 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 90e66c7da049..f002ebcb7ac1 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -194,6 +194,5 @@ int rockchip_get_clk(struct udevice **devp); * Return: 0 success, or error value */ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); -int rockchip_get_scmi_clk(struct udevice **devp);

#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index 3ea59e900861..7f4a90853929 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -11,12 +11,12 @@ #define KHz 1000 #define OSC_HZ (24 * MHz)

-#define CPU_PVTPLL_HZ (1008 * MHz) #define LPLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1500 * MHz) #define NPLL_HZ (850 * MHz) #define PPLL_HZ (1100 * MHz) +#define SPLL_HZ (702 * MHz)

/* RK3588 pll id */ enum rk3588_pll_id { @@ -447,5 +447,22 @@ enum { CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT, CLK_I2C_SEL_200M = 0, CLK_I2C_SEL_100M, + + /* SECURECRU_CLKSEL_CON01 */ + SCMI_HCLK_SD_SEL_SHIFT = 2, + SCMI_HCLK_SD_SEL_MASK = 3 << SCMI_HCLK_SD_SEL_SHIFT, + SCMI_HCLK_SD_SEL_150M = 0, + SCMI_HCLK_SD_SEL_100M, + SCMI_HCLK_SD_SEL_50M, + SCMI_HCLK_SD_SEL_24M, + + /* SECURECRU_CLKSEL_CON03 */ + SCMI_CCLK_SD_SEL_SHIFT = 12, + SCMI_CCLK_SD_SEL_MASK = 3 << SCMI_CCLK_SD_SEL_SHIFT, + SCMI_CCLK_SD_SEL_GPLL = 0, + SCMI_CCLK_SD_SEL_SPLL, + SCMI_CCLK_SD_SEL_24M, + SCMI_CCLK_SD_DIV_SHIFT = 6, + SCMI_CCLK_SD_DIV_MASK = 0x3f << SCMI_CCLK_SD_DIV_SHIFT, }; #endif diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index a7df553e8750..41e31b61a55b 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -9,6 +9,7 @@ #include <clk-uclass.h> #include <dm.h> #include <errno.h> +#include <scmi_protocols.h> #include <syscon.h> #include <asm/arch-rockchip/cru_rk3588.h> #include <asm/arch-rockchip/clock.h> @@ -1994,3 +1995,127 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = { .bind = rk3588_clk_bind, .probe = rk3588_clk_probe, }; + +#ifdef CONFIG_SPL_BUILD +#define SCRU_BASE 0xfd7d0000 + +static ulong rk3588_scru_clk_get_rate(struct clk *clk) +{ + u32 con, div, sel, parent; + + switch (clk->id) { + case SCMI_CCLK_SD: + con = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)); + sel = (con & SCMI_CCLK_SD_SEL_MASK) >> SCMI_CCLK_SD_SEL_SHIFT; + div = (con & SCMI_CCLK_SD_DIV_MASK) >> SCMI_CCLK_SD_DIV_SHIFT; + if (sel == SCMI_CCLK_SD_SEL_GPLL) + parent = GPLL_HZ; + else if (sel == SCMI_CCLK_SD_SEL_SPLL) + parent = SPLL_HZ; + else + parent = OSC_HZ; + return DIV_TO_RATE(parent, div); + case SCMI_HCLK_SD: + con = readl(SCRU_BASE + RK3588_CLKSEL_CON(1)); + sel = (con & SCMI_HCLK_SD_SEL_MASK) >> SCMI_HCLK_SD_SEL_SHIFT; + if (sel == SCMI_HCLK_SD_SEL_150M) + return 150 * MHz; + else if (sel == SCMI_HCLK_SD_SEL_100M) + return 100 * MHz; + else if (sel == SCMI_HCLK_SD_SEL_50M) + return 50 * MHz; + else + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rk3588_scru_clk_set_rate(struct clk *clk, ulong rate) +{ + u32 div, sel; + + switch (clk->id) { + case SCMI_CCLK_SD: + if ((OSC_HZ % rate) == 0) { + sel = SCMI_CCLK_SD_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if ((SPLL_HZ % rate) == 0) { + sel = SCMI_CCLK_SD_SEL_SPLL; + div = DIV_ROUND_UP(SPLL_HZ, rate); + } else { + sel = SCMI_CCLK_SD_SEL_GPLL; + div = DIV_ROUND_UP(GPLL_HZ, rate); + } + rk_clrsetreg(SCRU_BASE + RK3588_CLKSEL_CON(3), + SCMI_CCLK_SD_SEL_MASK | SCMI_CCLK_SD_DIV_MASK, + sel << SCMI_CCLK_SD_SEL_SHIFT | + (div - 1) << SCMI_CCLK_SD_DIV_SHIFT); + break; + case SCMI_HCLK_SD: + if (rate >= 150 * MHz) + sel = SCMI_HCLK_SD_SEL_150M; + else if (rate >= 100 * MHz) + sel = SCMI_HCLK_SD_SEL_100M; + else if (rate >= 50 * MHz) + sel = SCMI_HCLK_SD_SEL_50M; + else + sel = SCMI_HCLK_SD_SEL_24M; + rk_clrsetreg(SCRU_BASE + RK3588_CLKSEL_CON(1), + SCMI_HCLK_SD_SEL_MASK, + sel << SCMI_HCLK_SD_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rk3588_scru_clk_get_rate(clk); +} + +static const struct clk_ops rk3588_scru_clk_ops = { + .get_rate = rk3588_scru_clk_get_rate, + .set_rate = rk3588_scru_clk_set_rate, +}; + +U_BOOT_DRIVER(rockchip_rk3588_scru) = { + .name = "rockchip_rk3588_scru", + .id = UCLASS_CLK, + .ops = &rk3588_scru_clk_ops, +}; + +static int rk3588_scmi_spl_glue_bind(struct udevice *dev) +{ + ofnode node; + u32 protocol_id; + const char *name; + + dev_for_each_subnode(node, dev) { + if (!ofnode_is_enabled(node)) + continue; + + if (ofnode_read_u32(node, "reg", &protocol_id)) + continue; + + if (protocol_id != SCMI_PROTOCOL_ID_CLOCK) + continue; + + name = ofnode_get_name(node); + return device_bind_driver_to_node(dev, "rockchip_rk3588_scru", + name, node, NULL); + } + + return -ENOENT; +} + +static const struct udevice_id rk3588_scmi_spl_glue_ids[] = { + { .compatible = "arm,scmi-smc" }, + { } +}; + +U_BOOT_DRIVER(rk3588_scmi_spl_glue) = { + .name = "rk3588_scmi_spl_glue", + .id = UCLASS_NOP, + .of_match = rk3588_scmi_spl_glue_ids, + .bind = rk3588_scmi_spl_glue_bind, +}; +#endif

IO mux selection is not working correctly for all pins. Sync mux route data from linux to add any missing and update wrong trigger pins to fix this. Also apply the pull-up fix needed for GPIO0 D3-D6.

Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman jonas@kwiboo.se --- v3: - Patch picked from [1]

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230318233039.799975-1-jon...

drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++---------- 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 935aed9efc62..314edb5a6064 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -13,6 +13,12 @@ #include "pinctrl-rockchip.h"

static struct rockchip_mux_route_data rk3568_mux_route_data[] = { + MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ @@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ @@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ @@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ @@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ @@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, return ret; }

+ /* + * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, + * where that pull up value becomes 3. + */ + if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { + if (ret == 1) + ret = 3; + } + /* enable the write to the equivalent lower bits */ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);

The GPIO V2 controller on RK3568 and RK3588 works very similar to prior generation, main difference is the use of a write mask in the upper 16 bits and register address offset have changed.

GPIO_VER_ID is a new register at 0x0078 that is used to determine when the driver should use new or old register offsets and values. Earlier generation return 0x0 from this offset.

Refactor code and add support for the GPIO V2 controller used in RK3568 and RK3588.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com --- v3: - Patch picked from [1] - Collect r-b tag

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230319183949.1375997-1-jo...

drivers/gpio/rk_gpio.c | 112 ++++++++++++++++++++++++++++------------- 1 file changed, 76 insertions(+), 36 deletions(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index f7ad4d68b452..d9bde8f4f034 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -13,83 +13,118 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/gpio.h> #include <dm/pinctrl.h> -#include <dt-bindings/clock/rk3288-cru.h> +#include <dm/read.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#define SWPORT_DR 0x0000 +#define SWPORT_DDR 0x0004 +#define EXT_PORT 0x0050 +#define SWPORT_DR_L 0x0000 +#define SWPORT_DR_H 0x0004 +#define SWPORT_DDR_L 0x0008 +#define SWPORT_DDR_H 0x000C +#define EXT_PORT_V2 0x0070 +#define VER_ID_V2 0x0078

enum { ROCKCHIP_GPIOS_PER_BANK = 32, };

-#define OFFSET_TO_BIT(bit) (1UL << (bit)) - struct rockchip_gpio_priv { - struct rockchip_gpio_regs *regs; + void __iomem *regs; struct udevice *pinctrl; int bank; char name[2]; + u32 version; };

-static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) +static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) { struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; + u32 mask = BIT(offset), data;

- clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset)); + if (priv->version) + data = readl(priv->regs + EXT_PORT_V2); + else + data = readl(priv->regs + EXT_PORT);

- return 0; + return (data & mask) ? 1 : 0; }

-static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, - int value) +static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, + int value) { struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; - int mask = OFFSET_TO_BIT(offset); + u32 mask = BIT(offset), data = value ? mask : 0;

- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0); - setbits_le32(&regs->swport_ddr, mask); + if (priv->version && offset >= 16) + rk_clrsetreg(priv->regs + SWPORT_DR_H, mask >> 16, data >> 16); + else if (priv->version) + rk_clrsetreg(priv->regs + SWPORT_DR_L, mask, data); + else + clrsetbits_le32(priv->regs + SWPORT_DR, mask, data);

return 0; }

-static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) +static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) { struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; + u32 mask = BIT(offset); + + if (priv->version && offset >= 16) + rk_clrreg(priv->regs + SWPORT_DDR_H, mask >> 16); + else if (priv->version) + rk_clrreg(priv->regs + SWPORT_DDR_L, mask); + else + clrbits_le32(priv->regs + SWPORT_DDR, mask);

- return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0; + return 0; }

-static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, - int value) +static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; - int mask = OFFSET_TO_BIT(offset); + u32 mask = BIT(offset); + + rockchip_gpio_set_value(dev, offset, value);

- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0); + if (priv->version && offset >= 16) + rk_setreg(priv->regs + SWPORT_DDR_H, mask >> 16); + else if (priv->version) + rk_setreg(priv->regs + SWPORT_DDR_L, mask); + else + setbits_le32(priv->regs + SWPORT_DDR, mask);

return 0; }

static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) { -#ifdef CONFIG_SPL_BUILD - return -ENODATA; -#else struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; - bool is_output; + u32 mask = BIT(offset), data; int ret;

- ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); - if (ret) - return ret; - is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset); + if (CONFIG_IS_ENABLED(PINCTRL)) { + ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); + if (ret < 0) + return ret; + else if (ret != RK_FUNC_GPIO) + return GPIOF_FUNC; + } + + if (priv->version && offset >= 16) + data = readl(priv->regs + SWPORT_DDR_H) << 16; + else if (priv->version) + data = readl(priv->regs + SWPORT_DDR_L); + else + data = readl(priv->regs + SWPORT_DDR);

- return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; -#endif + return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; }

/* Simple SPL interface to GPIOs */ @@ -147,9 +182,12 @@ static int rockchip_gpio_probe(struct udevice *dev) int ret;

priv->regs = dev_read_addr_ptr(dev); - ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); - if (ret) - return ret; + + if (CONFIG_IS_ENABLED(PINCTRL)) { + ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); + if (ret) + return ret; + }

/* * If "gpio-ranges" is present in the devicetree use it to parse @@ -170,6 +208,8 @@ static int rockchip_gpio_probe(struct udevice *dev) priv->name[0] = 'A' + priv->bank; uc_priv->bank_name = priv->name;

+ priv->version = readl(priv->regs + VER_ID_V2); + return 0; }